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authorDave Airlie <airlied@redhat.com>2017-10-26 21:43:17 -0400
committerDave Airlie <airlied@redhat.com>2017-10-26 21:43:17 -0400
commitce485df43dc286f3ad96f9992b22e3974d051c44 (patch)
treeeb586142d3ba45378d0aa82b7fa75329e69bebb1
parent522dbb354e8b6149d69244b4cf745a3222ddbb05 (diff)
parent894e287b3dcc8bfc8d974f883dab3b5c66344089 (diff)
Merge tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
One fix for stable: - fix perf enable/disable ioctls for 32bits (Lionel) Plus GVT fixes: - Fix per_ctx_bb check (Zhenyu) - Fix GPU hang of Linux guest (Xion) - Refine MMIO_RING_F to check for presence of VCS2 ring (Zhi) * tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915/gvt: Adding ACTHD mmio read handler drm/i915/gvt: Extract mmio_read_from_hw() common function drm/i915/gvt: Refine MMIO_RING_F() drm/i915/gvt: properly check per_ctx bb valid state
-rw-r--r--drivers/gpu/drm/i915/gvt/cmd_parser.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/execlist.c3
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c70
-rw-r--r--drivers/gpu/drm/i915/gvt/reg.h3
-rw-r--r--drivers/gpu/drm/i915/gvt/scheduler.h1
5 files changed, 15 insertions, 65 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 21c36e256884..d4726a3358a4 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -2723,6 +2723,9 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2723 uint32_t per_ctx_start[CACHELINE_DWORDS] = {0}; 2723 uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2724 unsigned char *bb_start_sva; 2724 unsigned char *bb_start_sva;
2725 2725
2726 if (!wa_ctx->per_ctx.valid)
2727 return 0;
2728
2726 per_ctx_start[0] = 0x18800001; 2729 per_ctx_start[0] = 0x18800001;
2727 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; 2730 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2728 2731
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index 91b4300f3b39..e5320b4eb698 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -701,8 +701,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
701 CACHELINE_BYTES; 701 CACHELINE_BYTES;
702 workload->wa_ctx.per_ctx.guest_gma = 702 workload->wa_ctx.per_ctx.guest_gma =
703 per_ctx & PER_CTX_ADDR_MASK; 703 per_ctx & PER_CTX_ADDR_MASK;
704 704 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
705 WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
706 } 705 }
707 706
708 if (emulate_schedule_in) 707 if (emulate_schedule_in)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 2294466dd415..a5bed2e71b92 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1429,18 +1429,7 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1429 return 0; 1429 return 0;
1430} 1430}
1431 1431
1432static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, 1432static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1433 unsigned int offset, void *p_data, unsigned int bytes)
1434{
1435 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1436
1437 mmio_hw_access_pre(dev_priv);
1438 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1439 mmio_hw_access_post(dev_priv);
1440 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1441}
1442
1443static int instdone_mmio_read(struct intel_vgpu *vgpu,
1444 unsigned int offset, void *p_data, unsigned int bytes) 1433 unsigned int offset, void *p_data, unsigned int bytes)
1445{ 1434{
1446 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1435 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -1589,6 +1578,8 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1589 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1578 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1590 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1579 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1591 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1580 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1581 if (HAS_BSD2(dev_priv)) \
1582 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1592} while (0) 1583} while (0)
1593 1584
1594#define MMIO_RING_D(prefix, d) \ 1585#define MMIO_RING_D(prefix, d) \
@@ -1635,10 +1626,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1635#undef RING_REG 1626#undef RING_REG
1636 1627
1637#define RING_REG(base) (base + 0x6c) 1628#define RING_REG(base) (base + 0x6c)
1638 MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL); 1629 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1639 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
1640#undef RING_REG 1630#undef RING_REG
1641 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL); 1631 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1642 1632
1643 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); 1633 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1644 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1634 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
@@ -1648,7 +1638,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1648 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1638 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1649 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1639 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1650 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1640 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1651 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1641 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1652 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1642 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1653 1643
1654 /* RING MODE */ 1644 /* RING MODE */
@@ -1662,9 +1652,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1662 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1652 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1663 NULL, NULL); 1653 NULL, NULL);
1664 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1654 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1665 ring_timestamp_mmio_read, NULL); 1655 mmio_read_from_hw, NULL);
1666 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1656 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1667 ring_timestamp_mmio_read, NULL); 1657 mmio_read_from_hw, NULL);
1668 1658
1669 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1659 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1670 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1660 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
@@ -2411,9 +2401,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2411 struct drm_i915_private *dev_priv = gvt->dev_priv; 2401 struct drm_i915_private *dev_priv = gvt->dev_priv;
2412 int ret; 2402 int ret;
2413 2403
2414 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
2415 intel_vgpu_reg_imr_handler);
2416
2417 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2404 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2418 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2405 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2419 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2406 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
@@ -2476,68 +2463,34 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2476 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2463 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2477 intel_vgpu_reg_master_irq_handler); 2464 intel_vgpu_reg_master_irq_handler);
2478 2465
2479 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, 2466 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2480 F_CMD_ACCESS, NULL, NULL); 2467 mmio_read_from_hw, NULL);
2481 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2482
2483 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2484 NULL, NULL);
2485 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2486 F_CMD_ACCESS, NULL, NULL);
2487 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2488 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2489 NULL, NULL);
2490 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2491 F_CMD_ACCESS, NULL, NULL);
2492 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2493 F_CMD_ACCESS, NULL, NULL);
2494 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2495 ring_mode_mmio_write);
2496 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2497 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2498 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2499 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2500 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2501 ring_timestamp_mmio_read, NULL);
2502
2503 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2504 2468
2505#define RING_REG(base) (base + 0xd0) 2469#define RING_REG(base) (base + 0xd0)
2506 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2470 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2507 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2471 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2508 ring_reset_ctl_write); 2472 ring_reset_ctl_write);
2509 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2510 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2511 ring_reset_ctl_write);
2512#undef RING_REG 2473#undef RING_REG
2513 2474
2514#define RING_REG(base) (base + 0x230) 2475#define RING_REG(base) (base + 0x230)
2515 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2476 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2516 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
2517#undef RING_REG 2477#undef RING_REG
2518 2478
2519#define RING_REG(base) (base + 0x234) 2479#define RING_REG(base) (base + 0x234)
2520 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2480 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2521 NULL, NULL); 2481 NULL, NULL);
2522 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2523 ~0LL, D_BDW_PLUS, NULL, NULL);
2524#undef RING_REG 2482#undef RING_REG
2525 2483
2526#define RING_REG(base) (base + 0x244) 2484#define RING_REG(base) (base + 0x244)
2527 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2485 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2528 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2529 NULL, NULL);
2530#undef RING_REG 2486#undef RING_REG
2531 2487
2532#define RING_REG(base) (base + 0x370) 2488#define RING_REG(base) (base + 0x370)
2533 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2489 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2534 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2535 NULL, NULL);
2536#undef RING_REG 2490#undef RING_REG
2537 2491
2538#define RING_REG(base) (base + 0x3a0) 2492#define RING_REG(base) (base + 0x3a0)
2539 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2493 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2540 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2541#undef RING_REG 2494#undef RING_REG
2542 2495
2543 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2496 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
@@ -2557,11 +2510,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2557 2510
2558#define RING_REG(base) (base + 0x270) 2511#define RING_REG(base) (base + 0x270)
2559 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2512 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2560 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2561#undef RING_REG 2513#undef RING_REG
2562 2514
2563 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); 2515 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2564 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2565 2516
2566 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2517 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2567 2518
@@ -2849,7 +2800,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2849 MMIO_D(0x65f08, D_SKL | D_KBL); 2800 MMIO_D(0x65f08, D_SKL | D_KBL);
2850 MMIO_D(0x320f0, D_SKL | D_KBL); 2801 MMIO_D(0x320f0, D_SKL | D_KBL);
2851 2802
2852 MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2853 MMIO_D(0x70034, D_SKL_PLUS); 2803 MMIO_D(0x70034, D_SKL_PLUS);
2854 MMIO_D(0x71034, D_SKL_PLUS); 2804 MMIO_D(0x71034, D_SKL_PLUS);
2855 MMIO_D(0x72034, D_SKL_PLUS); 2805 MMIO_D(0x72034, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index fbd023a16f18..7d01c77a0f7a 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -54,9 +54,6 @@
54 54
55#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) 55#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
56 56
57#define _REG_VECS_EXCC 0x1A028
58#define _REG_VCS2_EXCC 0x1c028
59
60#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100) 57#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
61#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) 58#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
62 59
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 0d431a968a32..93a49eb0209e 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -68,6 +68,7 @@ struct shadow_indirect_ctx {
68struct shadow_per_ctx { 68struct shadow_per_ctx {
69 unsigned long guest_gma; 69 unsigned long guest_gma;
70 unsigned long shadow_gma; 70 unsigned long shadow_gma;
71 unsigned valid;
71}; 72};
72 73
73struct intel_shadow_wa_ctx { 74struct intel_shadow_wa_ctx {