diff options
author | Daniel Mack <daniel@zonque.org> | 2018-05-23 04:14:40 -0400 |
---|---|---|
committer | Kalle Valo <kvalo@codeaurora.org> | 2018-05-25 06:07:34 -0400 |
commit | ce1d4be82b1009374f7bea0229fb6758cb1afb84 (patch) | |
tree | b61f37dd4169ab9bec86b9b50a95569a159f0fda | |
parent | edd23ab403cf092a20ea185770f197f502ac32f0 (diff) |
wcn36xx: only handle packets when ED or DONE bit is set
On RX and TX interrupts, check for the WCN36XX_CH_STAT_INT_ED_MASK or
WCN36XX_CH_STAT_INT_DONE_MASK in the interrupt reason register, and
only handle packets when it is set. This way, reap_tx_dxes() is only
invoked when needed.
This brings the dequeing logic in line with what the prima downstream
driver is doing.
While at it, also log the interrupt reason.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
-rw-r--r-- | drivers/net/wireless/ath/wcn36xx/dxe.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/wcn36xx/dxe.c b/drivers/net/wireless/ath/wcn36xx/dxe.c index d11c9c536627..8c64e05ca3b7 100644 --- a/drivers/net/wireless/ath/wcn36xx/dxe.c +++ b/drivers/net/wireless/ath/wcn36xx/dxe.c | |||
@@ -430,8 +430,12 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev) | |||
430 | WCN36XX_INT_MASK_CHAN_TX_H); | 430 | WCN36XX_INT_MASK_CHAN_TX_H); |
431 | } | 431 | } |
432 | 432 | ||
433 | wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n"); | 433 | wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high, reason %08x\n", |
434 | reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch); | 434 | int_reason); |
435 | |||
436 | if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | | ||
437 | WCN36XX_CH_STAT_INT_ED_MASK)) | ||
438 | reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch); | ||
435 | } | 439 | } |
436 | 440 | ||
437 | if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) { | 441 | if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) { |
@@ -465,8 +469,12 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev) | |||
465 | WCN36XX_INT_MASK_CHAN_TX_L); | 469 | WCN36XX_INT_MASK_CHAN_TX_L); |
466 | } | 470 | } |
467 | 471 | ||
468 | wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n"); | 472 | wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low, reason %08x\n", |
469 | reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch); | 473 | int_reason); |
474 | |||
475 | if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | | ||
476 | WCN36XX_CH_STAT_INT_ED_MASK)) | ||
477 | reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch); | ||
470 | } | 478 | } |
471 | 479 | ||
472 | return IRQ_HANDLED; | 480 | return IRQ_HANDLED; |
@@ -545,6 +553,10 @@ static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, | |||
545 | WCN36XX_DXE_0_INT_ED_CLR, | 553 | WCN36XX_DXE_0_INT_ED_CLR, |
546 | int_mask); | 554 | int_mask); |
547 | 555 | ||
556 | if (!(int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | | ||
557 | WCN36XX_CH_STAT_INT_ED_MASK))) | ||
558 | return 0; | ||
559 | |||
548 | spin_lock(&ch->lock); | 560 | spin_lock(&ch->lock); |
549 | 561 | ||
550 | ctl = ch->head_blk_ctl; | 562 | ctl = ch->head_blk_ctl; |