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authorLeo Liu <leo.liu@amd.com>2019-07-09 11:04:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 15:18:04 -0400
commitcdbd115eaf1d17cff0d84c99e53774acba96eca7 (patch)
tree3f5ec10bb0225614f6dc0cd965774973b7a6ca06
parent22a8f442866bf539c7a659923155d9afa03d77bb (diff)
drm/amdgpu/VCN2: expose rings functions
They can be reused by VCN2.x family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c87
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h38
2 files changed, 79 insertions, 46 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 9bb29cd3aa50..ebef2f663654 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -1490,7 +1490,7 @@ static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1490 * 1490 *
1491 * Write a start command to the ring. 1491 * Write a start command to the ring.
1492 */ 1492 */
1493static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1493void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1494{ 1494{
1495 struct amdgpu_device *adev = ring->adev; 1495 struct amdgpu_device *adev = ring->adev;
1496 1496
@@ -1507,7 +1507,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1507 * 1507 *
1508 * Write a end command to the ring. 1508 * Write a end command to the ring.
1509 */ 1509 */
1510static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1510void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1511{ 1511{
1512 struct amdgpu_device *adev = ring->adev; 1512 struct amdgpu_device *adev = ring->adev;
1513 1513
@@ -1522,7 +1522,7 @@ static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1522 * 1522 *
1523 * Write a nop command to the ring. 1523 * Write a nop command to the ring.
1524 */ 1524 */
1525static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1525void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1526{ 1526{
1527 struct amdgpu_device *adev = ring->adev; 1527 struct amdgpu_device *adev = ring->adev;
1528 int i; 1528 int i;
@@ -1543,8 +1543,8 @@ static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
1543 * 1543 *
1544 * Write a fence and a trap command to the ring. 1544 * Write a fence and a trap command to the ring.
1545 */ 1545 */
1546static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1546void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1547 unsigned flags) 1547 unsigned flags)
1548{ 1548{
1549 struct amdgpu_device *adev = ring->adev; 1549 struct amdgpu_device *adev = ring->adev;
1550 1550
@@ -1580,10 +1580,10 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
1580 * 1580 *
1581 * Write ring commands to execute the indirect buffer 1581 * Write ring commands to execute the indirect buffer
1582 */ 1582 */
1583static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1583void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1584 struct amdgpu_job *job, 1584 struct amdgpu_job *job,
1585 struct amdgpu_ib *ib, 1585 struct amdgpu_ib *ib,
1586 uint32_t flags) 1586 uint32_t flags)
1587{ 1587{
1588 struct amdgpu_device *adev = ring->adev; 1588 struct amdgpu_device *adev = ring->adev;
1589 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1589 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
@@ -1599,9 +1599,8 @@ static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1599 amdgpu_ring_write(ring, ib->length_dw); 1599 amdgpu_ring_write(ring, ib->length_dw);
1600} 1600}
1601 1601
1602static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1602void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1603 uint32_t reg, uint32_t val, 1603 uint32_t val, uint32_t mask)
1604 uint32_t mask)
1605{ 1604{
1606 struct amdgpu_device *adev = ring->adev; 1605 struct amdgpu_device *adev = ring->adev;
1607 1606
@@ -1619,8 +1618,8 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1619 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1618 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1620} 1619}
1621 1620
1622static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1621void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1623 unsigned vmid, uint64_t pd_addr) 1622 unsigned vmid, uint64_t pd_addr)
1624{ 1623{
1625 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1624 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1626 uint32_t data0, data1, mask; 1625 uint32_t data0, data1, mask;
@@ -1634,8 +1633,8 @@ static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1634 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1633 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1635} 1634}
1636 1635
1637static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1636void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1638 uint32_t reg, uint32_t val) 1637 uint32_t reg, uint32_t val)
1639{ 1638{
1640 struct amdgpu_device *adev = ring->adev; 1639 struct amdgpu_device *adev = ring->adev;
1641 1640
@@ -1727,8 +1726,8 @@ static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1727 * 1726 *
1728 * Write enc a fence and a trap command to the ring. 1727 * Write enc a fence and a trap command to the ring.
1729 */ 1728 */
1730static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1729void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1731 u64 seq, unsigned flags) 1730 u64 seq, unsigned flags)
1732{ 1731{
1733 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1732 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1734 1733
@@ -1739,7 +1738,7 @@ static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1739 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1738 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1740} 1739}
1741 1740
1742static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1741void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1743{ 1742{
1744 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1743 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1745} 1744}
@@ -1752,10 +1751,10 @@ static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1752 * 1751 *
1753 * Write enc ring commands to execute the indirect buffer 1752 * Write enc ring commands to execute the indirect buffer
1754 */ 1753 */
1755static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1754void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1756 struct amdgpu_job *job, 1755 struct amdgpu_job *job,
1757 struct amdgpu_ib *ib, 1756 struct amdgpu_ib *ib,
1758 uint32_t flags) 1757 uint32_t flags)
1759{ 1758{
1760 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1759 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1761 1760
@@ -1766,9 +1765,8 @@ static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1766 amdgpu_ring_write(ring, ib->length_dw); 1765 amdgpu_ring_write(ring, ib->length_dw);
1767} 1766}
1768 1767
1769static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1768void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1770 uint32_t reg, uint32_t val, 1769 uint32_t val, uint32_t mask)
1771 uint32_t mask)
1772{ 1770{
1773 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1771 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1774 amdgpu_ring_write(ring, reg << 2); 1772 amdgpu_ring_write(ring, reg << 2);
@@ -1776,8 +1774,8 @@ static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1776 amdgpu_ring_write(ring, val); 1774 amdgpu_ring_write(ring, val);
1777} 1775}
1778 1776
1779static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1777void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1780 unsigned int vmid, uint64_t pd_addr) 1778 unsigned int vmid, uint64_t pd_addr)
1781{ 1779{
1782 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1780 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1783 1781
@@ -1788,8 +1786,7 @@ static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1788 lower_32_bits(pd_addr), 0xffffffff); 1786 lower_32_bits(pd_addr), 0xffffffff);
1789} 1787}
1790 1788
1791static void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1789void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1792 uint32_t reg, uint32_t val)
1793{ 1790{
1794 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1791 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1795 amdgpu_ring_write(ring, reg << 2); 1792 amdgpu_ring_write(ring, reg << 2);
@@ -1853,7 +1850,7 @@ static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1853 * 1850 *
1854 * Write a start command to the ring. 1851 * Write a start command to the ring.
1855 */ 1852 */
1856static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) 1853void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1857{ 1854{
1858 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1855 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
1859 0, 0, PACKETJ_TYPE0)); 1856 0, 0, PACKETJ_TYPE0));
@@ -1871,7 +1868,7 @@ static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1871 * 1868 *
1872 * Write a end command to the ring. 1869 * Write a end command to the ring.
1873 */ 1870 */
1874static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) 1871void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1875{ 1872{
1876 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1873 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
1877 0, 0, PACKETJ_TYPE0)); 1874 0, 0, PACKETJ_TYPE0));
@@ -1890,8 +1887,8 @@ static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1890 * 1887 *
1891 * Write a fence and a trap command to the ring. 1888 * Write a fence and a trap command to the ring.
1892 */ 1889 */
1893static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1890void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1894 unsigned flags) 1891 unsigned flags)
1895{ 1892{
1896 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1893 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1897 1894
@@ -1939,10 +1936,10 @@ static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u6
1939 * 1936 *
1940 * Write ring commands to execute the indirect buffer. 1937 * Write ring commands to execute the indirect buffer.
1941 */ 1938 */
1942static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, 1939void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1943 struct amdgpu_job *job, 1940 struct amdgpu_job *job,
1944 struct amdgpu_ib *ib, 1941 struct amdgpu_ib *ib,
1945 uint32_t flags) 1942 uint32_t flags)
1946{ 1943{
1947 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1944 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1948 1945
@@ -1990,9 +1987,8 @@ static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1990 amdgpu_ring_write(ring, 0x2); 1987 amdgpu_ring_write(ring, 0x2);
1991} 1988}
1992 1989
1993static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, 1990void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1994 uint32_t reg, uint32_t val, 1991 uint32_t val, uint32_t mask)
1995 uint32_t mask)
1996{ 1992{
1997 uint32_t reg_offset = (reg << 2); 1993 uint32_t reg_offset = (reg << 2);
1998 1994
@@ -2018,8 +2014,8 @@ static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
2018 amdgpu_ring_write(ring, mask); 2014 amdgpu_ring_write(ring, mask);
2019} 2015}
2020 2016
2021static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, 2017void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
2022 unsigned vmid, uint64_t pd_addr) 2018 unsigned vmid, uint64_t pd_addr)
2023{ 2019{
2024 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 2020 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
2025 uint32_t data0, data1, mask; 2021 uint32_t data0, data1, mask;
@@ -2033,8 +2029,7 @@ static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
2033 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); 2029 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
2034} 2030}
2035 2031
2036static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, 2032void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
2037 uint32_t reg, uint32_t val)
2038{ 2033{
2039 uint32_t reg_offset = (reg << 2); 2034 uint32_t reg_offset = (reg << 2);
2040 2035
@@ -2052,7 +2047,7 @@ static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
2052 amdgpu_ring_write(ring, val); 2047 amdgpu_ring_write(ring, val);
2053} 2048}
2054 2049
2055static void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) 2050void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
2056{ 2051{
2057 int i; 2052 int i;
2058 2053
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
index a74227f4663b..8467292f32e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
@@ -24,6 +24,44 @@
24#ifndef __VCN_V2_0_H__ 24#ifndef __VCN_V2_0_H__
25#define __VCN_V2_0_H__ 25#define __VCN_V2_0_H__
26 26
27extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
28extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
29extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
30extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
31 unsigned flags);
32extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
33 struct amdgpu_ib *ib, uint32_t flags);
34extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
35 uint32_t val, uint32_t mask);
36extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
37 unsigned vmid, uint64_t pd_addr);
38extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
39 uint32_t reg, uint32_t val);
40
41extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
42extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
43 u64 seq, unsigned flags);
44extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
45 struct amdgpu_ib *ib, uint32_t flags);
46extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
47 uint32_t val, uint32_t mask);
48extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
49 unsigned int vmid, uint64_t pd_addr);
50extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
51
52extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring);
53extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring);
54extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
55 unsigned flags);
56extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
57 struct amdgpu_ib *ib, uint32_t flags);
58extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
59 uint32_t val, uint32_t mask);
60extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
61 unsigned vmid, uint64_t pd_addr);
62extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
63extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count);
64
27extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block; 65extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
28 66
29#endif /* __VCN_V2_0_H__ */ 67#endif /* __VCN_V2_0_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 06:39:40 -0400