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authorTom St Denis <tom.stdenis@amd.com>2016-12-05 13:24:49 -0500
committerAlex Deucher <alexander.deucher@amd.com>2016-12-08 14:12:18 -0500
commitcc3f5b8df9fc5306fa9da245c6f41ed75cd9c608 (patch)
tree4030f79f9e7e32561f459ae3a181a70e0788837a
parent34e646f44412b366940d859686449f1d02496905 (diff)
drm/amd/amdgpu: Add gpr reading for GFX v7
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 1a745cf93f47..c4e14015ec5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4380,6 +4380,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
4380 return RREG32(mmSQ_IND_DATA); 4380 return RREG32(mmSQ_IND_DATA);
4381} 4381}
4382 4382
4383static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4384 uint32_t wave, uint32_t thread,
4385 uint32_t regno, uint32_t num, uint32_t *out)
4386{
4387 WREG32(mmSQ_IND_INDEX,
4388 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4389 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4390 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4391 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4392 (SQ_IND_INDEX__FORCE_READ_MASK) |
4393 (SQ_IND_INDEX__AUTO_INCR_MASK));
4394 while (num--)
4395 *(out++) = RREG32(mmSQ_IND_DATA);
4396}
4397
4383static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4398static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4384{ 4399{
4385 /* type 0 wave data */ 4400 /* type 0 wave data */
@@ -4404,10 +4419,20 @@ static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
4404 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4405} 4420}
4406 4421
4422static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4423 uint32_t wave, uint32_t start,
4424 uint32_t size, uint32_t *dst)
4425{
4426 wave_read_regs(
4427 adev, simd, wave, 0,
4428 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4429}
4430
4407static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4431static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4408 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4432 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4409 .select_se_sh = &gfx_v7_0_select_se_sh, 4433 .select_se_sh = &gfx_v7_0_select_se_sh,
4410 .read_wave_data = &gfx_v7_0_read_wave_data, 4434 .read_wave_data = &gfx_v7_0_read_wave_data,
4435 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4411}; 4436};
4412 4437
4413static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4438static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {