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authorJani Nikula <jani.nikula@intel.com>2013-09-17 11:33:43 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-18 03:59:10 -0400
commitcc173961a68034c1171a421f0dbed39edfb60880 (patch)
tree49ae065fe81f3d43b9d7a6b4d5dc0b139a584699
parent571c608d06df2d50233263d233a32edab1842865 (diff)
drm/i915: do not update cursor in crtc mode set
The cursor is disabled before crtc mode set in crtc disable (and we assert this is the case), and enabled afterwards in crtc enable. Do not update it in crtc mode set. On HSW enabling a plane on a disabled pipe may hang the entire system. And there's no good reason for doing it ever, so just don't. v2: Add note about HSW hangs - vsyrjala Cc: stable@vger.kernel.org Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d7c4f634bb9..a38056d68dd8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4877,9 +4877,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4877 return -EINVAL; 4877 return -EINVAL;
4878 } 4878 }
4879 4879
4880 /* Ensure that the cursor is valid for the new mode before changing... */
4881 intel_crtc_update_cursor(crtc, true);
4882
4883 if (is_lvds && dev_priv->lvds_downclock_avail) { 4880 if (is_lvds && dev_priv->lvds_downclock_avail) {
4884 /* 4881 /*
4885 * Ensure we match the reduced clock's P to the target clock. 4882 * Ensure we match the reduced clock's P to the target clock.
@@ -5768,9 +5765,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5768 intel_crtc->config.dpll.p2 = clock.p2; 5765 intel_crtc->config.dpll.p2 = clock.p2;
5769 } 5766 }
5770 5767
5771 /* Ensure that the cursor is valid for the new mode before changing... */
5772 intel_crtc_update_cursor(crtc, true);
5773
5774 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5768 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5775 if (intel_crtc->config.has_pch_encoder) { 5769 if (intel_crtc->config.has_pch_encoder) {
5776 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); 5770 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
@@ -6260,9 +6254,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6260 if (!intel_ddi_pll_mode_set(crtc)) 6254 if (!intel_ddi_pll_mode_set(crtc))
6261 return -EINVAL; 6255 return -EINVAL;
6262 6256
6263 /* Ensure that the cursor is valid for the new mode before changing... */
6264 intel_crtc_update_cursor(crtc, true);
6265
6266 if (intel_crtc->config.has_dp_encoder) 6257 if (intel_crtc->config.has_dp_encoder)
6267 intel_dp_set_m_n(intel_crtc); 6258 intel_dp_set_m_n(intel_crtc);
6268 6259