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authorBard Liao <bardliao@realtek.com>2015-12-30 02:33:21 -0500
committerMark Brown <broonie@kernel.org>2015-12-30 11:35:07 -0500
commitca8457bb02d8ecddf7f49ab874127dd4df782b16 (patch)
tree079c9ffbcb089694455b7dbe5b98ecaaa01188a1
parent8005c49d9aea74d382f474ce11afbbc7d7130bec (diff)
ASoC: rt5645: add sys clk detection
Add system clock detection to prevent output DC from SPO. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/codecs/rt5645.c4
-rw-r--r--sound/soc/codecs/rt5645.h4
2 files changed, 8 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
index 28132375e427..61bbeac0c117 100644
--- a/sound/soc/codecs/rt5645.c
+++ b/sound/soc/codecs/rt5645.c
@@ -1646,9 +1646,13 @@ static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1646 RT5645_PWR_CLS_D_L, 1646 RT5645_PWR_CLS_D_L,
1647 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1647 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1648 RT5645_PWR_CLS_D_L); 1648 RT5645_PWR_CLS_D_L);
1649 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1650 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1649 break; 1651 break;
1650 1652
1651 case SND_SOC_DAPM_PRE_PMD: 1653 case SND_SOC_DAPM_PRE_PMD:
1654 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1655 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1652 snd_soc_write(codec, RT5645_EQ_CTRL2, 0); 1656 snd_soc_write(codec, RT5645_EQ_CTRL2, 0);
1653 snd_soc_update_bits(codec, RT5645_PWR_DIG1, 1657 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1654 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1658 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
index 093e46d559fb..205e0715c99a 100644
--- a/sound/soc/codecs/rt5645.h
+++ b/sound/soc/codecs/rt5645.h
@@ -2122,6 +2122,10 @@ enum {
2122/* General Control3 (0xfc) */ 2122/* General Control3 (0xfc) */
2123#define RT5645_JD_PSV_MODE (0x1 << 12) 2123#define RT5645_JD_PSV_MODE (0x1 << 12)
2124#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) 2124#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
2125#define RT5645_DET_CLK_MASK (0x3 << 9)
2126#define RT5645_DET_CLK_DIS (0x0 << 9)
2127#define RT5645_DET_CLK_MODE1 (0x1 << 9)
2128#define RT5645_DET_CLK_MODE2 (0x2 << 9)
2125#define RT5645_MICINDET_MANU (0x1 << 7) 2129#define RT5645_MICINDET_MANU (0x1 << 7)
2126#define RT5645_RING2_SLEEVE_GND (0x1 << 5) 2130#define RT5645_RING2_SLEEVE_GND (0x1 << 5)
2127 2131