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authorLinus Torvalds <torvalds@linux-foundation.org>2018-05-11 12:18:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-05-11 12:18:02 -0400
commitca30093dd7ff8fd3423c68db1f70f72a88542cb9 (patch)
tree1f2c832f828e14d57f8fdb2c4ea44b70533327a5
parent0a0b98734479aa5b3c671d5190e86273372cab95 (diff)
parent72777fe79768ec30ac2163d26de68a89edc9849f (diff)
Merge tag 'drm-fixes-for-v4.17-rc5' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "nouveau, amdgpu, i915, vc4, omap, exynos and atomic fixes. As last week seemed a bit slow, we got a few more fixes this week. The main stuff is two weeks of fixes for amdgpu, some missing bits of vega12 atom firmware support were added, and some power management fixes. Nouveau got two regression fixes for an DP MST deadlock and a random oops fix. i915 got an LVDS panel timeout fix 2 WARN fixes. exynos fixed a pagefault issue in the mixer driver. vc4 has an oops fix. omap had a bunch of uninit var and error-checking fixes. Two atomic modesetting state fixes. One minor agp cleanup patch" * tag 'drm-fixes-for-v4.17-rc5' of git://people.freedesktop.org/~airlied/linux: (30 commits) drm/amd/pp: Fix performance drop on Fiji drm/nouveau: Fix deadlock in nv50_mstm_register_connector() drm/nouveau/ttm: don't dereference nvbo::cli, it can outlive client agp: uninorth: make two functions static drm/amd/pp: Refine the output of pp_power_profile_mode on VI drm/amdgpu: Switch to interruptable wait to recover from ring hang. drm/ttm: Use GFP_TRANSHUGE_LIGHT for allocating huge pages drm/amd/display: Use kvzalloc for potentially large allocations drm/amd/display: Don't return ddc result and read_bytes in same return value drm/amd/display: Add get_firmware_info_v3_2 for VG12 drm/amd: Add BIOS smu_info v3_3 required struct def. drm/amd/display: Add VG12 ASIC IDs drm/vc4: Fix scaling of uni-planar formats drm/exynos: hdmi: avoid duplicating drm_bridge_attach drm/i915: Fix drm:intel_enable_lvds ERROR message in kernel log drm/i915: Correctly populate user mode h/vdisplay with pipe src size during readout drm/i915: Adjust eDP's logical vco in a reliable place. drm/bridge/sii8620: add Kconfig dependency on extcon drm/omap: handle alloc failures in omap_connector drm/omap: add missing linefeeds to prints ...
Diffstat
-rw-r--r--drivers/char/agp/uninorth-agp.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c6
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c20
-rw-r--r--drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c86
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c10
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_surface.c14
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h5
-rw-r--r--drivers/gpu/drm/amd/display/include/dal_asic_id.h9
-rw-r--r--drivers/gpu/drm/amd/display/modules/color/color_gamma.c72
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h170
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c52
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c4
-rw-r--r--drivers/gpu/drm/bridge/Kconfig1
-rw-r--r--drivers/gpu/drm/drm_atomic.c8
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c22
-rw-r--r--drivers/gpu/drm/exynos/regs-mixer.h1
-rw-r--r--drivers/gpu/drm/i915/intel_cdclk.c41
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c20
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c7
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c20
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4.c2
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4_core.c7
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5.c2
-rw-r--r--drivers/gpu/drm/omapdrm/omap_connector.c10
-rw-r--r--drivers/gpu/drm/omapdrm/omap_dmm_tiler.c6
-rw-r--r--drivers/gpu/drm/omapdrm/tcm-sita.c2
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c11
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc_dma.c3
-rw-r--r--drivers/gpu/drm/vc4/vc4_dpi.c25
-rw-r--r--drivers/gpu/drm/vc4/vc4_plane.c2
37 files changed, 501 insertions, 158 deletions
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index c381c8e396fc..79d8c84693a1 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -195,7 +195,7 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int ty
195 return 0; 195 return 0;
196} 196}
197 197
198int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 198static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
199{ 199{
200 size_t i; 200 size_t i;
201 u32 *gp; 201 u32 *gp;
@@ -470,7 +470,7 @@ static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
470 return 0; 470 return 0;
471} 471}
472 472
473void null_cache_flush(void) 473static void null_cache_flush(void)
474{ 474{
475 mb(); 475 mb();
476} 476}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 09d35051fdd6..3fabf9f97022 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -419,9 +419,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
419 419
420 if (other) { 420 if (other) {
421 signed long r; 421 signed long r;
422 r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); 422 r = dma_fence_wait(other, true);
423 if (r < 0) { 423 if (r < 0) {
424 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 424 if (r != -ERESTARTSYS)
425 DRM_ERROR("Error (%ld) waiting for fence!\n", r);
426
425 return r; 427 return r;
426 } 428 }
427 } 429 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ace9ad578ca0..4304d9e408b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
83 enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ? 83 enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
84 I2C_MOT_TRUE : I2C_MOT_FALSE; 84 I2C_MOT_TRUE : I2C_MOT_FALSE;
85 enum ddc_result res; 85 enum ddc_result res;
86 ssize_t read_bytes; 86 uint32_t read_bytes = msg->size;
87 87
88 if (WARN_ON(msg->size > 16)) 88 if (WARN_ON(msg->size > 16))
89 return -E2BIG; 89 return -E2BIG;
90 90
91 switch (msg->request & ~DP_AUX_I2C_MOT) { 91 switch (msg->request & ~DP_AUX_I2C_MOT) {
92 case DP_AUX_NATIVE_READ: 92 case DP_AUX_NATIVE_READ:
93 read_bytes = dal_ddc_service_read_dpcd_data( 93 res = dal_ddc_service_read_dpcd_data(
94 TO_DM_AUX(aux)->ddc_service, 94 TO_DM_AUX(aux)->ddc_service,
95 false, 95 false,
96 I2C_MOT_UNDEF, 96 I2C_MOT_UNDEF,
97 msg->address, 97 msg->address,
98 msg->buffer, 98 msg->buffer,
99 msg->size); 99 msg->size,
100 return read_bytes; 100 &read_bytes);
101 break;
101 case DP_AUX_NATIVE_WRITE: 102 case DP_AUX_NATIVE_WRITE:
102 res = dal_ddc_service_write_dpcd_data( 103 res = dal_ddc_service_write_dpcd_data(
103 TO_DM_AUX(aux)->ddc_service, 104 TO_DM_AUX(aux)->ddc_service,
@@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
108 msg->size); 109 msg->size);
109 break; 110 break;
110 case DP_AUX_I2C_READ: 111 case DP_AUX_I2C_READ:
111 read_bytes = dal_ddc_service_read_dpcd_data( 112 res = dal_ddc_service_read_dpcd_data(
112 TO_DM_AUX(aux)->ddc_service, 113 TO_DM_AUX(aux)->ddc_service,
113 true, 114 true,
114 mot, 115 mot,
115 msg->address, 116 msg->address,
116 msg->buffer, 117 msg->buffer,
117 msg->size); 118 msg->size,
118 return read_bytes; 119 &read_bytes);
120 break;
119 case DP_AUX_I2C_WRITE: 121 case DP_AUX_I2C_WRITE:
120 res = dal_ddc_service_write_dpcd_data( 122 res = dal_ddc_service_write_dpcd_data(
121 TO_DM_AUX(aux)->ddc_service, 123 TO_DM_AUX(aux)->ddc_service,
@@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
137 r == DDC_RESULT_SUCESSFULL); 139 r == DDC_RESULT_SUCESSFULL);
138#endif 140#endif
139 141
140 return msg->size; 142 if (res != DDC_RESULT_SUCESSFULL)
143 return -EIO;
144 return read_bytes;
141} 145}
142 146
143static enum drm_connector_status 147static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 985fe8c22875..10a5807a7e8b 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
70 struct bios_parser *bp, 70 struct bios_parser *bp,
71 struct dc_firmware_info *info); 71 struct dc_firmware_info *info);
72 72
73static enum bp_result get_firmware_info_v3_2(
74 struct bios_parser *bp,
75 struct dc_firmware_info *info);
76
73static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 77static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
74 struct atom_display_object_path_v2 *object); 78 struct atom_display_object_path_v2 *object);
75 79
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
1321 case 3: 1325 case 3:
1322 switch (revision.minor) { 1326 switch (revision.minor) {
1323 case 1: 1327 case 1:
1324 case 2:
1325 result = get_firmware_info_v3_1(bp, info); 1328 result = get_firmware_info_v3_1(bp, info);
1326 break; 1329 break;
1330 case 2:
1331 result = get_firmware_info_v3_2(bp, info);
1332 break;
1327 default: 1333 default:
1328 break; 1334 break;
1329 } 1335 }
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
1383 return BP_RESULT_OK; 1389 return BP_RESULT_OK;
1384} 1390}
1385 1391
1392static enum bp_result get_firmware_info_v3_2(
1393 struct bios_parser *bp,
1394 struct dc_firmware_info *info)
1395{
1396 struct atom_firmware_info_v3_2 *firmware_info;
1397 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1398 struct atom_common_table_header *header;
1399 struct atom_data_revision revision;
1400 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1401 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1402
1403 if (!info)
1404 return BP_RESULT_BADINPUT;
1405
1406 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1407 DATA_TABLES(firmwareinfo));
1408
1409 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1410 DATA_TABLES(dce_info));
1411
1412 if (!firmware_info || !dce_info)
1413 return BP_RESULT_BADBIOSTABLE;
1414
1415 memset(info, 0, sizeof(*info));
1416
1417 header = GET_IMAGE(struct atom_common_table_header,
1418 DATA_TABLES(smu_info));
1419 get_atom_data_table_revision(header, &revision);
1420
1421 if (revision.minor == 2) {
1422 /* Vega12 */
1423 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1424 DATA_TABLES(smu_info));
1425
1426 if (!smu_info_v3_2)
1427 return BP_RESULT_BADBIOSTABLE;
1428
1429 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1430 } else if (revision.minor == 3) {
1431 /* Vega20 */
1432 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1433 DATA_TABLES(smu_info));
1434
1435 if (!smu_info_v3_3)
1436 return BP_RESULT_BADBIOSTABLE;
1437
1438 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1439 }
1440
1441 // We need to convert from 10KHz units into KHz units.
1442 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1443
1444 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1445 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1446 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1447 if (info->pll_info.crystal_frequency == 0) {
1448 if (revision.minor == 2)
1449 info->pll_info.crystal_frequency = 27000;
1450 else if (revision.minor == 3)
1451 info->pll_info.crystal_frequency = 100000;
1452 }
1453 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1454 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1455 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1456
1457 /* Get GPU PLL VCO Clock */
1458 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1459 if (revision.minor == 2)
1460 info->smu_gpu_pll_output_freq =
1461 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1462 else if (revision.minor == 3)
1463 info->smu_gpu_pll_output_freq =
1464 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1465 }
1466
1467 return BP_RESULT_OK;
1468}
1469
1386static enum bp_result bios_parser_get_encoder_cap_info( 1470static enum bp_result bios_parser_get_encoder_cap_info(
1387 struct dc_bios *dcb, 1471 struct dc_bios *dcb,
1388 struct graphics_object_id object_id, 1472 struct graphics_object_id object_id,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 49c2face1e7a..ae48d603ebd6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
629 return ret; 629 return ret;
630} 630}
631 631
632ssize_t dal_ddc_service_read_dpcd_data( 632enum ddc_result dal_ddc_service_read_dpcd_data(
633 struct ddc_service *ddc, 633 struct ddc_service *ddc,
634 bool i2c, 634 bool i2c,
635 enum i2c_mot_mode mot, 635 enum i2c_mot_mode mot,
636 uint32_t address, 636 uint32_t address,
637 uint8_t *data, 637 uint8_t *data,
638 uint32_t len) 638 uint32_t len,
639 uint32_t *read)
639{ 640{
640 struct aux_payload read_payload = { 641 struct aux_payload read_payload = {
641 .i2c_over_aux = i2c, 642 .i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
652 .mot = mot 653 .mot = mot
653 }; 654 };
654 655
656 *read = 0;
657
655 if (len > DEFAULT_AUX_MAX_DATA_SIZE) { 658 if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
656 BREAK_TO_DEBUGGER(); 659 BREAK_TO_DEBUGGER();
657 return DDC_RESULT_FAILED_INVALID_OPERATION; 660 return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
661 ddc->ctx->i2caux, 664 ddc->ctx->i2caux,
662 ddc->ddc_pin, 665 ddc->ddc_pin,
663 &command)) { 666 &command)) {
664 return (ssize_t)command.payloads->length; 667 *read = command.payloads->length;
668 return DDC_RESULT_SUCESSFULL;
665 } 669 }
666 670
667 return DDC_RESULT_FAILED_OPERATION; 671 return DDC_RESULT_FAILED_OPERATION;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index ade5b8ee9c3c..132eef3826e2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -66,8 +66,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
66{ 66{
67 struct dc *core_dc = dc; 67 struct dc *core_dc = dc;
68 68
69 struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state), 69 struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
70 GFP_KERNEL); 70 GFP_KERNEL);
71 71
72 if (NULL == plane_state) 72 if (NULL == plane_state)
73 return NULL; 73 return NULL;
@@ -120,7 +120,7 @@ static void dc_plane_state_free(struct kref *kref)
120{ 120{
121 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount); 121 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
122 destruct(plane_state); 122 destruct(plane_state);
123 kfree(plane_state); 123 kvfree(plane_state);
124} 124}
125 125
126void dc_plane_state_release(struct dc_plane_state *plane_state) 126void dc_plane_state_release(struct dc_plane_state *plane_state)
@@ -136,7 +136,7 @@ void dc_gamma_retain(struct dc_gamma *gamma)
136static void dc_gamma_free(struct kref *kref) 136static void dc_gamma_free(struct kref *kref)
137{ 137{
138 struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount); 138 struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
139 kfree(gamma); 139 kvfree(gamma);
140} 140}
141 141
142void dc_gamma_release(struct dc_gamma **gamma) 142void dc_gamma_release(struct dc_gamma **gamma)
@@ -147,7 +147,7 @@ void dc_gamma_release(struct dc_gamma **gamma)
147 147
148struct dc_gamma *dc_create_gamma(void) 148struct dc_gamma *dc_create_gamma(void)
149{ 149{
150 struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL); 150 struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
151 151
152 if (gamma == NULL) 152 if (gamma == NULL)
153 goto alloc_fail; 153 goto alloc_fail;
@@ -167,7 +167,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf)
167static void dc_transfer_func_free(struct kref *kref) 167static void dc_transfer_func_free(struct kref *kref)
168{ 168{
169 struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount); 169 struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
170 kfree(tf); 170 kvfree(tf);
171} 171}
172 172
173void dc_transfer_func_release(struct dc_transfer_func *tf) 173void dc_transfer_func_release(struct dc_transfer_func *tf)
@@ -177,7 +177,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
177 177
178struct dc_transfer_func *dc_create_transfer_func(void) 178struct dc_transfer_func *dc_create_transfer_func(void)
179{ 179{
180 struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL); 180 struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
181 181
182 if (tf == NULL) 182 if (tf == NULL)
183 goto alloc_fail; 183 goto alloc_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 090b7a8dd67b..30b3a08b91be 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data(
102 uint8_t *read_buf, 102 uint8_t *read_buf,
103 uint32_t read_size); 103 uint32_t read_size);
104 104
105ssize_t dal_ddc_service_read_dpcd_data( 105enum ddc_result dal_ddc_service_read_dpcd_data(
106 struct ddc_service *ddc, 106 struct ddc_service *ddc,
107 bool i2c, 107 bool i2c,
108 enum i2c_mot_mode mot, 108 enum i2c_mot_mode mot,
109 uint32_t address, 109 uint32_t address,
110 uint8_t *data, 110 uint8_t *data,
111 uint32_t len); 111 uint32_t len,
112 uint32_t *read);
112 113
113enum ddc_result dal_ddc_service_write_dpcd_data( 114enum ddc_result dal_ddc_service_write_dpcd_data(
114 struct ddc_service *ddc, 115 struct ddc_service *ddc,
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 9831cb5eaa7c..9b0a04f99ac8 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -113,9 +113,14 @@
113 113
114#define AI_GREENLAND_P_A0 1 114#define AI_GREENLAND_P_A0 1
115#define AI_GREENLAND_P_A1 2 115#define AI_GREENLAND_P_A1 2
116#define AI_UNKNOWN 0xFF
116 117
117#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN) 118#define AI_VEGA12_P_A0 20
118#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN) 119#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
120#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
121
122#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
123#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
119 124
120/* DCN1_0 */ 125/* DCN1_0 */
121#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ 126#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index e7e374f56864..b3747a019deb 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1093,19 +1093,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
1093 1093
1094 output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1094 output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1095 1095
1096 rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS), 1096 rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1097 GFP_KERNEL); 1097 GFP_KERNEL);
1098 if (!rgb_user) 1098 if (!rgb_user)
1099 goto rgb_user_alloc_fail; 1099 goto rgb_user_alloc_fail;
1100 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS), 1100 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
1101 GFP_KERNEL); 1101 GFP_KERNEL);
1102 if (!rgb_regamma) 1102 if (!rgb_regamma)
1103 goto rgb_regamma_alloc_fail; 1103 goto rgb_regamma_alloc_fail;
1104 axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3), 1104 axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
1105 GFP_KERNEL); 1105 GFP_KERNEL);
1106 if (!axix_x) 1106 if (!axix_x)
1107 goto axix_x_alloc_fail; 1107 goto axix_x_alloc_fail;
1108 coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL); 1108 coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1109 if (!coeff) 1109 if (!coeff)
1110 goto coeff_alloc_fail; 1110 goto coeff_alloc_fail;
1111 1111
@@ -1157,13 +1157,13 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
1157 1157
1158 ret = true; 1158 ret = true;
1159 1159
1160 kfree(coeff); 1160 kvfree(coeff);
1161coeff_alloc_fail: 1161coeff_alloc_fail:
1162 kfree(axix_x); 1162 kvfree(axix_x);
1163axix_x_alloc_fail: 1163axix_x_alloc_fail:
1164 kfree(rgb_regamma); 1164 kvfree(rgb_regamma);
1165rgb_regamma_alloc_fail: 1165rgb_regamma_alloc_fail:
1166 kfree(rgb_user); 1166 kvfree(rgb_user);
1167rgb_user_alloc_fail: 1167rgb_user_alloc_fail:
1168 return ret; 1168 return ret;
1169} 1169}
@@ -1192,19 +1192,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
1192 1192
1193 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1193 input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
1194 1194
1195 rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS), 1195 rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
1196 GFP_KERNEL); 1196 GFP_KERNEL);
1197 if (!rgb_user) 1197 if (!rgb_user)
1198 goto rgb_user_alloc_fail; 1198 goto rgb_user_alloc_fail;
1199 curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS), 1199 curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
1200 GFP_KERNEL); 1200 GFP_KERNEL);
1201 if (!curve) 1201 if (!curve)
1202 goto curve_alloc_fail; 1202 goto curve_alloc_fail;
1203 axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS), 1203 axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
1204 GFP_KERNEL); 1204 GFP_KERNEL);
1205 if (!axix_x) 1205 if (!axix_x)
1206 goto axix_x_alloc_fail; 1206 goto axix_x_alloc_fail;
1207 coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL); 1207 coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
1208 if (!coeff) 1208 if (!coeff)
1209 goto coeff_alloc_fail; 1209 goto coeff_alloc_fail;
1210 1210
@@ -1246,13 +1246,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
1246 1246
1247 ret = true; 1247 ret = true;
1248 1248
1249 kfree(coeff); 1249 kvfree(coeff);
1250coeff_alloc_fail: 1250coeff_alloc_fail:
1251 kfree(axix_x); 1251 kvfree(axix_x);
1252axix_x_alloc_fail: 1252axix_x_alloc_fail:
1253 kfree(curve); 1253 kvfree(curve);
1254curve_alloc_fail: 1254curve_alloc_fail:
1255 kfree(rgb_user); 1255 kvfree(rgb_user);
1256rgb_user_alloc_fail: 1256rgb_user_alloc_fail:
1257 1257
1258 return ret; 1258 return ret;
@@ -1281,8 +1281,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1281 } 1281 }
1282 ret = true; 1282 ret = true;
1283 } else if (trans == TRANSFER_FUNCTION_PQ) { 1283 } else if (trans == TRANSFER_FUNCTION_PQ) {
1284 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + 1284 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1285 _EXTRA_POINTS), GFP_KERNEL); 1285 (MAX_HW_POINTS + _EXTRA_POINTS),
1286 GFP_KERNEL);
1286 if (!rgb_regamma) 1287 if (!rgb_regamma)
1287 goto rgb_regamma_alloc_fail; 1288 goto rgb_regamma_alloc_fail;
1288 points->end_exponent = 7; 1289 points->end_exponent = 7;
@@ -1302,11 +1303,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1302 } 1303 }
1303 ret = true; 1304 ret = true;
1304 1305
1305 kfree(rgb_regamma); 1306 kvfree(rgb_regamma);
1306 } else if (trans == TRANSFER_FUNCTION_SRGB || 1307 } else if (trans == TRANSFER_FUNCTION_SRGB ||
1307 trans == TRANSFER_FUNCTION_BT709) { 1308 trans == TRANSFER_FUNCTION_BT709) {
1308 rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + 1309 rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
1309 _EXTRA_POINTS), GFP_KERNEL); 1310 (MAX_HW_POINTS + _EXTRA_POINTS),
1311 GFP_KERNEL);
1310 if (!rgb_regamma) 1312 if (!rgb_regamma)
1311 goto rgb_regamma_alloc_fail; 1313 goto rgb_regamma_alloc_fail;
1312 points->end_exponent = 0; 1314 points->end_exponent = 0;
@@ -1324,7 +1326,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
1324 } 1326 }
1325 ret = true; 1327 ret = true;
1326 1328
1327 kfree(rgb_regamma); 1329 kvfree(rgb_regamma);
1328 } 1330 }
1329rgb_regamma_alloc_fail: 1331rgb_regamma_alloc_fail:
1330 return ret; 1332 return ret;
@@ -1348,8 +1350,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1348 } 1350 }
1349 ret = true; 1351 ret = true;
1350 } else if (trans == TRANSFER_FUNCTION_PQ) { 1352 } else if (trans == TRANSFER_FUNCTION_PQ) {
1351 rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS + 1353 rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1352 _EXTRA_POINTS), GFP_KERNEL); 1354 (MAX_HW_POINTS + _EXTRA_POINTS),
1355 GFP_KERNEL);
1353 if (!rgb_degamma) 1356 if (!rgb_degamma)
1354 goto rgb_degamma_alloc_fail; 1357 goto rgb_degamma_alloc_fail;
1355 1358
@@ -1364,11 +1367,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1364 } 1367 }
1365 ret = true; 1368 ret = true;
1366 1369
1367 kfree(rgb_degamma); 1370 kvfree(rgb_degamma);
1368 } else if (trans == TRANSFER_FUNCTION_SRGB || 1371 } else if (trans == TRANSFER_FUNCTION_SRGB ||
1369 trans == TRANSFER_FUNCTION_BT709) { 1372 trans == TRANSFER_FUNCTION_BT709) {
1370 rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS + 1373 rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
1371 _EXTRA_POINTS), GFP_KERNEL); 1374 (MAX_HW_POINTS + _EXTRA_POINTS),
1375 GFP_KERNEL);
1372 if (!rgb_degamma) 1376 if (!rgb_degamma)
1373 goto rgb_degamma_alloc_fail; 1377 goto rgb_degamma_alloc_fail;
1374 1378
@@ -1382,7 +1386,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
1382 } 1386 }
1383 ret = true; 1387 ret = true;
1384 1388
1385 kfree(rgb_degamma); 1389 kvfree(rgb_degamma);
1386 } 1390 }
1387 points->end_exponent = 0; 1391 points->end_exponent = 0;
1388 points->x_point_at_y1_red = 1; 1392 points->x_point_at_y1_red = 1;
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 0f5ad54d3fd3..de177ce8ca80 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
501 LIQUID_COOLING = 0x01 501 LIQUID_COOLING = 0x01
502}; 502};
503 503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
504 530
505/* 531/*
506 *************************************************************************** 532 ***************************************************************************
@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
1169 uint32_t rlc_gpu_timer_refclk; 1195 uint32_t rlc_gpu_timer_refclk;
1170}; 1196};
1171 1197
1172 1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
1173 1221
1174/* 1222/*
1175 *************************************************************************** 1223 ***************************************************************************
@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
1198 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1246 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199}; 1247};
1200 1248
1249struct atom_smu_info_v3_2 {
1250 struct atom_common_table_header table_header;
1251 uint8_t smuip_min_ver;
1252 uint8_t smuip_max_ver;
1253 uint8_t smu_rsd1;
1254 uint8_t gpuclk_ss_mode;
1255 uint16_t sclk_ss_percentage;
1256 uint16_t sclk_ss_rate_10hz;
1257 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1258 uint16_t gpuclk_ss_rate_10hz;
1259 uint32_t core_refclk_10khz;
1260 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1261 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1262 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1263 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1264 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1265 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1266 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1267 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1268 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1269 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1270 uint16_t smugoldenoffset;
1271 uint32_t gpupll_vco_freq_10khz;
1272 uint32_t bootup_smnclk_10khz;
1273 uint32_t bootup_socclk_10khz;
1274 uint32_t bootup_mp0clk_10khz;
1275 uint32_t bootup_mp1clk_10khz;
1276 uint32_t bootup_lclk_10khz;
1277 uint32_t bootup_dcefclk_10khz;
1278 uint32_t ctf_threshold_override_value;
1279 uint32_t reserved[5];
1280};
1281
1282struct atom_smu_info_v3_3 {
1283 struct atom_common_table_header table_header;
1284 uint8_t smuip_min_ver;
1285 uint8_t smuip_max_ver;
1286 uint8_t smu_rsd1;
1287 uint8_t gpuclk_ss_mode;
1288 uint16_t sclk_ss_percentage;
1289 uint16_t sclk_ss_rate_10hz;
1290 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1291 uint16_t gpuclk_ss_rate_10hz;
1292 uint32_t core_refclk_10khz;
1293 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1294 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1295 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1296 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1297 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1298 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1299 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1300 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1301 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1302 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1303 uint16_t smugoldenoffset;
1304 uint32_t gpupll_vco_freq_10khz;
1305 uint32_t bootup_smnclk_10khz;
1306 uint32_t bootup_socclk_10khz;
1307 uint32_t bootup_mp0clk_10khz;
1308 uint32_t bootup_mp1clk_10khz;
1309 uint32_t bootup_lclk_10khz;
1310 uint32_t bootup_dcefclk_10khz;
1311 uint32_t ctf_threshold_override_value;
1312 uint32_t syspll3_0_vco_freq_10khz;
1313 uint32_t syspll3_1_vco_freq_10khz;
1314 uint32_t bootup_fclk_10khz;
1315 uint32_t bootup_waflclk_10khz;
1316 uint32_t reserved[3];
1317};
1318
1201/* 1319/*
1202 *************************************************************************** 1320 ***************************************************************************
1203 Data Table smc_dpm_info structure 1321 Data Table smc_dpm_info structure
@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
1283 uint32_t boardreserved[10]; 1401 uint32_t boardreserved[10];
1284}; 1402};
1285 1403
1286
1287/* 1404/*
1288 *************************************************************************** 1405 ***************************************************************************
1289 Data Table asic_profiling_info structure 1406 Data Table asic_profiling_info structure
@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
1864 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 1981 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865}; 1982};
1866 1983
1984enum atom_smu11_syspll_id {
1985 SMU11_SYSPLL0_ID = 0,
1986 SMU11_SYSPLL1_0_ID = 1,
1987 SMU11_SYSPLL1_1_ID = 2,
1988 SMU11_SYSPLL1_2_ID = 3,
1989 SMU11_SYSPLL2_ID = 4,
1990 SMU11_SYSPLL3_0_ID = 5,
1991 SMU11_SYSPLL3_1_ID = 6,
1992};
1993
1994
1995enum atom_smu11_syspll0_clock_id {
1996 SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1997 SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1998 SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1999 SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
2000 SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
2001 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2002};
2003
2004
2005enum atom_smu11_syspll1_0_clock_id {
2006 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2007};
2008
2009enum atom_smu11_syspll1_1_clock_id {
2010 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2011};
2012
2013enum atom_smu11_syspll1_2_clock_id {
2014 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2015};
2016
2017enum atom_smu11_syspll2_clock_id {
2018 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2019};
2020
2021enum atom_smu11_syspll3_0_clock_id {
2022 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2023 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2024 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2025};
2026
2027enum atom_smu11_syspll3_1_clock_id {
2028 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2029 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2030 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2031};
2032
1867struct atom_get_smu_clock_info_output_parameters_v3_1 2033struct atom_get_smu_clock_info_output_parameters_v3_1
1868{ 2034{
1869 union { 2035 union {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 26fbeafc3c96..18b5b2ff47fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -79,12 +79,13 @@
79#define PCIE_BUS_CLK 10000 79#define PCIE_BUS_CLK 10000
80#define TCLK (PCIE_BUS_CLK / 10) 80#define TCLK (PCIE_BUS_CLK / 10)
81 81
82static const struct profile_mode_setting smu7_profiling[5] = 82static const struct profile_mode_setting smu7_profiling[6] =
83 {{1, 0, 100, 30, 1, 0, 100, 10}, 83 {{1, 0, 100, 30, 1, 0, 100, 10},
84 {1, 10, 0, 30, 0, 0, 0, 0}, 84 {1, 10, 0, 30, 0, 0, 0, 0},
85 {0, 0, 0, 0, 1, 10, 16, 31}, 85 {0, 0, 0, 0, 1, 10, 16, 31},
86 {1, 0, 11, 50, 1, 0, 100, 10}, 86 {1, 0, 11, 50, 1, 0, 100, 10},
87 {1, 0, 5, 30, 0, 0, 0, 0}, 87 {1, 0, 5, 30, 0, 0, 0, 0},
88 {0, 0, 0, 0, 0, 0, 0, 0},
88 }; 89 };
89 90
90/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 91/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
@@ -4864,6 +4865,17 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4864 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting); 4865 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
4865 4866
4866 for (i = 0; i < len; i++) { 4867 for (i = 0; i < len; i++) {
4868 if (i == hwmgr->power_profile_mode) {
4869 size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4870 i, profile_name[i], "*",
4871 data->current_profile_setting.sclk_up_hyst,
4872 data->current_profile_setting.sclk_down_hyst,
4873 data->current_profile_setting.sclk_activity,
4874 data->current_profile_setting.mclk_up_hyst,
4875 data->current_profile_setting.mclk_down_hyst,
4876 data->current_profile_setting.mclk_activity);
4877 continue;
4878 }
4867 if (smu7_profiling[i].bupdate_sclk) 4879 if (smu7_profiling[i].bupdate_sclk)
4868 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ", 4880 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4869 i, profile_name[i], smu7_profiling[i].sclk_up_hyst, 4881 i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
@@ -4883,24 +4895,6 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4883 "-", "-", "-"); 4895 "-", "-", "-");
4884 } 4896 }
4885 4897
4886 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
4887 i, profile_name[i],
4888 data->custom_profile_setting.sclk_up_hyst,
4889 data->custom_profile_setting.sclk_down_hyst,
4890 data->custom_profile_setting.sclk_activity,
4891 data->custom_profile_setting.mclk_up_hyst,
4892 data->custom_profile_setting.mclk_down_hyst,
4893 data->custom_profile_setting.mclk_activity);
4894
4895 size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
4896 "*", "CURRENT",
4897 data->current_profile_setting.sclk_up_hyst,
4898 data->current_profile_setting.sclk_down_hyst,
4899 data->current_profile_setting.sclk_activity,
4900 data->current_profile_setting.mclk_up_hyst,
4901 data->current_profile_setting.mclk_down_hyst,
4902 data->current_profile_setting.mclk_activity);
4903
4904 return size; 4898 return size;
4905} 4899}
4906 4900
@@ -4939,16 +4933,16 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
4939 if (size < 8) 4933 if (size < 8)
4940 return -EINVAL; 4934 return -EINVAL;
4941 4935
4942 data->custom_profile_setting.bupdate_sclk = input[0]; 4936 tmp.bupdate_sclk = input[0];
4943 data->custom_profile_setting.sclk_up_hyst = input[1]; 4937 tmp.sclk_up_hyst = input[1];
4944 data->custom_profile_setting.sclk_down_hyst = input[2]; 4938 tmp.sclk_down_hyst = input[2];
4945 data->custom_profile_setting.sclk_activity = input[3]; 4939 tmp.sclk_activity = input[3];
4946 data->custom_profile_setting.bupdate_mclk = input[4]; 4940 tmp.bupdate_mclk = input[4];
4947 data->custom_profile_setting.mclk_up_hyst = input[5]; 4941 tmp.mclk_up_hyst = input[5];
4948 data->custom_profile_setting.mclk_down_hyst = input[6]; 4942 tmp.mclk_down_hyst = input[6];
4949 data->custom_profile_setting.mclk_activity = input[7]; 4943 tmp.mclk_activity = input[7];
4950 if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) { 4944 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
4951 memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting)); 4945 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
4952 hwmgr->power_profile_mode = mode; 4946 hwmgr->power_profile_mode = mode;
4953 } 4947 }
4954 break; 4948 break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index f40179c9ca97..b8d0bb378595 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -325,7 +325,6 @@ struct smu7_hwmgr {
325 uint16_t mem_latency_high; 325 uint16_t mem_latency_high;
326 uint16_t mem_latency_low; 326 uint16_t mem_latency_low;
327 uint32_t vr_config; 327 uint32_t vr_config;
328 struct profile_mode_setting custom_profile_setting;
329 struct profile_mode_setting current_profile_setting; 328 struct profile_mode_setting current_profile_setting;
330}; 329};
331 330
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 03bc7453f3b1..d9e92e306535 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -852,12 +852,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
852{ 852{
853 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 853 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
854 854
855 n = (n & 0xff) << 8;
856
857 if (data->power_containment_features & 855 if (data->power_containment_features &
858 POWERCONTAINMENT_FEATURE_PkgPwrLimit) 856 POWERCONTAINMENT_FEATURE_PkgPwrLimit)
859 return smum_send_msg_to_smc_with_parameter(hwmgr, 857 return smum_send_msg_to_smc_with_parameter(hwmgr,
860 PPSMC_MSG_PkgPwrSetLimit, n); 858 PPSMC_MSG_PkgPwrSetLimit, n<<8);
861 return 0; 859 return 0;
862} 860}
863 861
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3aa65bdecb0e..684ac626ac53 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -74,6 +74,7 @@ config DRM_SIL_SII8620
74 tristate "Silicon Image SII8620 HDMI/MHL bridge" 74 tristate "Silicon Image SII8620 HDMI/MHL bridge"
75 depends on OF && RC_CORE 75 depends on OF && RC_CORE
76 select DRM_KMS_HELPER 76 select DRM_KMS_HELPER
77 imply EXTCON
77 help 78 help
78 Silicon Image SII8620 HDMI/MHL bridge chip driver. 79 Silicon Image SII8620 HDMI/MHL bridge chip driver.
79 80
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 7d25c42f22db..c825c76edc1d 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -155,6 +155,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
155 state->connectors[i].state); 155 state->connectors[i].state);
156 state->connectors[i].ptr = NULL; 156 state->connectors[i].ptr = NULL;
157 state->connectors[i].state = NULL; 157 state->connectors[i].state = NULL;
158 state->connectors[i].old_state = NULL;
159 state->connectors[i].new_state = NULL;
158 drm_connector_put(connector); 160 drm_connector_put(connector);
159 } 161 }
160 162
@@ -169,6 +171,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
169 171
170 state->crtcs[i].ptr = NULL; 172 state->crtcs[i].ptr = NULL;
171 state->crtcs[i].state = NULL; 173 state->crtcs[i].state = NULL;
174 state->crtcs[i].old_state = NULL;
175 state->crtcs[i].new_state = NULL;
172 } 176 }
173 177
174 for (i = 0; i < config->num_total_plane; i++) { 178 for (i = 0; i < config->num_total_plane; i++) {
@@ -181,6 +185,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
181 state->planes[i].state); 185 state->planes[i].state);
182 state->planes[i].ptr = NULL; 186 state->planes[i].ptr = NULL;
183 state->planes[i].state = NULL; 187 state->planes[i].state = NULL;
188 state->planes[i].old_state = NULL;
189 state->planes[i].new_state = NULL;
184 } 190 }
185 191
186 for (i = 0; i < state->num_private_objs; i++) { 192 for (i = 0; i < state->num_private_objs; i++) {
@@ -190,6 +196,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
190 state->private_objs[i].state); 196 state->private_objs[i].state);
191 state->private_objs[i].ptr = NULL; 197 state->private_objs[i].ptr = NULL;
192 state->private_objs[i].state = NULL; 198 state->private_objs[i].state = NULL;
199 state->private_objs[i].old_state = NULL;
200 state->private_objs[i].new_state = NULL;
193 } 201 }
194 state->num_private_objs = 0; 202 state->num_private_objs = 0;
195 203
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index abd84cbcf1c2..09c4bc0b1859 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -954,8 +954,6 @@ static int hdmi_create_connector(struct drm_encoder *encoder)
954 drm_mode_connector_attach_encoder(connector, encoder); 954 drm_mode_connector_attach_encoder(connector, encoder);
955 955
956 if (hdata->bridge) { 956 if (hdata->bridge) {
957 encoder->bridge = hdata->bridge;
958 hdata->bridge->encoder = encoder;
959 ret = drm_bridge_attach(encoder, hdata->bridge, NULL); 957 ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
960 if (ret) 958 if (ret)
961 DRM_ERROR("Failed to attach bridge\n"); 959 DRM_ERROR("Failed to attach bridge\n");
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 257299ec95c4..272c79f5f5bf 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -473,7 +473,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
473 chroma_addr[1] = chroma_addr[0] + 0x40; 473 chroma_addr[1] = chroma_addr[0] + 0x40;
474 } else { 474 } else {
475 luma_addr[1] = luma_addr[0] + fb->pitches[0]; 475 luma_addr[1] = luma_addr[0] + fb->pitches[0];
476 chroma_addr[1] = chroma_addr[0] + fb->pitches[0]; 476 chroma_addr[1] = chroma_addr[0] + fb->pitches[1];
477 } 477 }
478 } else { 478 } else {
479 luma_addr[1] = 0; 479 luma_addr[1] = 0;
@@ -482,6 +482,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
482 482
483 spin_lock_irqsave(&ctx->reg_slock, flags); 483 spin_lock_irqsave(&ctx->reg_slock, flags);
484 484
485 vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
485 /* interlace or progressive scan mode */ 486 /* interlace or progressive scan mode */
486 val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); 487 val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
487 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP); 488 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
@@ -495,21 +496,23 @@ static void vp_video_buffer(struct mixer_context *ctx,
495 vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | 496 vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
496 VP_IMG_VSIZE(fb->height)); 497 VP_IMG_VSIZE(fb->height));
497 /* chroma plane for NV12/NV21 is half the height of the luma plane */ 498 /* chroma plane for NV12/NV21 is half the height of the luma plane */
498 vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | 499 vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
499 VP_IMG_VSIZE(fb->height / 2)); 500 VP_IMG_VSIZE(fb->height / 2));
500 501
501 vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w); 502 vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
502 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
503 vp_reg_write(ctx, VP_SRC_H_POSITION, 503 vp_reg_write(ctx, VP_SRC_H_POSITION,
504 VP_SRC_H_POSITION_VAL(state->src.x)); 504 VP_SRC_H_POSITION_VAL(state->src.x));
505 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
506
507 vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w); 505 vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
508 vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x); 506 vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
507
509 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 508 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
509 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2);
510 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2);
510 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2); 511 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
511 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2); 512 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
512 } else { 513 } else {
514 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
515 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
513 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h); 516 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
514 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y); 517 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
515 } 518 }
@@ -699,6 +702,15 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
699 702
700 /* interlace scan need to check shadow register */ 703 /* interlace scan need to check shadow register */
701 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 704 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
705 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
706 vp_reg_read(ctx, VP_SHADOW_UPDATE))
707 goto out;
708
709 base = mixer_reg_read(ctx, MXR_CFG);
710 shadow = mixer_reg_read(ctx, MXR_CFG_S);
711 if (base != shadow)
712 goto out;
713
702 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0)); 714 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
703 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0)); 715 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
704 if (base != shadow) 716 if (base != shadow)
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index c311f571bdf9..189cfa2470a8 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -47,6 +47,7 @@
47#define MXR_MO 0x0304 47#define MXR_MO 0x0304
48#define MXR_RESOLUTION 0x0310 48#define MXR_RESOLUTION 0x0310
49 49
50#define MXR_CFG_S 0x2004
50#define MXR_GRAPHIC0_BASE_S 0x2024 51#define MXR_GRAPHIC0_BASE_S 0x2024
51#define MXR_GRAPHIC1_BASE_S 0x2044 52#define MXR_GRAPHIC1_BASE_S 0x2044
52 53
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 32d24c69da3c..704ddb4d3ca7 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2302,9 +2302,44 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2302 return 0; 2302 return 0;
2303} 2303}
2304 2304
2305static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2306{
2307 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2308 struct intel_crtc *crtc;
2309 struct intel_crtc_state *crtc_state;
2310 int vco, i;
2311
2312 vco = intel_state->cdclk.logical.vco;
2313 if (!vco)
2314 vco = dev_priv->skl_preferred_vco_freq;
2315
2316 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2317 if (!crtc_state->base.enable)
2318 continue;
2319
2320 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2321 continue;
2322
2323 /*
2324 * DPLL0 VCO may need to be adjusted to get the correct
2325 * clock for eDP. This will affect cdclk as well.
2326 */
2327 switch (crtc_state->port_clock / 2) {
2328 case 108000:
2329 case 216000:
2330 vco = 8640000;
2331 break;
2332 default:
2333 vco = 8100000;
2334 break;
2335 }
2336 }
2337
2338 return vco;
2339}
2340
2305static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) 2341static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2306{ 2342{
2307 struct drm_i915_private *dev_priv = to_i915(state->dev);
2308 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 2343 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2309 int min_cdclk, cdclk, vco; 2344 int min_cdclk, cdclk, vco;
2310 2345
@@ -2312,9 +2347,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2312 if (min_cdclk < 0) 2347 if (min_cdclk < 0)
2313 return min_cdclk; 2348 return min_cdclk;
2314 2349
2315 vco = intel_state->cdclk.logical.vco; 2350 vco = skl_dpll0_vco(intel_state);
2316 if (!vco)
2317 vco = dev_priv->skl_preferred_vco_freq;
2318 2351
2319 /* 2352 /*
2320 * FIXME should also account for plane ratio 2353 * FIXME should also account for plane ratio
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b48fd2561fe..56004ffbd8bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15178,6 +15178,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
15178 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); 15178 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15179 if (crtc_state->base.active) { 15179 if (crtc_state->base.active) {
15180 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); 15180 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15181 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15182 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15181 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); 15183 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15182 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); 15184 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15183 15185
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9a4a51e79fa1..b7b4cfdeb974 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1881,26 +1881,6 @@ found:
1881 reduce_m_n); 1881 reduce_m_n);
1882 } 1882 }
1883 1883
1884 /*
1885 * DPLL0 VCO may need to be adjusted to get the correct
1886 * clock for eDP. This will affect cdclk as well.
1887 */
1888 if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1889 int vco;
1890
1891 switch (pipe_config->port_clock / 2) {
1892 case 108000:
1893 case 216000:
1894 vco = 8640000;
1895 break;
1896 default:
1897 vco = 8100000;
1898 break;
1899 }
1900
1901 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1902 }
1903
1904 if (!HAS_DDI(dev_priv)) 1884 if (!HAS_DDI(dev_priv))
1905 intel_dp_set_clock(encoder, pipe_config); 1885 intel_dp_set_clock(encoder, pipe_config);
1906 1886
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index d35d2d50f595..8691c86f579c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -326,7 +326,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
326 326
327 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); 327 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
328 POSTING_READ(lvds_encoder->reg); 328 POSTING_READ(lvds_encoder->reg);
329 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) 329
330 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
330 DRM_ERROR("timed out waiting for panel to power on\n"); 331 DRM_ERROR("timed out waiting for panel to power on\n");
331 332
332 intel_panel_enable_backlight(pipe_config, conn_state); 333 intel_panel_enable_backlight(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 6f402c4f2bdd..ab61c038f42c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -214,7 +214,6 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
214 INIT_LIST_HEAD(&nvbo->entry); 214 INIT_LIST_HEAD(&nvbo->entry);
215 INIT_LIST_HEAD(&nvbo->vma_list); 215 INIT_LIST_HEAD(&nvbo->vma_list);
216 nvbo->bo.bdev = &drm->ttm.bdev; 216 nvbo->bo.bdev = &drm->ttm.bdev;
217 nvbo->cli = cli;
218 217
219 /* This is confusing, and doesn't actually mean we want an uncached 218 /* This is confusing, and doesn't actually mean we want an uncached
220 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 219 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h
index be8e00b49cde..73c48440d4d7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -26,8 +26,6 @@ struct nouveau_bo {
26 26
27 struct list_head vma_list; 27 struct list_head vma_list;
28 28
29 struct nouveau_cli *cli;
30
31 unsigned contig:1; 29 unsigned contig:1;
32 unsigned page:5; 30 unsigned page:5;
33 unsigned kind:8; 31 unsigned kind:8;
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index dff51a0ee028..8c093ca4222e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -63,7 +63,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
63 struct ttm_mem_reg *reg) 63 struct ttm_mem_reg *reg)
64{ 64{
65 struct nouveau_bo *nvbo = nouveau_bo(bo); 65 struct nouveau_bo *nvbo = nouveau_bo(bo);
66 struct nouveau_drm *drm = nvbo->cli->drm; 66 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
67 struct nouveau_mem *mem; 67 struct nouveau_mem *mem;
68 int ret; 68 int ret;
69 69
@@ -103,7 +103,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
103 struct ttm_mem_reg *reg) 103 struct ttm_mem_reg *reg)
104{ 104{
105 struct nouveau_bo *nvbo = nouveau_bo(bo); 105 struct nouveau_bo *nvbo = nouveau_bo(bo);
106 struct nouveau_drm *drm = nvbo->cli->drm; 106 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
107 struct nouveau_mem *mem; 107 struct nouveau_mem *mem;
108 int ret; 108 int ret;
109 109
@@ -131,7 +131,7 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man,
131 struct ttm_mem_reg *reg) 131 struct ttm_mem_reg *reg)
132{ 132{
133 struct nouveau_bo *nvbo = nouveau_bo(bo); 133 struct nouveau_bo *nvbo = nouveau_bo(bo);
134 struct nouveau_drm *drm = nvbo->cli->drm; 134 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
135 struct nouveau_mem *mem; 135 struct nouveau_mem *mem;
136 int ret; 136 int ret;
137 137
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 8bd739cfd00d..2b3ccd850750 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -3264,10 +3264,11 @@ nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3264 3264
3265 drm_connector_unregister(&mstc->connector); 3265 drm_connector_unregister(&mstc->connector);
3266 3266
3267 drm_modeset_lock_all(drm->dev);
3268 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 3267 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3268
3269 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
3269 mstc->port = NULL; 3270 mstc->port = NULL;
3270 drm_modeset_unlock_all(drm->dev); 3271 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
3271 3272
3272 drm_connector_unreference(&mstc->connector); 3273 drm_connector_unreference(&mstc->connector);
3273} 3274}
@@ -3277,9 +3278,7 @@ nv50_mstm_register_connector(struct drm_connector *connector)
3277{ 3278{
3278 struct nouveau_drm *drm = nouveau_drm(connector->dev); 3279 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3279 3280
3280 drm_modeset_lock_all(drm->dev);
3281 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 3281 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3282 drm_modeset_unlock_all(drm->dev);
3283 3282
3284 drm_connector_register(connector); 3283 drm_connector_register(connector);
3285} 3284}
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 5e2e65e88847..7f3ac6b13b56 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -828,6 +828,12 @@ static void dispc_ovl_set_scale_coef(struct dispc_device *dispc,
828 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); 828 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
829 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); 829 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
830 830
831 if (!h_coef || !v_coef) {
832 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n",
833 __func__);
834 return;
835 }
836
831 for (i = 0; i < 8; i++) { 837 for (i = 0; i < 8; i++) {
832 u32 h, hv; 838 u32 h, hv;
833 839
@@ -2342,7 +2348,7 @@ static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc,
2342 } 2348 }
2343 2349
2344 if (in_width > maxsinglelinewidth) { 2350 if (in_width > maxsinglelinewidth) {
2345 DSSERR("Cannot scale max input width exceeded"); 2351 DSSERR("Cannot scale max input width exceeded\n");
2346 return -EINVAL; 2352 return -EINVAL;
2347 } 2353 }
2348 return 0; 2354 return 0;
@@ -2424,13 +2430,13 @@ again:
2424 } 2430 }
2425 2431
2426 if (in_width > (maxsinglelinewidth * 2)) { 2432 if (in_width > (maxsinglelinewidth * 2)) {
2427 DSSERR("Cannot setup scaling"); 2433 DSSERR("Cannot setup scaling\n");
2428 DSSERR("width exceeds maximum width possible"); 2434 DSSERR("width exceeds maximum width possible\n");
2429 return -EINVAL; 2435 return -EINVAL;
2430 } 2436 }
2431 2437
2432 if (in_width > maxsinglelinewidth && *five_taps) { 2438 if (in_width > maxsinglelinewidth && *five_taps) {
2433 DSSERR("cannot setup scaling with five taps"); 2439 DSSERR("cannot setup scaling with five taps\n");
2434 return -EINVAL; 2440 return -EINVAL;
2435 } 2441 }
2436 return 0; 2442 return 0;
@@ -2472,7 +2478,7 @@ static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc,
2472 in_width > maxsinglelinewidth && ++*decim_x); 2478 in_width > maxsinglelinewidth && ++*decim_x);
2473 2479
2474 if (in_width > maxsinglelinewidth) { 2480 if (in_width > maxsinglelinewidth) {
2475 DSSERR("Cannot scale width exceeds max line width"); 2481 DSSERR("Cannot scale width exceeds max line width\n");
2476 return -EINVAL; 2482 return -EINVAL;
2477 } 2483 }
2478 2484
@@ -2490,7 +2496,7 @@ static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc,
2490 * bandwidth. Despite what theory says this appears to 2496 * bandwidth. Despite what theory says this appears to
2491 * be true also for 16-bit color formats. 2497 * be true also for 16-bit color formats.
2492 */ 2498 */
2493 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x); 2499 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x);
2494 2500
2495 return -EINVAL; 2501 return -EINVAL;
2496 } 2502 }
@@ -4633,7 +4639,7 @@ static int dispc_errata_i734_wa_init(struct dispc_device *dispc)
4633 i734_buf.size, &i734_buf.paddr, 4639 i734_buf.size, &i734_buf.paddr,
4634 GFP_KERNEL); 4640 GFP_KERNEL);
4635 if (!i734_buf.vaddr) { 4641 if (!i734_buf.vaddr) {
4636 dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed", 4642 dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed\n",
4637 __func__); 4643 __func__);
4638 return -ENOMEM; 4644 return -ENOMEM;
4639 } 4645 }
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index 97c88861d67a..5879f45f6fc9 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -679,7 +679,7 @@ static int hdmi_audio_config(struct device *dev,
679 struct omap_dss_audio *dss_audio) 679 struct omap_dss_audio *dss_audio)
680{ 680{
681 struct omap_hdmi *hd = dev_get_drvdata(dev); 681 struct omap_hdmi *hd = dev_get_drvdata(dev);
682 int ret; 682 int ret = 0;
683 683
684 mutex_lock(&hd->lock); 684 mutex_lock(&hd->lock);
685 685
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index 35ed2add6189..813ba42f2753 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -922,8 +922,13 @@ int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
922{ 922{
923 const struct hdmi4_features *features; 923 const struct hdmi4_features *features;
924 struct resource *res; 924 struct resource *res;
925 const struct soc_device_attribute *soc;
925 926
926 features = soc_device_match(hdmi4_soc_devices)->data; 927 soc = soc_device_match(hdmi4_soc_devices);
928 if (!soc)
929 return -ENODEV;
930
931 features = soc->data;
927 core->cts_swmode = features->cts_swmode; 932 core->cts_swmode = features->cts_swmode;
928 core->audio_use_mclk = features->audio_use_mclk; 933 core->audio_use_mclk = features->audio_use_mclk;
929 934
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index d28da9ac3e90..ae1a001d1b83 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -671,7 +671,7 @@ static int hdmi_audio_config(struct device *dev,
671 struct omap_dss_audio *dss_audio) 671 struct omap_dss_audio *dss_audio)
672{ 672{
673 struct omap_hdmi *hd = dev_get_drvdata(dev); 673 struct omap_hdmi *hd = dev_get_drvdata(dev);
674 int ret; 674 int ret = 0;
675 675
676 mutex_lock(&hd->lock); 676 mutex_lock(&hd->lock);
677 677
diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c
index a0d7b1d905e8..5cde26ac937b 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -121,6 +121,9 @@ static int omap_connector_get_modes(struct drm_connector *connector)
121 if (dssdrv->read_edid) { 121 if (dssdrv->read_edid) {
122 void *edid = kzalloc(MAX_EDID, GFP_KERNEL); 122 void *edid = kzalloc(MAX_EDID, GFP_KERNEL);
123 123
124 if (!edid)
125 return 0;
126
124 if ((dssdrv->read_edid(dssdev, edid, MAX_EDID) > 0) && 127 if ((dssdrv->read_edid(dssdev, edid, MAX_EDID) > 0) &&
125 drm_edid_is_valid(edid)) { 128 drm_edid_is_valid(edid)) {
126 drm_mode_connector_update_edid_property( 129 drm_mode_connector_update_edid_property(
@@ -139,6 +142,9 @@ static int omap_connector_get_modes(struct drm_connector *connector)
139 struct drm_display_mode *mode = drm_mode_create(dev); 142 struct drm_display_mode *mode = drm_mode_create(dev);
140 struct videomode vm = {0}; 143 struct videomode vm = {0};
141 144
145 if (!mode)
146 return 0;
147
142 dssdrv->get_timings(dssdev, &vm); 148 dssdrv->get_timings(dssdev, &vm);
143 149
144 drm_display_mode_from_videomode(&vm, mode); 150 drm_display_mode_from_videomode(&vm, mode);
@@ -200,6 +206,10 @@ static int omap_connector_mode_valid(struct drm_connector *connector,
200 if (!r) { 206 if (!r) {
201 /* check if vrefresh is still valid */ 207 /* check if vrefresh is still valid */
202 new_mode = drm_mode_duplicate(dev, mode); 208 new_mode = drm_mode_duplicate(dev, mode);
209
210 if (!new_mode)
211 return MODE_BAD;
212
203 new_mode->clock = vm.pixelclock / 1000; 213 new_mode->clock = vm.pixelclock / 1000;
204 new_mode->vrefresh = 0; 214 new_mode->vrefresh = 0;
205 if (mode->vrefresh == drm_mode_vrefresh(new_mode)) 215 if (mode->vrefresh == drm_mode_vrefresh(new_mode))
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index f9fa1c90b35c..401c02e9e6b2 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -401,12 +401,16 @@ int tiler_unpin(struct tiler_block *block)
401struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w, 401struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
402 u16 h, u16 align) 402 u16 h, u16 align)
403{ 403{
404 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); 404 struct tiler_block *block;
405 u32 min_align = 128; 405 u32 min_align = 128;
406 int ret; 406 int ret;
407 unsigned long flags; 407 unsigned long flags;
408 u32 slot_bytes; 408 u32 slot_bytes;
409 409
410 block = kzalloc(sizeof(*block), GFP_KERNEL);
411 if (!block)
412 return ERR_PTR(-ENOMEM);
413
410 BUG_ON(!validfmt(fmt)); 414 BUG_ON(!validfmt(fmt));
411 415
412 /* convert width/height to slots */ 416 /* convert width/height to slots */
diff --git a/drivers/gpu/drm/omapdrm/tcm-sita.c b/drivers/gpu/drm/omapdrm/tcm-sita.c
index d7f7bc9f061a..817be3c41863 100644
--- a/drivers/gpu/drm/omapdrm/tcm-sita.c
+++ b/drivers/gpu/drm/omapdrm/tcm-sita.c
@@ -90,7 +90,7 @@ static int l2r_t2b(u16 w, u16 h, u16 a, s16 offset,
90{ 90{
91 int i; 91 int i;
92 unsigned long index; 92 unsigned long index;
93 bool area_free; 93 bool area_free = false;
94 unsigned long slots_per_band = PAGE_SIZE / slot_bytes; 94 unsigned long slots_per_band = PAGE_SIZE / slot_bytes;
95 unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0; 95 unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0;
96 unsigned long curr_bit = bit_offset; 96 unsigned long curr_bit = bit_offset;
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index f0481b7b60c5..06c94e3a5f15 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -910,7 +910,8 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
910 while (npages >= HPAGE_PMD_NR) { 910 while (npages >= HPAGE_PMD_NR) {
911 gfp_t huge_flags = gfp_flags; 911 gfp_t huge_flags = gfp_flags;
912 912
913 huge_flags |= GFP_TRANSHUGE; 913 huge_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
914 __GFP_KSWAPD_RECLAIM;
914 huge_flags &= ~__GFP_MOVABLE; 915 huge_flags &= ~__GFP_MOVABLE;
915 huge_flags &= ~__GFP_COMP; 916 huge_flags &= ~__GFP_COMP;
916 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); 917 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
@@ -1027,11 +1028,15 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
1027 GFP_USER | GFP_DMA32, "uc dma", 0); 1028 GFP_USER | GFP_DMA32, "uc dma", 0);
1028 1029
1029 ttm_page_pool_init_locked(&_manager->wc_pool_huge, 1030 ttm_page_pool_init_locked(&_manager->wc_pool_huge,
1030 GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP), 1031 (GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1032 __GFP_KSWAPD_RECLAIM) &
1033 ~(__GFP_MOVABLE | __GFP_COMP),
1031 "wc huge", order); 1034 "wc huge", order);
1032 1035
1033 ttm_page_pool_init_locked(&_manager->uc_pool_huge, 1036 ttm_page_pool_init_locked(&_manager->uc_pool_huge,
1034 GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP) 1037 (GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
1038 __GFP_KSWAPD_RECLAIM) &
1039 ~(__GFP_MOVABLE | __GFP_COMP)
1035 , "uc huge", order); 1040 , "uc huge", order);
1036 1041
1037 _manager->options.max_size = max_pages; 1042 _manager->options.max_size = max_pages;
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 8a25d1974385..f63d99c302e4 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -910,7 +910,8 @@ static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt *ttm_dma, bool huge)
910 gfp_flags |= __GFP_ZERO; 910 gfp_flags |= __GFP_ZERO;
911 911
912 if (huge) { 912 if (huge) {
913 gfp_flags |= GFP_TRANSHUGE; 913 gfp_flags |= GFP_TRANSHUGE_LIGHT | __GFP_NORETRY |
914 __GFP_KSWAPD_RECLAIM;
914 gfp_flags &= ~__GFP_MOVABLE; 915 gfp_flags &= ~__GFP_MOVABLE;
915 gfp_flags &= ~__GFP_COMP; 916 gfp_flags &= ~__GFP_COMP;
916 } 917 }
diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index 72c9dbd81d7f..f185812970da 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -96,7 +96,6 @@ struct vc4_dpi {
96 struct platform_device *pdev; 96 struct platform_device *pdev;
97 97
98 struct drm_encoder *encoder; 98 struct drm_encoder *encoder;
99 struct drm_connector *connector;
100 99
101 void __iomem *regs; 100 void __iomem *regs;
102 101
@@ -164,14 +163,31 @@ static void vc4_dpi_encoder_disable(struct drm_encoder *encoder)
164 163
165static void vc4_dpi_encoder_enable(struct drm_encoder *encoder) 164static void vc4_dpi_encoder_enable(struct drm_encoder *encoder)
166{ 165{
166 struct drm_device *dev = encoder->dev;
167 struct drm_display_mode *mode = &encoder->crtc->mode; 167 struct drm_display_mode *mode = &encoder->crtc->mode;
168 struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder); 168 struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder);
169 struct vc4_dpi *dpi = vc4_encoder->dpi; 169 struct vc4_dpi *dpi = vc4_encoder->dpi;
170 struct drm_connector_list_iter conn_iter;
171 struct drm_connector *connector = NULL, *connector_scan;
170 u32 dpi_c = DPI_ENABLE | DPI_OUTPUT_ENABLE_MODE; 172 u32 dpi_c = DPI_ENABLE | DPI_OUTPUT_ENABLE_MODE;
171 int ret; 173 int ret;
172 174
173 if (dpi->connector->display_info.num_bus_formats) { 175 /* Look up the connector attached to DPI so we can get the
174 u32 bus_format = dpi->connector->display_info.bus_formats[0]; 176 * bus_format. Ideally the bridge would tell us the
177 * bus_format we want, but it doesn't yet, so assume that it's
178 * uniform throughout the bridge chain.
179 */
180 drm_connector_list_iter_begin(dev, &conn_iter);
181 drm_for_each_connector_iter(connector_scan, &conn_iter) {
182 if (connector_scan->encoder == encoder) {
183 connector = connector_scan;
184 break;
185 }
186 }
187 drm_connector_list_iter_end(&conn_iter);
188
189 if (connector && connector->display_info.num_bus_formats) {
190 u32 bus_format = connector->display_info.bus_formats[0];
175 191
176 switch (bus_format) { 192 switch (bus_format) {
177 case MEDIA_BUS_FMT_RGB888_1X24: 193 case MEDIA_BUS_FMT_RGB888_1X24:
@@ -199,6 +215,9 @@ static void vc4_dpi_encoder_enable(struct drm_encoder *encoder)
199 DRM_ERROR("Unknown media bus format %d\n", bus_format); 215 DRM_ERROR("Unknown media bus format %d\n", bus_format);
200 break; 216 break;
201 } 217 }
218 } else {
219 /* Default to 24bit if no connector found. */
220 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
202 } 221 }
203 222
204 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 223 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index ce39390be389..13dcaad06798 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -503,7 +503,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
503 * the scl fields here. 503 * the scl fields here.
504 */ 504 */
505 if (num_planes == 1) { 505 if (num_planes == 1) {
506 scl0 = vc4_get_scl_field(state, 1); 506 scl0 = vc4_get_scl_field(state, 0);
507 scl1 = scl0; 507 scl1 = scl0;
508 } else { 508 } else {
509 scl0 = vc4_get_scl_field(state, 1); 509 scl0 = vc4_get_scl_field(state, 1);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 08:59:42 -0400