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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-07-05 16:09:08 -0400
committerIngo Molnar <mingo@kernel.org>2016-07-08 05:00:06 -0400
commitca22312dc840065206285626829ceed8bb4df88c (patch)
tree72bdccda640061eedf0330cd47af411dff0fc110
parente99a0745bdf8a5f7e3126a686846af4aeb852cc9 (diff)
x86/platform/intel-mid: Extend PWRMU to support Penwell
Intel Penwell is one of the first SoCs in Intel MID series. It has slightly older version of PWRMU IP, though it is compatible with one found on Intel Tangier. Since we are not using (yet) any advanced stuff in the driver we may safely re-use what it's done for Intel Tangier for now. Extend PWRMU driver to support Intel Penwell by adding PCI ID and re-using existing ->set_initial_state() function. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1467749348-100518-2-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/platform/intel-mid/pwr.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 59faf05d23f5..5bc90dd102d4 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -75,6 +75,7 @@
75#define LSS_PWS_BITS 2 /* power state width */ 75#define LSS_PWS_BITS 2 /* power state width */
76 76
77/* Supported device IDs */ 77/* Supported device IDs */
78#define PCI_DEVICE_ID_PENWELL 0x0828
78#define PCI_DEVICE_ID_TANGIER 0x11a1 79#define PCI_DEVICE_ID_TANGIER 0x11a1
79 80
80struct mid_pwr_dev { 81struct mid_pwr_dev {
@@ -354,7 +355,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
354 return 0; 355 return 0;
355} 356}
356 357
357static int tng_set_initial_state(struct mid_pwr *pwr) 358static int mid_set_initial_state(struct mid_pwr *pwr)
358{ 359{
359 unsigned int i, j; 360 unsigned int i, j;
360 int ret; 361 int ret;
@@ -397,12 +398,13 @@ static int tng_set_initial_state(struct mid_pwr *pwr)
397 return 0; 398 return 0;
398} 399}
399 400
400static const struct mid_pwr_device_info tng_info = { 401static const struct mid_pwr_device_info mid_info = {
401 .set_initial_state = tng_set_initial_state, 402 .set_initial_state = mid_set_initial_state,
402}; 403};
403 404
404static const struct pci_device_id mid_pwr_pci_ids[] = { 405static const struct pci_device_id mid_pwr_pci_ids[] = {
405 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info }, 406 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
407 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
406 {} 408 {}
407}; 409};
408MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids); 410MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);