diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2016-03-15 11:55:41 -0400 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-05-09 10:04:15 -0400 |
| commit | c9c3c6eecc5533d14bb9bc82319257eb8bc52768 (patch) | |
| tree | a639c8aca7f7e360a7d51c148da846c5fb9e8c98 | |
| parent | 6f339dc2719eb01448c70fe3d56287d1eb9bd67e (diff) | |
clk: rockchip: simplify GRF handling in pll clocks
With the previous commit, the clock drivers now know at init time if the
GRF regmap is available. That means if it isn't available then, it also
won't become available later and we can therefore switch PLLs, that need
the GRF for the lock-status, to read-only mode - similar behaviour as the
aborting of rate changes we did before.
This saves some conditionals on every rate change and we can also drop
the rockchip_clk_get_grf function completely.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 30 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 5 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 1 |
3 files changed, 3 insertions, 33 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 8ac73bc7f93d..76e278d679ba 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c | |||
| @@ -92,15 +92,10 @@ static long rockchip_pll_round_rate(struct clk_hw *hw, | |||
| 92 | */ | 92 | */ |
| 93 | static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) | 93 | static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) |
| 94 | { | 94 | { |
| 95 | struct regmap *grf = rockchip_clk_get_grf(pll->ctx); | 95 | struct regmap *grf = pll->ctx->grf; |
| 96 | unsigned int val; | 96 | unsigned int val; |
| 97 | int delay = 24000000, ret; | 97 | int delay = 24000000, ret; |
| 98 | 98 | ||
| 99 | if (IS_ERR(grf)) { | ||
| 100 | pr_err("%s: grf regmap not available\n", __func__); | ||
| 101 | return PTR_ERR(grf); | ||
| 102 | } | ||
| 103 | |||
| 104 | while (delay > 0) { | 99 | while (delay > 0) { |
| 105 | ret = regmap_read(grf, pll->lock_offset, &val); | 100 | ret = regmap_read(grf, pll->lock_offset, &val); |
| 106 | if (ret) { | 101 | if (ret) { |
| @@ -253,13 +248,6 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, | |||
| 253 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); | 248 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); |
| 254 | const struct rockchip_pll_rate_table *rate; | 249 | const struct rockchip_pll_rate_table *rate; |
| 255 | unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); | 250 | unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); |
| 256 | struct regmap *grf = rockchip_clk_get_grf(pll->ctx); | ||
| 257 | |||
| 258 | if (IS_ERR(grf)) { | ||
| 259 | pr_debug("%s: grf regmap not available, aborting rate change\n", | ||
| 260 | __func__); | ||
| 261 | return PTR_ERR(grf); | ||
| 262 | } | ||
| 263 | 251 | ||
| 264 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", | 252 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", |
| 265 | __func__, __clk_get_name(hw->clk), old_rate, drate, prate); | 253 | __func__, __clk_get_name(hw->clk), old_rate, drate, prate); |
| @@ -492,13 +480,6 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, | |||
| 492 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); | 480 | struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); |
| 493 | const struct rockchip_pll_rate_table *rate; | 481 | const struct rockchip_pll_rate_table *rate; |
| 494 | unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); | 482 | unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); |
| 495 | struct regmap *grf = rockchip_clk_get_grf(pll->ctx); | ||
| 496 | |||
| 497 | if (IS_ERR(grf)) { | ||
| 498 | pr_debug("%s: grf regmap not available, aborting rate change\n", | ||
| 499 | __func__); | ||
| 500 | return PTR_ERR(grf); | ||
| 501 | } | ||
| 502 | 483 | ||
| 503 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", | 484 | pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", |
| 504 | __func__, clk_hw_get_name(hw), old_rate, drate, prate); | 485 | __func__, clk_hw_get_name(hw), old_rate, drate, prate); |
| @@ -565,11 +546,6 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) | |||
| 565 | rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); | 546 | rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); |
| 566 | if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf | 547 | if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf |
| 567 | || rate->nb != cur.nb) { | 548 | || rate->nb != cur.nb) { |
| 568 | struct regmap *grf = rockchip_clk_get_grf(pll->ctx); | ||
| 569 | |||
| 570 | if (IS_ERR(grf)) | ||
| 571 | return; | ||
| 572 | |||
| 573 | pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", | 549 | pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", |
| 574 | __func__, clk_hw_get_name(hw)); | 550 | __func__, clk_hw_get_name(hw)); |
| 575 | rockchip_rk3066_pll_set_params(pll, rate); | 551 | rockchip_rk3066_pll_set_params(pll, rate); |
| @@ -943,13 +919,13 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, | |||
| 943 | 919 | ||
| 944 | switch (pll_type) { | 920 | switch (pll_type) { |
| 945 | case pll_rk3036: | 921 | case pll_rk3036: |
| 946 | if (!pll->rate_table) | 922 | if (!pll->rate_table || IS_ERR(ctx->grf)) |
| 947 | init.ops = &rockchip_rk3036_pll_clk_norate_ops; | 923 | init.ops = &rockchip_rk3036_pll_clk_norate_ops; |
| 948 | else | 924 | else |
| 949 | init.ops = &rockchip_rk3036_pll_clk_ops; | 925 | init.ops = &rockchip_rk3036_pll_clk_ops; |
| 950 | break; | 926 | break; |
| 951 | case pll_rk3066: | 927 | case pll_rk3066: |
| 952 | if (!pll->rate_table) | 928 | if (!pll->rate_table || IS_ERR(ctx->grf)) |
| 953 | init.ops = &rockchip_rk3066_pll_clk_norate_ops; | 929 | init.ops = &rockchip_rk3066_pll_clk_norate_ops; |
| 954 | else | 930 | else |
| 955 | init.ops = &rockchip_rk3066_pll_clk_ops; | 931 | init.ops = &rockchip_rk3066_pll_clk_ops; |
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 9f99a4213d02..7ffd134995f2 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c | |||
| @@ -365,11 +365,6 @@ void __init rockchip_clk_of_add_provider(struct device_node *np, | |||
| 365 | pr_err("%s: could not register clk provider\n", __func__); | 365 | pr_err("%s: could not register clk provider\n", __func__); |
| 366 | } | 366 | } |
| 367 | 367 | ||
| 368 | struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx) | ||
| 369 | { | ||
| 370 | return ctx->grf; | ||
| 371 | } | ||
| 372 | |||
| 373 | void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, | 368 | void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, |
| 374 | struct clk *clk, unsigned int id) | 369 | struct clk *clk, unsigned int id) |
| 375 | { | 370 | { |
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1abb7d05d1c7..2194ffa8c9fd 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h | |||
| @@ -600,7 +600,6 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, | |||
| 600 | void __iomem *base, unsigned long nr_clks); | 600 | void __iomem *base, unsigned long nr_clks); |
| 601 | void rockchip_clk_of_add_provider(struct device_node *np, | 601 | void rockchip_clk_of_add_provider(struct device_node *np, |
| 602 | struct rockchip_clk_provider *ctx); | 602 | struct rockchip_clk_provider *ctx); |
| 603 | struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx); | ||
| 604 | void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, | 603 | void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, |
| 605 | struct clk *clk, unsigned int id); | 604 | struct clk *clk, unsigned int id); |
| 606 | void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, | 605 | void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, |