Merge branch 'Update-MT7629-to-support-PHYLINK-API'

MarkLee says:

====================
Update MT7629 to support PHYLINK API

This patch set has two goals :
	1. Fix mt7629 GMII mode issue after apply mediatek
	   PHYLINK support patch.
	2. Update mt7629 dts to reflect the latest dt-binding
	   with PHYLINK support.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

3 files changed, 13 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
index 3621b7d2b22a..9980c10c6e29 100644
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
@@ -66,9 +66,21 @@
         pinctrl-1 = <&ephy_leds_pins>;
         status = "okay";
 
+        gmac0: mac@0 {
+                compatible = "mediatek,eth-mac";
+                reg = <0>;
+                phy-mode = "2500base-x";
+                fixed-link {
+                        speed = <2500>;
+                        full-duplex;
+                        pause;
+                };
+        };
+
         gmac1: mac@1 {
                 compatible = "mediatek,eth-mac";
                 reg = <1>;
+                phy-mode = "gmii";
                 phy-handle = <&phy0>;
         };
 
@@ -78,7 +90,6 @@
 
                 phy0: ethernet-phy@0 {
                         reg = <0>;
-                        phy-mode = "gmii";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
index 9608bc2ccb3f..867b88103b9d 100644
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -468,14 +468,12 @@
                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
                         reg = <0x1b128000 0x3000>;
                         #clock-cells = <1>;
-                        mediatek,physpeed = "2500";
                 };
 
                 sgmiisys1: syscon@1b130000 {
                         compatible = "mediatek,mt7629-sgmiisys", "syscon";
                         reg = <0x1b130000 0x3000>;
                         #clock-cells = <1>;
-                        mediatek,physpeed = "2500";
                 };
         };
 };
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index c61069340f4f..703adb96429e 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -261,6 +261,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
                 ge_mode = 0;
                 switch (state->interface) {
                 case PHY_INTERFACE_MODE_MII:
+                case PHY_INTERFACE_MODE_GMII:
                         ge_mode = 1;
                         break;
                 case PHY_INTERFACE_MODE_REVMII: