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authorAlexis Ballier <aballier@gentoo.org>2015-08-13 13:27:33 -0400
committerKukjin Kim <kgene@kernel.org>2015-08-13 13:30:58 -0400
commitc8b34e36ca1a3e4c8ada87acefbb25119ee89347 (patch)
treef4b7d3a3e9ef7bf0135b493cd48e5f8928201212
parente0b12512b40c7a1cc0825773d118ecfdb464be41 (diff)
ARM: dts: enable SPI1 for exynos4412-odroidu3
SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier <aballier@gentoo.org> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidu3.dts8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 44684e57ead1..8632f35c6c26 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15#include "exynos4412-odroid-common.dtsi" 15#include "exynos4412-odroid-common.dtsi"
16#include <dt-bindings/gpio/gpio.h>
16 17
17/ { 18/ {
18 model = "Hardkernel ODROID-U3 board based on Exynos4412"; 19 model = "Hardkernel ODROID-U3 board based on Exynos4412";
@@ -61,3 +62,10 @@
61 "Speakers", "SPKL", 62 "Speakers", "SPKL",
62 "Speakers", "SPKR"; 63 "Speakers", "SPKR";
63}; 64};
65
66&spi_1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&spi1_bus>;
69 cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
70 status = "okay";
71};