diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-12-02 23:10:42 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-22 22:39:04 -0500 |
commit | c814a60dbe320a41a0f4fa082815931fac986e93 (patch) | |
tree | ba6a9d1b7fe2a159c85b518ca0d7ea24823e0e46 | |
parent | 7f39e597726774cb3fee71f4b605a5499f7c3a8a (diff) |
drm/nvc0-/fb: hook up skeleton interrupt handler
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | 2 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c index e5fc37c4caac..45470e1f0385 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | |||
@@ -33,6 +33,21 @@ nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) | |||
33 | return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); | 33 | return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); |
34 | } | 34 | } |
35 | 35 | ||
36 | static void | ||
37 | nvc0_fb_intr(struct nouveau_subdev *subdev) | ||
38 | { | ||
39 | struct nvc0_fb_priv *priv = (void *)subdev; | ||
40 | u32 intr = nv_rd32(priv, 0x000100); | ||
41 | if (intr & 0x08000000) { | ||
42 | nv_debug(priv, "PFFB intr\n"); | ||
43 | intr &= ~0x08000000; | ||
44 | } | ||
45 | if (intr & 0x00002000) { | ||
46 | nv_debug(priv, "PBFB intr\n"); | ||
47 | intr &= ~0x00002000; | ||
48 | } | ||
49 | } | ||
50 | |||
36 | int | 51 | int |
37 | nvc0_fb_init(struct nouveau_object *object) | 52 | nvc0_fb_init(struct nouveau_object *object) |
38 | { | 53 | { |
@@ -86,6 +101,7 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
86 | return -EFAULT; | 101 | return -EFAULT; |
87 | } | 102 | } |
88 | 103 | ||
104 | nv_subdev(priv)->intr = nvc0_fb_intr; | ||
89 | return 0; | 105 | return 0; |
90 | } | 106 | } |
91 | 107 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c index c02b4763a2d5..34472d317097 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | |||
@@ -32,6 +32,7 @@ nvc0_mc_intr[] = { | |||
32 | { 0x00000080, NVDEV_ENGINE_COPY2 }, | 32 | { 0x00000080, NVDEV_ENGINE_COPY2 }, |
33 | { 0x00000100, NVDEV_ENGINE_FIFO }, | 33 | { 0x00000100, NVDEV_ENGINE_FIFO }, |
34 | { 0x00001000, NVDEV_ENGINE_GR }, | 34 | { 0x00001000, NVDEV_ENGINE_GR }, |
35 | { 0x00002000, NVDEV_SUBDEV_FB }, | ||
35 | { 0x00008000, NVDEV_ENGINE_BSP }, | 36 | { 0x00008000, NVDEV_ENGINE_BSP }, |
36 | { 0x00040000, NVDEV_SUBDEV_THERM }, | 37 | { 0x00040000, NVDEV_SUBDEV_THERM }, |
37 | { 0x00020000, NVDEV_ENGINE_VP }, | 38 | { 0x00020000, NVDEV_ENGINE_VP }, |
@@ -40,6 +41,7 @@ nvc0_mc_intr[] = { | |||
40 | { 0x01000000, NVDEV_SUBDEV_PWR }, | 41 | { 0x01000000, NVDEV_SUBDEV_PWR }, |
41 | { 0x02000000, NVDEV_SUBDEV_LTCG }, | 42 | { 0x02000000, NVDEV_SUBDEV_LTCG }, |
42 | { 0x04000000, NVDEV_ENGINE_DISP }, | 43 | { 0x04000000, NVDEV_ENGINE_DISP }, |
44 | { 0x08000000, NVDEV_SUBDEV_FB }, | ||
43 | { 0x10000000, NVDEV_SUBDEV_BUS }, | 45 | { 0x10000000, NVDEV_SUBDEV_BUS }, |
44 | { 0x40000000, NVDEV_SUBDEV_IBUS }, | 46 | { 0x40000000, NVDEV_SUBDEV_IBUS }, |
45 | { 0x80000000, NVDEV_ENGINE_SW }, | 47 | { 0x80000000, NVDEV_ENGINE_SW }, |