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authorBjorn Helgaas <bhelgaas@google.com>2019-05-13 19:34:48 -0400
committerBjorn Helgaas <bhelgaas@google.com>2019-05-13 19:34:48 -0400
commitc7a1c2bbb65e25551d585fba0fd36a01e0a22690 (patch)
tree19f3e31d93923be1256908ccf6921b5b9f43d60b
parentf8587c80c62a65c004ee838275351814b52c428c (diff)
parent0d6076184aecb97cc583bc7f9e125518d6c24404 (diff)
Merge branch 'pci/trivial'
- Cleanup PCI register definitions, typos, etc (Bjorn Helgaas) - Remove unnecessary use of user-space types in CPER (Bjorn Helgaas) - Cleanup setup-bus.c comments & whitespace (Nicholas Johnson) * pci/trivial: PCI: Cleanup setup-bus.c comments and whitespace CPER: Remove unnecessary use of user-space types CPER: Add UEFI spec references PCI: Fix comment typos PCI: Cleanup register definition width and whitespace # Conflicts: # drivers/pci/pci.c # drivers/pci/setup-bus.c
Diffstat
-rw-r--r--drivers/pci/controller/pci-host-generic.c2
-rw-r--r--drivers/pci/controller/pcie-iproc-msi.c2
-rw-r--r--drivers/pci/pci.c302
-rw-r--r--drivers/pci/setup-bus.c496
-rw-r--r--include/linux/cper.h336
-rw-r--r--include/uapi/linux/pci_regs.h132
6 files changed, 640 insertions, 630 deletions
diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c
index dea3ec7592a2..75a2fb930d4b 100644
--- a/drivers/pci/controller/pci-host-generic.c
+++ b/drivers/pci/controller/pci-host-generic.c
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Simple, generic PCI host controller driver targetting firmware-initialised 3 * Simple, generic PCI host controller driver targeting firmware-initialised
4 * systems and virtual machines (e.g. the PCI emulation provided by kvmtool). 4 * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
5 * 5 *
6 * Copyright (C) 2014 ARM Limited 6 * Copyright (C) 2014 ARM Limited
diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c
index cb3401a931f8..0a3f61be5625 100644
--- a/drivers/pci/controller/pcie-iproc-msi.c
+++ b/drivers/pci/controller/pcie-iproc-msi.c
@@ -367,7 +367,7 @@ static void iproc_msi_handler(struct irq_desc *desc)
367 367
368 /* 368 /*
369 * Now go read the tail pointer again to see if there are new 369 * Now go read the tail pointer again to see if there are new
370 * oustanding events that came in during the above window. 370 * outstanding events that came in during the above window.
371 */ 371 */
372 } while (true); 372 } while (true);
373 373
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6a670aae89f4..c52d8fd13a23 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -197,8 +197,8 @@ EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
197 197
198/** 198/**
199 * pci_dev_str_match_path - test if a path string matches a device 199 * pci_dev_str_match_path - test if a path string matches a device
200 * @dev: the PCI device to test 200 * @dev: the PCI device to test
201 * @path: string to match the device against 201 * @path: string to match the device against
202 * @endptr: pointer to the string after the match 202 * @endptr: pointer to the string after the match
203 * 203 *
204 * Test if a string (typically from a kernel parameter) formatted as a 204 * Test if a string (typically from a kernel parameter) formatted as a
@@ -280,8 +280,8 @@ free_and_exit:
280 280
281/** 281/**
282 * pci_dev_str_match - test if a string matches a device 282 * pci_dev_str_match - test if a string matches a device
283 * @dev: the PCI device to test 283 * @dev: the PCI device to test
284 * @p: string to match the device against 284 * @p: string to match the device against
285 * @endptr: pointer to the string after the match 285 * @endptr: pointer to the string after the match
286 * 286 *
287 * Test if a string (typically from a kernel parameter) matches a specified 287 * Test if a string (typically from a kernel parameter) matches a specified
@@ -341,7 +341,7 @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p,
341 } else { 341 } else {
342 /* 342 /*
343 * PCI Bus, Device, Function IDs are specified 343 * PCI Bus, Device, Function IDs are specified
344 * (optionally, may include a path of devfns following it) 344 * (optionally, may include a path of devfns following it)
345 */ 345 */
346 ret = pci_dev_str_match_path(dev, p, &p); 346 ret = pci_dev_str_match_path(dev, p, &p);
347 if (ret < 0) 347 if (ret < 0)
@@ -425,7 +425,7 @@ static int __pci_bus_find_cap_start(struct pci_bus *bus,
425 * Tell if a device supports a given PCI capability. 425 * Tell if a device supports a given PCI capability.
426 * Returns the address of the requested capability structure within the 426 * Returns the address of the requested capability structure within the
427 * device's PCI configuration space or 0 in case the device does not 427 * device's PCI configuration space or 0 in case the device does not
428 * support it. Possible values for @cap: 428 * support it. Possible values for @cap include:
429 * 429 *
430 * %PCI_CAP_ID_PM Power Management 430 * %PCI_CAP_ID_PM Power Management
431 * %PCI_CAP_ID_AGP Accelerated Graphics Port 431 * %PCI_CAP_ID_AGP Accelerated Graphics Port
@@ -450,11 +450,11 @@ EXPORT_SYMBOL(pci_find_capability);
450 450
451/** 451/**
452 * pci_bus_find_capability - query for devices' capabilities 452 * pci_bus_find_capability - query for devices' capabilities
453 * @bus: the PCI bus to query 453 * @bus: the PCI bus to query
454 * @devfn: PCI device to query 454 * @devfn: PCI device to query
455 * @cap: capability code 455 * @cap: capability code
456 * 456 *
457 * Like pci_find_capability() but works for pci devices that do not have a 457 * Like pci_find_capability() but works for PCI devices that do not have a
458 * pci_dev structure set up yet. 458 * pci_dev structure set up yet.
459 * 459 *
460 * Returns the address of the requested capability structure within the 460 * Returns the address of the requested capability structure within the
@@ -535,7 +535,7 @@ EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
535 * 535 *
536 * Returns the address of the requested extended capability structure 536 * Returns the address of the requested extended capability structure
537 * within the device's PCI configuration space or 0 if the device does 537 * within the device's PCI configuration space or 0 if the device does
538 * not support it. Possible values for @cap: 538 * not support it. Possible values for @cap include:
539 * 539 *
540 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 540 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
541 * %PCI_EXT_CAP_ID_VC Virtual Channel 541 * %PCI_EXT_CAP_ID_VC Virtual Channel
@@ -618,12 +618,13 @@ int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
618EXPORT_SYMBOL_GPL(pci_find_ht_capability); 618EXPORT_SYMBOL_GPL(pci_find_ht_capability);
619 619
620/** 620/**
621 * pci_find_parent_resource - return resource region of parent bus of given region 621 * pci_find_parent_resource - return resource region of parent bus of given
622 * region
622 * @dev: PCI device structure contains resources to be searched 623 * @dev: PCI device structure contains resources to be searched
623 * @res: child resource record for which parent is sought 624 * @res: child resource record for which parent is sought
624 * 625 *
625 * For given resource region of given device, return the resource 626 * For given resource region of given device, return the resource region of
626 * region of parent bus the given region is contained in. 627 * parent bus the given region is contained in.
627 */ 628 */
628struct resource *pci_find_parent_resource(const struct pci_dev *dev, 629struct resource *pci_find_parent_resource(const struct pci_dev *dev,
629 struct resource *res) 630 struct resource *res)
@@ -800,7 +801,7 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
800 801
801/** 802/**
802 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 803 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
803 * given PCI device 804 * given PCI device
804 * @dev: PCI device to handle. 805 * @dev: PCI device to handle.
805 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 806 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
806 * 807 *
@@ -826,7 +827,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
826 if (state < PCI_D0 || state > PCI_D3hot) 827 if (state < PCI_D0 || state > PCI_D3hot)
827 return -EINVAL; 828 return -EINVAL;
828 829
829 /* Validate current state: 830 /*
831 * Validate current state:
830 * Can enter D0 from any state, but if we can only go deeper 832 * Can enter D0 from any state, but if we can only go deeper
831 * to sleep if we're already in a low power state 833 * to sleep if we're already in a low power state
832 */ 834 */
@@ -837,14 +839,15 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
837 return -EINVAL; 839 return -EINVAL;
838 } 840 }
839 841
840 /* check if this device supports the desired state */ 842 /* Check if this device supports the desired state */
841 if ((state == PCI_D1 && !dev->d1_support) 843 if ((state == PCI_D1 && !dev->d1_support)
842 || (state == PCI_D2 && !dev->d2_support)) 844 || (state == PCI_D2 && !dev->d2_support))
843 return -EIO; 845 return -EIO;
844 846
845 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 847 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
846 848
847 /* If we're (effectively) in D3, force entire word to 0. 849 /*
850 * If we're (effectively) in D3, force entire word to 0.
848 * This doesn't affect PME_Status, disables PME_En, and 851 * This doesn't affect PME_Status, disables PME_En, and
849 * sets PowerState to 0. 852 * sets PowerState to 0.
850 */ 853 */
@@ -867,11 +870,13 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
867 break; 870 break;
868 } 871 }
869 872
870 /* enter specified state */ 873 /* Enter specified state */
871 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 874 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
872 875
873 /* Mandatory power management transition delays */ 876 /*
874 /* see PCI PM 1.1 5.6.1 table 18 */ 877 * Mandatory power management transition delays; see PCI PM 1.1
878 * 5.6.1 table 18
879 */
875 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 880 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
876 pci_dev_d3_sleep(dev); 881 pci_dev_d3_sleep(dev);
877 else if (state == PCI_D2 || dev->current_state == PCI_D2) 882 else if (state == PCI_D2 || dev->current_state == PCI_D2)
@@ -1085,16 +1090,18 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1085{ 1090{
1086 int error; 1091 int error;
1087 1092
1088 /* bound the state we're entering */ 1093 /* Bound the state we're entering */
1089 if (state > PCI_D3cold) 1094 if (state > PCI_D3cold)
1090 state = PCI_D3cold; 1095 state = PCI_D3cold;
1091 else if (state < PCI_D0) 1096 else if (state < PCI_D0)
1092 state = PCI_D0; 1097 state = PCI_D0;
1093 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 1098 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1099
1094 /* 1100 /*
1095 * If the device or the parent bridge do not support PCI PM, 1101 * If the device or the parent bridge do not support PCI
1096 * ignore the request if we're doing anything other than putting 1102 * PM, ignore the request if we're doing anything other
1097 * it into D0 (which would only happen on boot). 1103 * than putting it into D0 (which would only happen on
1104 * boot).
1098 */ 1105 */
1099 return 0; 1106 return 0;
1100 1107
@@ -1104,8 +1111,10 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1104 1111
1105 __pci_start_power_transition(dev, state); 1112 __pci_start_power_transition(dev, state);
1106 1113
1107 /* This device is quirked not to be put into D3, so 1114 /*
1108 don't put it in D3 */ 1115 * This device is quirked not to be put into D3, so don't put it in
1116 * D3
1117 */
1109 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 1118 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1110 return 0; 1119 return 0;
1111 1120
@@ -1127,12 +1136,11 @@ EXPORT_SYMBOL(pci_set_power_state);
1127 * pci_choose_state - Choose the power state of a PCI device 1136 * pci_choose_state - Choose the power state of a PCI device
1128 * @dev: PCI device to be suspended 1137 * @dev: PCI device to be suspended
1129 * @state: target sleep state for the whole system. This is the value 1138 * @state: target sleep state for the whole system. This is the value
1130 * that is passed to suspend() function. 1139 * that is passed to suspend() function.
1131 * 1140 *
1132 * Returns PCI power state suitable for given device and given system 1141 * Returns PCI power state suitable for given device and given system
1133 * message. 1142 * message.
1134 */ 1143 */
1135
1136pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 1144pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1137{ 1145{
1138 pci_power_t ret; 1146 pci_power_t ret;
@@ -1310,8 +1318,9 @@ static void pci_restore_ltr_state(struct pci_dev *dev)
1310} 1318}
1311 1319
1312/** 1320/**
1313 * pci_save_state - save the PCI configuration space of a device before suspending 1321 * pci_save_state - save the PCI configuration space of a device before
1314 * @dev: - PCI device that we're dealing with 1322 * suspending
1323 * @dev: PCI device that we're dealing with
1315 */ 1324 */
1316int pci_save_state(struct pci_dev *dev) 1325int pci_save_state(struct pci_dev *dev)
1317{ 1326{
@@ -1422,7 +1431,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
1422 1431
1423/** 1432/**
1424 * pci_restore_state - Restore the saved state of a PCI device 1433 * pci_restore_state - Restore the saved state of a PCI device
1425 * @dev: - PCI device that we're dealing with 1434 * @dev: PCI device that we're dealing with
1426 */ 1435 */
1427void pci_restore_state(struct pci_dev *dev) 1436void pci_restore_state(struct pci_dev *dev)
1428{ 1437{
@@ -1599,8 +1608,8 @@ static int do_pci_enable_device(struct pci_dev *dev, int bars)
1599 * pci_reenable_device - Resume abandoned device 1608 * pci_reenable_device - Resume abandoned device
1600 * @dev: PCI device to be resumed 1609 * @dev: PCI device to be resumed
1601 * 1610 *
1602 * Note this function is a backend of pci_default_resume and is not supposed 1611 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1603 * to be called by normal code, write proper resume handler and use it instead. 1612 * to be called by normal code, write proper resume handler and use it instead.
1604 */ 1613 */
1605int pci_reenable_device(struct pci_dev *dev) 1614int pci_reenable_device(struct pci_dev *dev)
1606{ 1615{
@@ -1675,9 +1684,9 @@ static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1675 * pci_enable_device_io - Initialize a device for use with IO space 1684 * pci_enable_device_io - Initialize a device for use with IO space
1676 * @dev: PCI device to be initialized 1685 * @dev: PCI device to be initialized
1677 * 1686 *
1678 * Initialize device before it's used by a driver. Ask low-level code 1687 * Initialize device before it's used by a driver. Ask low-level code
1679 * to enable I/O resources. Wake up the device if it was suspended. 1688 * to enable I/O resources. Wake up the device if it was suspended.
1680 * Beware, this function can fail. 1689 * Beware, this function can fail.
1681 */ 1690 */
1682int pci_enable_device_io(struct pci_dev *dev) 1691int pci_enable_device_io(struct pci_dev *dev)
1683{ 1692{
@@ -1689,9 +1698,9 @@ EXPORT_SYMBOL(pci_enable_device_io);
1689 * pci_enable_device_mem - Initialize a device for use with Memory space 1698 * pci_enable_device_mem - Initialize a device for use with Memory space
1690 * @dev: PCI device to be initialized 1699 * @dev: PCI device to be initialized
1691 * 1700 *
1692 * Initialize device before it's used by a driver. Ask low-level code 1701 * Initialize device before it's used by a driver. Ask low-level code
1693 * to enable Memory resources. Wake up the device if it was suspended. 1702 * to enable Memory resources. Wake up the device if it was suspended.
1694 * Beware, this function can fail. 1703 * Beware, this function can fail.
1695 */ 1704 */
1696int pci_enable_device_mem(struct pci_dev *dev) 1705int pci_enable_device_mem(struct pci_dev *dev)
1697{ 1706{
@@ -1703,12 +1712,12 @@ EXPORT_SYMBOL(pci_enable_device_mem);
1703 * pci_enable_device - Initialize device before it's used by a driver. 1712 * pci_enable_device - Initialize device before it's used by a driver.
1704 * @dev: PCI device to be initialized 1713 * @dev: PCI device to be initialized
1705 * 1714 *
1706 * Initialize device before it's used by a driver. Ask low-level code 1715 * Initialize device before it's used by a driver. Ask low-level code
1707 * to enable I/O and memory. Wake up the device if it was suspended. 1716 * to enable I/O and memory. Wake up the device if it was suspended.
1708 * Beware, this function can fail. 1717 * Beware, this function can fail.
1709 * 1718 *
1710 * Note we don't actually enable the device many times if we call 1719 * Note we don't actually enable the device many times if we call
1711 * this function repeatedly (we just increment the count). 1720 * this function repeatedly (we just increment the count).
1712 */ 1721 */
1713int pci_enable_device(struct pci_dev *dev) 1722int pci_enable_device(struct pci_dev *dev)
1714{ 1723{
@@ -1717,8 +1726,8 @@ int pci_enable_device(struct pci_dev *dev)
1717EXPORT_SYMBOL(pci_enable_device); 1726EXPORT_SYMBOL(pci_enable_device);
1718 1727
1719/* 1728/*
1720 * Managed PCI resources. This manages device on/off, intx/msi/msix 1729 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1721 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1730 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1722 * there's no need to track it separately. pci_devres is initialized 1731 * there's no need to track it separately. pci_devres is initialized
1723 * when a device is enabled using managed PCI device enable interface. 1732 * when a device is enabled using managed PCI device enable interface.
1724 */ 1733 */
@@ -1836,7 +1845,8 @@ int __weak pcibios_add_device(struct pci_dev *dev)
1836} 1845}
1837 1846
1838/** 1847/**
1839 * pcibios_release_device - provide arch specific hooks when releasing device dev 1848 * pcibios_release_device - provide arch specific hooks when releasing
1849 * device dev
1840 * @dev: the PCI device being released 1850 * @dev: the PCI device being released
1841 * 1851 *
1842 * Permits the platform to provide architecture specific functionality when 1852 * Permits the platform to provide architecture specific functionality when
@@ -1927,8 +1937,7 @@ EXPORT_SYMBOL(pci_disable_device);
1927 * @dev: the PCIe device reset 1937 * @dev: the PCIe device reset
1928 * @state: Reset state to enter into 1938 * @state: Reset state to enter into
1929 * 1939 *
1930 * 1940 * Set the PCIe reset state for the device. This is the default
1931 * Sets the PCIe reset state for the device. This is the default
1932 * implementation. Architecture implementations can override this. 1941 * implementation. Architecture implementations can override this.
1933 */ 1942 */
1934int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1943int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
@@ -1942,7 +1951,6 @@ int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1942 * @dev: the PCIe device reset 1951 * @dev: the PCIe device reset
1943 * @state: Reset state to enter into 1952 * @state: Reset state to enter into
1944 * 1953 *
1945 *
1946 * Sets the PCI reset state for the device. 1954 * Sets the PCI reset state for the device.
1947 */ 1955 */
1948int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1956int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
@@ -2339,7 +2347,8 @@ static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2339} 2347}
2340 2348
2341/** 2349/**
2342 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 2350 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2351 * into a sleep state
2343 * @dev: Device to handle. 2352 * @dev: Device to handle.
2344 * 2353 *
2345 * Choose the power state appropriate for the device depending on whether 2354 * Choose the power state appropriate for the device depending on whether
@@ -2367,7 +2376,8 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
2367EXPORT_SYMBOL(pci_prepare_to_sleep); 2376EXPORT_SYMBOL(pci_prepare_to_sleep);
2368 2377
2369/** 2378/**
2370 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 2379 * pci_back_from_sleep - turn PCI device on during system-wide transition
2380 * into working state
2371 * @dev: Device to handle. 2381 * @dev: Device to handle.
2372 * 2382 *
2373 * Disable device's system wake-up capability and put it into D0. 2383 * Disable device's system wake-up capability and put it into D0.
@@ -3005,7 +3015,7 @@ static void pci_add_saved_cap(struct pci_dev *pci_dev,
3005 3015
3006/** 3016/**
3007 * _pci_add_cap_save_buffer - allocate buffer for saving given 3017 * _pci_add_cap_save_buffer - allocate buffer for saving given
3008 * capability registers 3018 * capability registers
3009 * @dev: the PCI device 3019 * @dev: the PCI device
3010 * @cap: the capability to allocate the buffer for 3020 * @cap: the capability to allocate the buffer for
3011 * @extended: Standard or Extended capability ID 3021 * @extended: Standard or Extended capability ID
@@ -3186,7 +3196,7 @@ static void pci_disable_acs_redir(struct pci_dev *dev)
3186} 3196}
3187 3197
3188/** 3198/**
3189 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites 3199 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
3190 * @dev: the PCI device 3200 * @dev: the PCI device
3191 */ 3201 */
3192static void pci_std_enable_acs(struct pci_dev *dev) 3202static void pci_std_enable_acs(struct pci_dev *dev)
@@ -3609,13 +3619,14 @@ u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3609EXPORT_SYMBOL_GPL(pci_common_swizzle); 3619EXPORT_SYMBOL_GPL(pci_common_swizzle);
3610 3620
3611/** 3621/**
3612 * pci_release_region - Release a PCI bar 3622 * pci_release_region - Release a PCI bar
3613 * @pdev: PCI device whose resources were previously reserved by pci_request_region 3623 * @pdev: PCI device whose resources were previously reserved by
3614 * @bar: BAR to release 3624 * pci_request_region()
3625 * @bar: BAR to release
3615 * 3626 *
3616 * Releases the PCI I/O and memory resources previously reserved by a 3627 * Releases the PCI I/O and memory resources previously reserved by a
3617 * successful call to pci_request_region. Call this function only 3628 * successful call to pci_request_region(). Call this function only
3618 * after all use of the PCI regions has ceased. 3629 * after all use of the PCI regions has ceased.
3619 */ 3630 */
3620void pci_release_region(struct pci_dev *pdev, int bar) 3631void pci_release_region(struct pci_dev *pdev, int bar)
3621{ 3632{
@@ -3637,23 +3648,23 @@ void pci_release_region(struct pci_dev *pdev, int bar)
3637EXPORT_SYMBOL(pci_release_region); 3648EXPORT_SYMBOL(pci_release_region);
3638 3649
3639/** 3650/**
3640 * __pci_request_region - Reserved PCI I/O and memory resource 3651 * __pci_request_region - Reserved PCI I/O and memory resource
3641 * @pdev: PCI device whose resources are to be reserved 3652 * @pdev: PCI device whose resources are to be reserved
3642 * @bar: BAR to be reserved 3653 * @bar: BAR to be reserved
3643 * @res_name: Name to be associated with resource. 3654 * @res_name: Name to be associated with resource.
3644 * @exclusive: whether the region access is exclusive or not 3655 * @exclusive: whether the region access is exclusive or not
3645 * 3656 *
3646 * Mark the PCI region associated with PCI device @pdev BR @bar as 3657 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3647 * being reserved by owner @res_name. Do not access any 3658 * being reserved by owner @res_name. Do not access any
3648 * address inside the PCI regions unless this call returns 3659 * address inside the PCI regions unless this call returns
3649 * successfully. 3660 * successfully.
3650 * 3661 *
3651 * If @exclusive is set, then the region is marked so that userspace 3662 * If @exclusive is set, then the region is marked so that userspace
3652 * is explicitly not allowed to map the resource via /dev/mem or 3663 * is explicitly not allowed to map the resource via /dev/mem or
3653 * sysfs MMIO access. 3664 * sysfs MMIO access.
3654 * 3665 *
3655 * Returns 0 on success, or %EBUSY on error. A warning 3666 * Returns 0 on success, or %EBUSY on error. A warning
3656 * message is also printed on failure. 3667 * message is also printed on failure.
3657 */ 3668 */
3658static int __pci_request_region(struct pci_dev *pdev, int bar, 3669static int __pci_request_region(struct pci_dev *pdev, int bar,
3659 const char *res_name, int exclusive) 3670 const char *res_name, int exclusive)
@@ -3687,18 +3698,18 @@ err_out:
3687} 3698}
3688 3699
3689/** 3700/**
3690 * pci_request_region - Reserve PCI I/O and memory resource 3701 * pci_request_region - Reserve PCI I/O and memory resource
3691 * @pdev: PCI device whose resources are to be reserved 3702 * @pdev: PCI device whose resources are to be reserved
3692 * @bar: BAR to be reserved 3703 * @bar: BAR to be reserved
3693 * @res_name: Name to be associated with resource 3704 * @res_name: Name to be associated with resource
3694 * 3705 *
3695 * Mark the PCI region associated with PCI device @pdev BAR @bar as 3706 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3696 * being reserved by owner @res_name. Do not access any 3707 * being reserved by owner @res_name. Do not access any
3697 * address inside the PCI regions unless this call returns 3708 * address inside the PCI regions unless this call returns
3698 * successfully. 3709 * successfully.
3699 * 3710 *
3700 * Returns 0 on success, or %EBUSY on error. A warning 3711 * Returns 0 on success, or %EBUSY on error. A warning
3701 * message is also printed on failure. 3712 * message is also printed on failure.
3702 */ 3713 */
3703int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 3714int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3704{ 3715{
@@ -3766,12 +3777,13 @@ int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3766EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 3777EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3767 3778
3768/** 3779/**
3769 * pci_release_regions - Release reserved PCI I/O and memory resources 3780 * pci_release_regions - Release reserved PCI I/O and memory resources
3770 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 3781 * @pdev: PCI device whose resources were previously reserved by
3782 * pci_request_regions()
3771 * 3783 *
3772 * Releases all PCI I/O and memory resources previously reserved by a 3784 * Releases all PCI I/O and memory resources previously reserved by a
3773 * successful call to pci_request_regions. Call this function only 3785 * successful call to pci_request_regions(). Call this function only
3774 * after all use of the PCI regions has ceased. 3786 * after all use of the PCI regions has ceased.
3775 */ 3787 */
3776 3788
3777void pci_release_regions(struct pci_dev *pdev) 3789void pci_release_regions(struct pci_dev *pdev)
@@ -3781,17 +3793,17 @@ void pci_release_regions(struct pci_dev *pdev)
3781EXPORT_SYMBOL(pci_release_regions); 3793EXPORT_SYMBOL(pci_release_regions);
3782 3794
3783/** 3795/**
3784 * pci_request_regions - Reserved PCI I/O and memory resources 3796 * pci_request_regions - Reserve PCI I/O and memory resources
3785 * @pdev: PCI device whose resources are to be reserved 3797 * @pdev: PCI device whose resources are to be reserved
3786 * @res_name: Name to be associated with resource. 3798 * @res_name: Name to be associated with resource.
3787 * 3799 *
3788 * Mark all PCI regions associated with PCI device @pdev as 3800 * Mark all PCI regions associated with PCI device @pdev as
3789 * being reserved by owner @res_name. Do not access any 3801 * being reserved by owner @res_name. Do not access any
3790 * address inside the PCI regions unless this call returns 3802 * address inside the PCI regions unless this call returns
3791 * successfully. 3803 * successfully.
3792 * 3804 *
3793 * Returns 0 on success, or %EBUSY on error. A warning 3805 * Returns 0 on success, or %EBUSY on error. A warning
3794 * message is also printed on failure. 3806 * message is also printed on failure.
3795 */ 3807 */
3796int pci_request_regions(struct pci_dev *pdev, const char *res_name) 3808int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3797{ 3809{
@@ -3800,20 +3812,19 @@ int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3800EXPORT_SYMBOL(pci_request_regions); 3812EXPORT_SYMBOL(pci_request_regions);
3801 3813
3802/** 3814/**
3803 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 3815 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3804 * @pdev: PCI device whose resources are to be reserved 3816 * @pdev: PCI device whose resources are to be reserved
3805 * @res_name: Name to be associated with resource. 3817 * @res_name: Name to be associated with resource.
3806 * 3818 *
3807 * Mark all PCI regions associated with PCI device @pdev as 3819 * Mark all PCI regions associated with PCI device @pdev as being reserved
3808 * being reserved by owner @res_name. Do not access any 3820 * by owner @res_name. Do not access any address inside the PCI regions
3809 * address inside the PCI regions unless this call returns 3821 * unless this call returns successfully.
3810 * successfully.
3811 * 3822 *
3812 * pci_request_regions_exclusive() will mark the region so that 3823 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3813 * /dev/mem and the sysfs MMIO access will not be allowed. 3824 * and the sysfs MMIO access will not be allowed.
3814 * 3825 *
3815 * Returns 0 on success, or %EBUSY on error. A warning 3826 * Returns 0 on success, or %EBUSY on error. A warning message is also
3816 * message is also printed on failure. 3827 * printed on failure.
3817 */ 3828 */
3818int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 3829int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3819{ 3830{
@@ -3824,7 +3835,7 @@ EXPORT_SYMBOL(pci_request_regions_exclusive);
3824 3835
3825/* 3836/*
3826 * Record the PCI IO range (expressed as CPU physical address + size). 3837 * Record the PCI IO range (expressed as CPU physical address + size).
3827 * Return a negative value if an error has occured, zero otherwise 3838 * Return a negative value if an error has occurred, zero otherwise
3828 */ 3839 */
3829int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 3840int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3830 resource_size_t size) 3841 resource_size_t size)
@@ -3880,14 +3891,14 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address)
3880} 3891}
3881 3892
3882/** 3893/**
3883 * pci_remap_iospace - Remap the memory mapped I/O space 3894 * pci_remap_iospace - Remap the memory mapped I/O space
3884 * @res: Resource describing the I/O space 3895 * @res: Resource describing the I/O space
3885 * @phys_addr: physical address of range to be mapped 3896 * @phys_addr: physical address of range to be mapped
3886 * 3897 *
3887 * Remap the memory mapped I/O space described by the @res 3898 * Remap the memory mapped I/O space described by the @res and the CPU
3888 * and the CPU physical address @phys_addr into virtual address space. 3899 * physical address @phys_addr into virtual address space. Only
3889 * Only architectures that have memory mapped IO functions defined 3900 * architectures that have memory mapped IO functions defined (and the
3890 * (and the PCI_IOBASE value defined) should call this function. 3901 * PCI_IOBASE value defined) should call this function.
3891 */ 3902 */
3892int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) 3903int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3893{ 3904{
@@ -3903,8 +3914,10 @@ int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3903 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, 3914 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3904 pgprot_device(PAGE_KERNEL)); 3915 pgprot_device(PAGE_KERNEL));
3905#else 3916#else
3906 /* this architecture does not have memory mapped I/O space, 3917 /*
3907 so this function should never be called */ 3918 * This architecture does not have memory mapped I/O space,
3919 * so this function should never be called
3920 */
3908 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); 3921 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3909 return -ENODEV; 3922 return -ENODEV;
3910#endif 3923#endif
@@ -3912,12 +3925,12 @@ int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3912EXPORT_SYMBOL(pci_remap_iospace); 3925EXPORT_SYMBOL(pci_remap_iospace);
3913 3926
3914/** 3927/**
3915 * pci_unmap_iospace - Unmap the memory mapped I/O space 3928 * pci_unmap_iospace - Unmap the memory mapped I/O space
3916 * @res: resource to be unmapped 3929 * @res: resource to be unmapped
3917 * 3930 *
3918 * Unmap the CPU virtual address @res from virtual address space. 3931 * Unmap the CPU virtual address @res from virtual address space. Only
3919 * Only architectures that have memory mapped IO functions defined 3932 * architectures that have memory mapped IO functions defined (and the
3920 * (and the PCI_IOBASE value defined) should call this function. 3933 * PCI_IOBASE value defined) should call this function.
3921 */ 3934 */
3922void pci_unmap_iospace(struct resource *res) 3935void pci_unmap_iospace(struct resource *res)
3923{ 3936{
@@ -4263,7 +4276,7 @@ EXPORT_SYMBOL(pci_clear_mwi);
4263 * @pdev: the PCI device to operate on 4276 * @pdev: the PCI device to operate on
4264 * @enable: boolean: whether to enable or disable PCI INTx 4277 * @enable: boolean: whether to enable or disable PCI INTx
4265 * 4278 *
4266 * Enables/disables PCI INTx for device dev 4279 * Enables/disables PCI INTx for device @pdev
4267 */ 4280 */
4268void pci_intx(struct pci_dev *pdev, int enable) 4281void pci_intx(struct pci_dev *pdev, int enable)
4269{ 4282{
@@ -4339,9 +4352,8 @@ done:
4339 * pci_check_and_mask_intx - mask INTx on pending interrupt 4352 * pci_check_and_mask_intx - mask INTx on pending interrupt
4340 * @dev: the PCI device to operate on 4353 * @dev: the PCI device to operate on
4341 * 4354 *
4342 * Check if the device dev has its INTx line asserted, mask it and 4355 * Check if the device dev has its INTx line asserted, mask it and return
4343 * return true in that case. False is returned if no interrupt was 4356 * true in that case. False is returned if no interrupt was pending.
4344 * pending.
4345 */ 4357 */
4346bool pci_check_and_mask_intx(struct pci_dev *dev) 4358bool pci_check_and_mask_intx(struct pci_dev *dev)
4347{ 4359{
@@ -4353,9 +4365,9 @@ EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4353 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending 4365 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4354 * @dev: the PCI device to operate on 4366 * @dev: the PCI device to operate on
4355 * 4367 *
4356 * Check if the device dev has its INTx line asserted, unmask it if not 4368 * Check if the device dev has its INTx line asserted, unmask it if not and
4357 * and return true. False is returned and the mask remains active if 4369 * return true. False is returned and the mask remains active if there was
4358 * there was still an interrupt pending. 4370 * still an interrupt pending.
4359 */ 4371 */
4360bool pci_check_and_unmask_intx(struct pci_dev *dev) 4372bool pci_check_and_unmask_intx(struct pci_dev *dev)
4361{ 4373{
@@ -4364,7 +4376,7 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev)
4364EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 4376EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4365 4377
4366/** 4378/**
4367 * pci_wait_for_pending_transaction - waits for pending transaction 4379 * pci_wait_for_pending_transaction - wait for pending transaction
4368 * @dev: the PCI device to operate on 4380 * @dev: the PCI device to operate on
4369 * 4381 *
4370 * Return 0 if transaction is pending 1 otherwise. 4382 * Return 0 if transaction is pending 1 otherwise.
@@ -4422,7 +4434,7 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4422 4434
4423/** 4435/**
4424 * pcie_has_flr - check if a device supports function level resets 4436 * pcie_has_flr - check if a device supports function level resets
4425 * @dev: device to check 4437 * @dev: device to check
4426 * 4438 *
4427 * Returns true if the device advertises support for PCIe function level 4439 * Returns true if the device advertises support for PCIe function level
4428 * resets. 4440 * resets.
@@ -4441,7 +4453,7 @@ EXPORT_SYMBOL_GPL(pcie_has_flr);
4441 4453
4442/** 4454/**
4443 * pcie_flr - initiate a PCIe function level reset 4455 * pcie_flr - initiate a PCIe function level reset
4444 * @dev: device to reset 4456 * @dev: device to reset
4445 * 4457 *
4446 * Initiate a function level reset on @dev. The caller should ensure the 4458 * Initiate a function level reset on @dev. The caller should ensure the
4447 * device supports FLR before calling this function, e.g. by using the 4459 * device supports FLR before calling this function, e.g. by using the
@@ -4785,6 +4797,7 @@ static void pci_dev_restore(struct pci_dev *dev)
4785 * 4797 *
4786 * The device function is presumed to be unused and the caller is holding 4798 * The device function is presumed to be unused and the caller is holding
4787 * the device mutex lock when this function is called. 4799 * the device mutex lock when this function is called.
4800 *
4788 * Resetting the device will make the contents of PCI configuration space 4801 * Resetting the device will make the contents of PCI configuration space
4789 * random, so any caller of this must be prepared to reinitialise the 4802 * random, so any caller of this must be prepared to reinitialise the
4790 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 4803 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
@@ -5348,8 +5361,8 @@ EXPORT_SYMBOL_GPL(pci_reset_bus);
5348 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 5361 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5349 * @dev: PCI device to query 5362 * @dev: PCI device to query
5350 * 5363 *
5351 * Returns mmrbc: maximum designed memory read count in bytes 5364 * Returns mmrbc: maximum designed memory read count in bytes or
5352 * or appropriate error value. 5365 * appropriate error value.
5353 */ 5366 */
5354int pcix_get_max_mmrbc(struct pci_dev *dev) 5367int pcix_get_max_mmrbc(struct pci_dev *dev)
5355{ 5368{
@@ -5371,8 +5384,8 @@ EXPORT_SYMBOL(pcix_get_max_mmrbc);
5371 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 5384 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5372 * @dev: PCI device to query 5385 * @dev: PCI device to query
5373 * 5386 *
5374 * Returns mmrbc: maximum memory read count in bytes 5387 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5375 * or appropriate error value. 5388 * value.
5376 */ 5389 */
5377int pcix_get_mmrbc(struct pci_dev *dev) 5390int pcix_get_mmrbc(struct pci_dev *dev)
5378{ 5391{
@@ -5396,7 +5409,7 @@ EXPORT_SYMBOL(pcix_get_mmrbc);
5396 * @mmrbc: maximum memory read count in bytes 5409 * @mmrbc: maximum memory read count in bytes
5397 * valid values are 512, 1024, 2048, 4096 5410 * valid values are 512, 1024, 2048, 4096
5398 * 5411 *
5399 * If possible sets maximum memory read byte count, some bridges have erratas 5412 * If possible sets maximum memory read byte count, some bridges have errata
5400 * that prevent this. 5413 * that prevent this.
5401 */ 5414 */
5402int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 5415int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
@@ -5441,8 +5454,7 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
5441 * pcie_get_readrq - get PCI Express read request size 5454 * pcie_get_readrq - get PCI Express read request size
5442 * @dev: PCI device to query 5455 * @dev: PCI device to query
5443 * 5456 *
5444 * Returns maximum memory read request in bytes 5457 * Returns maximum memory read request in bytes or appropriate error value.
5445 * or appropriate error value.
5446 */ 5458 */
5447int pcie_get_readrq(struct pci_dev *dev) 5459int pcie_get_readrq(struct pci_dev *dev)
5448{ 5460{
@@ -5470,10 +5482,9 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
5470 return -EINVAL; 5482 return -EINVAL;
5471 5483
5472 /* 5484 /*
5473 * If using the "performance" PCIe config, we clamp the 5485 * If using the "performance" PCIe config, we clamp the read rq
5474 * read rq size to the max packet size to prevent the 5486 * size to the max packet size to keep the host bridge from
5475 * host bridge generating requests larger than we can 5487 * generating requests larger than we can cope with.
5476 * cope with
5477 */ 5488 */
5478 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 5489 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5479 int mps = pcie_get_mps(dev); 5490 int mps = pcie_get_mps(dev);
@@ -6119,6 +6130,7 @@ static int of_pci_bus_find_domain_nr(struct device *parent)
6119 6130
6120 if (parent) 6131 if (parent)
6121 domain = of_get_pci_domain_nr(parent->of_node); 6132 domain = of_get_pci_domain_nr(parent->of_node);
6133
6122 /* 6134 /*
6123 * Check DT domain and use_dt_domains values. 6135 * Check DT domain and use_dt_domains values.
6124 * 6136 *
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index c73e66725d05..0cdd5ff389de 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -49,17 +49,15 @@ static void free_list(struct list_head *head)
49} 49}
50 50
51/** 51/**
52 * add_to_list() - add a new resource tracker to the list 52 * add_to_list() - Add a new resource tracker to the list
53 * @head: Head of the list 53 * @head: Head of the list
54 * @dev: device corresponding to which the resource 54 * @dev: Device to which the resource belongs
55 * belongs 55 * @res: Resource to be tracked
56 * @res: The resource to be tracked 56 * @add_size: Additional size to be optionally added to the resource
57 * @add_size: additional size to be optionally added
58 * to the resource
59 */ 57 */
60static int add_to_list(struct list_head *head, 58static int add_to_list(struct list_head *head, struct pci_dev *dev,
61 struct pci_dev *dev, struct resource *res, 59 struct resource *res, resource_size_t add_size,
62 resource_size_t add_size, resource_size_t min_align) 60 resource_size_t min_align)
63{ 61{
64 struct pci_dev_resource *tmp; 62 struct pci_dev_resource *tmp;
65 63
@@ -80,8 +78,7 @@ static int add_to_list(struct list_head *head,
80 return 0; 78 return 0;
81} 79}
82 80
83static void remove_from_list(struct list_head *head, 81static void remove_from_list(struct list_head *head, struct resource *res)
84 struct resource *res)
85{ 82{
86 struct pci_dev_resource *dev_res, *tmp; 83 struct pci_dev_resource *dev_res, *tmp;
87 84
@@ -158,7 +155,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
158 tmp->res = r; 155 tmp->res = r;
159 tmp->dev = dev; 156 tmp->dev = dev;
160 157
161 /* fallback is smallest one or list is empty*/ 158 /* Fallback is smallest one or list is empty */
162 n = head; 159 n = head;
163 list_for_each_entry(dev_res, head, list) { 160 list_for_each_entry(dev_res, head, list) {
164 resource_size_t align; 161 resource_size_t align;
@@ -171,21 +168,20 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
171 break; 168 break;
172 } 169 }
173 } 170 }
174 /* Insert it just before n*/ 171 /* Insert it just before n */
175 list_add_tail(&tmp->list, n); 172 list_add_tail(&tmp->list, n);
176 } 173 }
177} 174}
178 175
179static void __dev_sort_resources(struct pci_dev *dev, 176static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
180 struct list_head *head)
181{ 177{
182 u16 class = dev->class >> 8; 178 u16 class = dev->class >> 8;
183 179
184 /* Don't touch classless devices or host bridges or ioapics. */ 180 /* Don't touch classless devices or host bridges or IOAPICs */
185 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) 181 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
186 return; 182 return;
187 183
188 /* Don't touch ioapic devices already enabled by firmware */ 184 /* Don't touch IOAPIC devices already enabled by firmware */
189 if (class == PCI_CLASS_SYSTEM_PIC) { 185 if (class == PCI_CLASS_SYSTEM_PIC) {
190 u16 command; 186 u16 command;
191 pci_read_config_word(dev, PCI_COMMAND, &command); 187 pci_read_config_word(dev, PCI_COMMAND, &command);
@@ -204,19 +200,18 @@ static inline void reset_resource(struct resource *res)
204} 200}
205 201
206/** 202/**
207 * reassign_resources_sorted() - satisfy any additional resource requests 203 * reassign_resources_sorted() - Satisfy any additional resource requests
208 * 204 *
209 * @realloc_head : head of the list tracking requests requiring additional 205 * @realloc_head: Head of the list tracking requests requiring
210 * resources 206 * additional resources
211 * @head : head of the list tracking requests with allocated 207 * @head: Head of the list tracking requests with allocated
212 * resources 208 * resources
213 * 209 *
214 * Walk through each element of the realloc_head and try to procure 210 * Walk through each element of the realloc_head and try to procure additional
215 * additional resources for the element, provided the element 211 * resources for the element, provided the element is in the head list.
216 * is in the head list.
217 */ 212 */
218static void reassign_resources_sorted(struct list_head *realloc_head, 213static void reassign_resources_sorted(struct list_head *realloc_head,
219 struct list_head *head) 214 struct list_head *head)
220{ 215{
221 struct resource *res; 216 struct resource *res;
222 struct pci_dev_resource *add_res, *tmp; 217 struct pci_dev_resource *add_res, *tmp;
@@ -228,18 +223,18 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
228 bool found_match = false; 223 bool found_match = false;
229 224
230 res = add_res->res; 225 res = add_res->res;
231 /* skip resource that has been reset */ 226 /* Skip resource that has been reset */
232 if (!res->flags) 227 if (!res->flags)
233 goto out; 228 goto out;
234 229
235 /* skip this resource if not found in head list */ 230 /* Skip this resource if not found in head list */
236 list_for_each_entry(dev_res, head, list) { 231 list_for_each_entry(dev_res, head, list) {
237 if (dev_res->res == res) { 232 if (dev_res->res == res) {
238 found_match = true; 233 found_match = true;
239 break; 234 break;
240 } 235 }
241 } 236 }
242 if (!found_match)/* just skip */ 237 if (!found_match) /* Just skip */
243 continue; 238 continue;
244 239
245 idx = res - &add_res->dev->resource[0]; 240 idx = res - &add_res->dev->resource[0];
@@ -266,14 +261,14 @@ out:
266} 261}
267 262
268/** 263/**
269 * assign_requested_resources_sorted() - satisfy resource requests 264 * assign_requested_resources_sorted() - Satisfy resource requests
270 * 265 *
271 * @head : head of the list tracking requests for resources 266 * @head: Head of the list tracking requests for resources
272 * @fail_head : head of the list tracking requests that could 267 * @fail_head: Head of the list tracking requests that could not be
273 * not be allocated 268 * allocated
274 * 269 *
275 * Satisfy resource requests of each element in the list. Add 270 * Satisfy resource requests of each element in the list. Add requests that
276 * requests that could not satisfied to the failed_list. 271 * could not be satisfied to the failed_list.
277 */ 272 */
278static void assign_requested_resources_sorted(struct list_head *head, 273static void assign_requested_resources_sorted(struct list_head *head,
279 struct list_head *fail_head) 274 struct list_head *fail_head)
@@ -289,8 +284,9 @@ static void assign_requested_resources_sorted(struct list_head *head,
289 pci_assign_resource(dev_res->dev, idx)) { 284 pci_assign_resource(dev_res->dev, idx)) {
290 if (fail_head) { 285 if (fail_head) {
291 /* 286 /*
292 * if the failed res is for ROM BAR, and it will 287 * If the failed resource is a ROM BAR and
293 * be enabled later, don't add it to the list 288 * it will be enabled later, don't add it
289 * to the list.
294 */ 290 */
295 if (!((idx == PCI_ROM_RESOURCE) && 291 if (!((idx == PCI_ROM_RESOURCE) &&
296 (!(res->flags & IORESOURCE_ROM_ENABLE)))) 292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
@@ -309,15 +305,14 @@ static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
309 struct pci_dev_resource *fail_res; 305 struct pci_dev_resource *fail_res;
310 unsigned long mask = 0; 306 unsigned long mask = 0;
311 307
312 /* check failed type */ 308 /* Check failed type */
313 list_for_each_entry(fail_res, fail_head, list) 309 list_for_each_entry(fail_res, fail_head, list)
314 mask |= fail_res->flags; 310 mask |= fail_res->flags;
315 311
316 /* 312 /*
317 * one pref failed resource will set IORESOURCE_MEM, 313 * One pref failed resource will set IORESOURCE_MEM, as we can
318 * as we can allocate pref in non-pref range. 314 * allocate pref in non-pref range. Will release all assigned
319 * Will release all assigned non-pref sibling resources 315 * non-pref sibling resources according to that bit.
320 * according to that bit.
321 */ 316 */
322 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); 317 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
323} 318}
@@ -327,11 +322,11 @@ static bool pci_need_to_release(unsigned long mask, struct resource *res)
327 if (res->flags & IORESOURCE_IO) 322 if (res->flags & IORESOURCE_IO)
328 return !!(mask & IORESOURCE_IO); 323 return !!(mask & IORESOURCE_IO);
329 324
330 /* check pref at first */ 325 /* Check pref at first */
331 if (res->flags & IORESOURCE_PREFETCH) { 326 if (res->flags & IORESOURCE_PREFETCH) {
332 if (mask & IORESOURCE_PREFETCH) 327 if (mask & IORESOURCE_PREFETCH)
333 return true; 328 return true;
334 /* count pref if its parent is non-pref */ 329 /* Count pref if its parent is non-pref */
335 else if ((mask & IORESOURCE_MEM) && 330 else if ((mask & IORESOURCE_MEM) &&
336 !(res->parent->flags & IORESOURCE_PREFETCH)) 331 !(res->parent->flags & IORESOURCE_PREFETCH))
337 return true; 332 return true;
@@ -342,33 +337,33 @@ static bool pci_need_to_release(unsigned long mask, struct resource *res)
342 if (res->flags & IORESOURCE_MEM) 337 if (res->flags & IORESOURCE_MEM)
343 return !!(mask & IORESOURCE_MEM); 338 return !!(mask & IORESOURCE_MEM);
344 339
345 return false; /* should not get here */ 340 return false; /* Should not get here */
346} 341}
347 342
348static void __assign_resources_sorted(struct list_head *head, 343static void __assign_resources_sorted(struct list_head *head,
349 struct list_head *realloc_head, 344 struct list_head *realloc_head,
350 struct list_head *fail_head) 345 struct list_head *fail_head)
351{ 346{
352 /* 347 /*
353 * Should not assign requested resources at first. 348 * Should not assign requested resources at first. They could be
354 * they could be adjacent, so later reassign can not reallocate 349 * adjacent, so later reassign can not reallocate them one by one in
355 * them one by one in parent resource window. 350 * parent resource window.
356 * Try to assign requested + add_size at beginning 351 *
357 * if could do that, could get out early. 352 * Try to assign requested + add_size at beginning. If could do that,
358 * if could not do that, we still try to assign requested at first, 353 * could get out early. If could not do that, we still try to assign
359 * then try to reassign add_size for some resources. 354 * requested at first, then try to reassign add_size for some resources.
360 * 355 *
361 * Separate three resource type checking if we need to release 356 * Separate three resource type checking if we need to release
362 * assigned resource after requested + add_size try. 357 * assigned resource after requested + add_size try.
363 * 1. if there is io port assign fail, will release assigned 358 *
364 * io port. 359 * 1. If IO port assignment fails, will release assigned IO
365 * 2. if there is pref mmio assign fail, release assigned 360 * port.
366 * pref mmio. 361 * 2. If pref MMIO assignment fails, release assigned pref
367 * if assigned pref mmio's parent is non-pref mmio and there 362 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
368 * is non-pref mmio assign fail, will release that assigned 363 * and non-pref MMIO assignment fails, will release that
369 * pref mmio. 364 * assigned pref MMIO.
370 * 3. if there is non-pref mmio assign fail or pref mmio 365 * 3. If non-pref MMIO assignment fails or pref MMIO
371 * assigned fail, will release assigned non-pref mmio. 366 * assignment fails, will release assigned non-pref MMIO.
372 */ 367 */
373 LIST_HEAD(save_head); 368 LIST_HEAD(save_head);
374 LIST_HEAD(local_fail_head); 369 LIST_HEAD(local_fail_head);
@@ -397,7 +392,7 @@ static void __assign_resources_sorted(struct list_head *head,
397 /* 392 /*
398 * There are two kinds of additional resources in the list: 393 * There are two kinds of additional resources in the list:
399 * 1. bridge resource -- IORESOURCE_STARTALIGN 394 * 1. bridge resource -- IORESOURCE_STARTALIGN
400 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN 395 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
401 * Here just fix the additional alignment for bridge 396 * Here just fix the additional alignment for bridge
402 */ 397 */
403 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) 398 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
@@ -406,10 +401,10 @@ static void __assign_resources_sorted(struct list_head *head,
406 add_align = get_res_add_align(realloc_head, dev_res->res); 401 add_align = get_res_add_align(realloc_head, dev_res->res);
407 402
408 /* 403 /*
409 * The "head" list is sorted by the alignment to make sure 404 * The "head" list is sorted by alignment so resources with
410 * resources with bigger alignment will be assigned first. 405 * bigger alignment will be assigned first. After we
411 * After we change the alignment of a dev_res in "head" list, 406 * change the alignment of a dev_res in "head" list, we
412 * we need to reorder the list by alignment to make it 407 * need to reorder the list by alignment to make it
413 * consistent. 408 * consistent.
414 */ 409 */
415 if (add_align > dev_res->res->start) { 410 if (add_align > dev_res->res->start) {
@@ -434,7 +429,7 @@ static void __assign_resources_sorted(struct list_head *head,
434 /* Try updated head list with add_size added */ 429 /* Try updated head list with add_size added */
435 assign_requested_resources_sorted(head, &local_fail_head); 430 assign_requested_resources_sorted(head, &local_fail_head);
436 431
437 /* all assigned with add_size ? */ 432 /* All assigned with add_size? */
438 if (list_empty(&local_fail_head)) { 433 if (list_empty(&local_fail_head)) {
439 /* Remove head list from realloc_head list */ 434 /* Remove head list from realloc_head list */
440 list_for_each_entry(dev_res, head, list) 435 list_for_each_entry(dev_res, head, list)
@@ -444,13 +439,13 @@ static void __assign_resources_sorted(struct list_head *head,
444 return; 439 return;
445 } 440 }
446 441
447 /* check failed type */ 442 /* Check failed type */
448 fail_type = pci_fail_res_type_mask(&local_fail_head); 443 fail_type = pci_fail_res_type_mask(&local_fail_head);
449 /* remove not need to be released assigned res from head list etc */ 444 /* Remove not need to be released assigned res from head list etc */
450 list_for_each_entry_safe(dev_res, tmp_res, head, list) 445 list_for_each_entry_safe(dev_res, tmp_res, head, list)
451 if (dev_res->res->parent && 446 if (dev_res->res->parent &&
452 !pci_need_to_release(fail_type, dev_res->res)) { 447 !pci_need_to_release(fail_type, dev_res->res)) {
453 /* remove it from realloc_head list */ 448 /* Remove it from realloc_head list */
454 remove_from_list(realloc_head, dev_res->res); 449 remove_from_list(realloc_head, dev_res->res);
455 remove_from_list(&save_head, dev_res->res); 450 remove_from_list(&save_head, dev_res->res);
456 list_del(&dev_res->list); 451 list_del(&dev_res->list);
@@ -476,16 +471,15 @@ requested_and_reassign:
476 /* Satisfy the must-have resource requests */ 471 /* Satisfy the must-have resource requests */
477 assign_requested_resources_sorted(head, fail_head); 472 assign_requested_resources_sorted(head, fail_head);
478 473
479 /* Try to satisfy any additional optional resource 474 /* Try to satisfy any additional optional resource requests */
480 requests */
481 if (realloc_head) 475 if (realloc_head)
482 reassign_resources_sorted(realloc_head, head); 476 reassign_resources_sorted(realloc_head, head);
483 free_list(head); 477 free_list(head);
484} 478}
485 479
486static void pdev_assign_resources_sorted(struct pci_dev *dev, 480static void pdev_assign_resources_sorted(struct pci_dev *dev,
487 struct list_head *add_head, 481 struct list_head *add_head,
488 struct list_head *fail_head) 482 struct list_head *fail_head)
489{ 483{
490 LIST_HEAD(head); 484 LIST_HEAD(head);
491 485
@@ -562,17 +556,19 @@ void pci_setup_cardbus(struct pci_bus *bus)
562} 556}
563EXPORT_SYMBOL(pci_setup_cardbus); 557EXPORT_SYMBOL(pci_setup_cardbus);
564 558
565/* Initialize bridges with base/limit values we have collected. 559/*
566 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 560 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
567 requires that if there is no I/O ports or memory behind the 561 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
568 bridge, corresponding range must be turned off by writing base 562 * are no I/O ports or memory behind the bridge, the corresponding range
569 value greater than limit to the bridge's base/limit registers. 563 * must be turned off by writing base value greater than limit to the
570 564 * bridge's base/limit registers.
571 Note: care must be taken when updating I/O base/limit registers 565 *
572 of bridges which support 32-bit I/O. This update requires two 566 * Note: care must be taken when updating I/O base/limit registers of
573 config space writes, so it's quite possible that an I/O window of 567 * bridges which support 32-bit I/O. This update requires two config space
574 the bridge will have some undesirable address (e.g. 0) after the 568 * writes, so it's quite possible that an I/O window of the bridge will
575 first write. Ditto 64-bit prefetchable MMIO. */ 569 * have some undesirable address (e.g. 0) after the first write. Ditto
570 * 64-bit prefetchable MMIO.
571 */
576static void pci_setup_bridge_io(struct pci_dev *bridge) 572static void pci_setup_bridge_io(struct pci_dev *bridge)
577{ 573{
578 struct resource *res; 574 struct resource *res;
@@ -586,7 +582,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
586 if (bridge->io_window_1k) 582 if (bridge->io_window_1k)
587 io_mask = PCI_IO_1K_RANGE_MASK; 583 io_mask = PCI_IO_1K_RANGE_MASK;
588 584
589 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 585 /* Set up the top and bottom of the PCI I/O segment for this bus */
590 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; 586 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
591 pcibios_resource_to_bus(bridge->bus, &region, res); 587 pcibios_resource_to_bus(bridge->bus, &region, res);
592 if (res->flags & IORESOURCE_IO) { 588 if (res->flags & IORESOURCE_IO) {
@@ -594,19 +590,19 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
594 io_base_lo = (region.start >> 8) & io_mask; 590 io_base_lo = (region.start >> 8) & io_mask;
595 io_limit_lo = (region.end >> 8) & io_mask; 591 io_limit_lo = (region.end >> 8) & io_mask;
596 l = ((u16) io_limit_lo << 8) | io_base_lo; 592 l = ((u16) io_limit_lo << 8) | io_base_lo;
597 /* Set up upper 16 bits of I/O base/limit. */ 593 /* Set up upper 16 bits of I/O base/limit */
598 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 594 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
599 pci_info(bridge, " bridge window %pR\n", res); 595 pci_info(bridge, " bridge window %pR\n", res);
600 } else { 596 } else {
601 /* Clear upper 16 bits of I/O base/limit. */ 597 /* Clear upper 16 bits of I/O base/limit */
602 io_upper16 = 0; 598 io_upper16 = 0;
603 l = 0x00f0; 599 l = 0x00f0;
604 } 600 }
605 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 601 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
606 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 602 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
607 /* Update lower 16 bits of I/O base/limit. */ 603 /* Update lower 16 bits of I/O base/limit */
608 pci_write_config_word(bridge, PCI_IO_BASE, l); 604 pci_write_config_word(bridge, PCI_IO_BASE, l);
609 /* Update upper 16 bits of I/O base/limit. */ 605 /* Update upper 16 bits of I/O base/limit */
610 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 606 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
611} 607}
612 608
@@ -616,7 +612,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge)
616 struct pci_bus_region region; 612 struct pci_bus_region region;
617 u32 l; 613 u32 l;
618 614
619 /* Set up the top and bottom of the PCI Memory segment for this bus. */ 615 /* Set up the top and bottom of the PCI Memory segment for this bus */
620 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; 616 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
621 pcibios_resource_to_bus(bridge->bus, &region, res); 617 pcibios_resource_to_bus(bridge->bus, &region, res);
622 if (res->flags & IORESOURCE_MEM) { 618 if (res->flags & IORESOURCE_MEM) {
@@ -635,12 +631,14 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
635 struct pci_bus_region region; 631 struct pci_bus_region region;
636 u32 l, bu, lu; 632 u32 l, bu, lu;
637 633
638 /* Clear out the upper 32 bits of PREF limit. 634 /*
639 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 635 * Clear out the upper 32 bits of PREF limit. If
640 disables PREF range, which is ok. */ 636 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
637 * PREF range, which is ok.
638 */
641 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 639 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
642 640
643 /* Set up PREF base/limit. */ 641 /* Set up PREF base/limit */
644 bu = lu = 0; 642 bu = lu = 0;
645 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; 643 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
646 pcibios_resource_to_bus(bridge->bus, &region, res); 644 pcibios_resource_to_bus(bridge->bus, &region, res);
@@ -657,7 +655,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
657 } 655 }
658 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 656 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
659 657
660 /* Set the upper 32 bits of PREF base & limit. */ 658 /* Set the upper 32 bits of PREF base & limit */
661 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 659 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
662 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 660 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
663} 661}
@@ -701,13 +699,13 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
701 return 0; 699 return 0;
702 700
703 if (pci_claim_resource(bridge, i) == 0) 701 if (pci_claim_resource(bridge, i) == 0)
704 return 0; /* claimed the window */ 702 return 0; /* Claimed the window */
705 703
706 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) 704 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
707 return 0; 705 return 0;
708 706
709 if (!pci_bus_clip_resource(bridge, i)) 707 if (!pci_bus_clip_resource(bridge, i))
710 return -EINVAL; /* clipping didn't change anything */ 708 return -EINVAL; /* Clipping didn't change anything */
711 709
712 switch (i - PCI_BRIDGE_RESOURCES) { 710 switch (i - PCI_BRIDGE_RESOURCES) {
713 case 0: 711 case 0:
@@ -724,14 +722,16 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
724 } 722 }
725 723
726 if (pci_claim_resource(bridge, i) == 0) 724 if (pci_claim_resource(bridge, i) == 0)
727 return 0; /* claimed a smaller window */ 725 return 0; /* Claimed a smaller window */
728 726
729 return -EINVAL; 727 return -EINVAL;
730} 728}
731 729
732/* Check whether the bridge supports optional I/O and 730/*
733 prefetchable memory ranges. If not, the respective 731 * Check whether the bridge supports optional I/O and prefetchable memory
734 base/limit registers must be read-only and read as 0. */ 732 * ranges. If not, the respective base/limit registers must be read-only
733 * and read as 0.
734 */
735static void pci_bridge_check_ranges(struct pci_bus *bus) 735static void pci_bridge_check_ranges(struct pci_bus *bus)
736{ 736{
737 struct pci_dev *bridge = bus->self; 737 struct pci_dev *bridge = bus->self;
@@ -751,12 +751,14 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
751 } 751 }
752} 752}
753 753
754/* Helper function for sizing routines: find first available 754/*
755 bus resource of a given type. Note: we intentionally skip 755 * Helper function for sizing routines: find first available bus resource
756 the bus resources which have already been assigned (that is, 756 * of a given type. Note: we intentionally skip the bus resources which
757 have non-NULL parent resource). */ 757 * have already been assigned (that is, have non-NULL parent resource).
758 */
758static struct resource *find_free_bus_resource(struct pci_bus *bus, 759static struct resource *find_free_bus_resource(struct pci_bus *bus,
759 unsigned long type_mask, unsigned long type) 760 unsigned long type_mask,
761 unsigned long type)
760{ 762{
761 int i; 763 int i;
762 struct resource *r; 764 struct resource *r;
@@ -771,19 +773,21 @@ static struct resource *find_free_bus_resource(struct pci_bus *bus,
771} 773}
772 774
773static resource_size_t calculate_iosize(resource_size_t size, 775static resource_size_t calculate_iosize(resource_size_t size,
774 resource_size_t min_size, 776 resource_size_t min_size,
775 resource_size_t size1, 777 resource_size_t size1,
776 resource_size_t add_size, 778 resource_size_t add_size,
777 resource_size_t children_add_size, 779 resource_size_t children_add_size,
778 resource_size_t old_size, 780 resource_size_t old_size,
779 resource_size_t align) 781 resource_size_t align)
780{ 782{
781 if (size < min_size) 783 if (size < min_size)
782 size = min_size; 784 size = min_size;
783 if (old_size == 1) 785 if (old_size == 1)
784 old_size = 0; 786 old_size = 0;
785 /* To be fixed in 2.5: we should have sort of HAVE_ISA 787 /*
786 flag in the struct pci_bus. */ 788 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
789 * struct pci_bus.
790 */
787#if defined(CONFIG_ISA) || defined(CONFIG_EISA) 791#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
788 size = (size & 0xff) + ((size & ~0xffUL) << 2); 792 size = (size & 0xff) + ((size & ~0xffUL) << 2);
789#endif 793#endif
@@ -796,11 +800,11 @@ static resource_size_t calculate_iosize(resource_size_t size,
796} 800}
797 801
798static resource_size_t calculate_memsize(resource_size_t size, 802static resource_size_t calculate_memsize(resource_size_t size,
799 resource_size_t min_size, 803 resource_size_t min_size,
800 resource_size_t add_size, 804 resource_size_t add_size,
801 resource_size_t children_add_size, 805 resource_size_t children_add_size,
802 resource_size_t old_size, 806 resource_size_t old_size,
803 resource_size_t align) 807 resource_size_t align)
804{ 808{
805 if (size < min_size) 809 if (size < min_size)
806 size = min_size; 810 size = min_size;
@@ -823,8 +827,7 @@ resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
823#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ 827#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
824#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ 828#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
825 829
826static resource_size_t window_alignment(struct pci_bus *bus, 830static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
827 unsigned long type)
828{ 831{
829 resource_size_t align = 1, arch_align; 832 resource_size_t align = 1, arch_align;
830 833
@@ -832,8 +835,8 @@ static resource_size_t window_alignment(struct pci_bus *bus,
832 align = PCI_P2P_DEFAULT_MEM_ALIGN; 835 align = PCI_P2P_DEFAULT_MEM_ALIGN;
833 else if (type & IORESOURCE_IO) { 836 else if (type & IORESOURCE_IO) {
834 /* 837 /*
835 * Per spec, I/O windows are 4K-aligned, but some 838 * Per spec, I/O windows are 4K-aligned, but some bridges have
836 * bridges have an extension to support 1K alignment. 839 * an extension to support 1K alignment.
837 */ 840 */
838 if (bus->self->io_window_1k) 841 if (bus->self->io_window_1k)
839 align = PCI_P2P_DEFAULT_IO_ALIGN_1K; 842 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
@@ -846,20 +849,21 @@ static resource_size_t window_alignment(struct pci_bus *bus,
846} 849}
847 850
848/** 851/**
849 * pbus_size_io() - size the io window of a given bus 852 * pbus_size_io() - Size the I/O window of a given bus
850 * 853 *
851 * @bus : the bus 854 * @bus: The bus
852 * @min_size : the minimum io window that must to be allocated 855 * @min_size: The minimum I/O window that must be allocated
853 * @add_size : additional optional io window 856 * @add_size: Additional optional I/O window
854 * @realloc_head : track the additional io window on this list 857 * @realloc_head: Track the additional I/O window on this list
855 * 858 *
856 * Sizing the IO windows of the PCI-PCI bridge is trivial, 859 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
857 * since these windows have 1K or 4K granularity and the IO ranges 860 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
858 * of non-bridge PCI devices are limited to 256 bytes. 861 * devices are limited to 256 bytes. We must be careful with the ISA
859 * We must be careful with the ISA aliasing though. 862 * aliasing though.
860 */ 863 */
861static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 864static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
862 resource_size_t add_size, struct list_head *realloc_head) 865 resource_size_t add_size,
866 struct list_head *realloc_head)
863{ 867{
864 struct pci_dev *dev; 868 struct pci_dev *dev;
865 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, 869 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
@@ -946,33 +950,33 @@ static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
946} 950}
947 951
948/** 952/**
949 * pbus_size_mem() - size the memory window of a given bus 953 * pbus_size_mem() - Size the memory window of a given bus
950 * 954 *
951 * @bus : the bus 955 * @bus: The bus
952 * @mask: mask the resource flag, then compare it with type 956 * @mask: Mask the resource flag, then compare it with type
953 * @type: the type of free resource from bridge 957 * @type: The type of free resource from bridge
954 * @type2: second match type 958 * @type2: Second match type
955 * @type3: third match type 959 * @type3: Third match type
956 * @min_size : the minimum memory window that must to be allocated 960 * @min_size: The minimum memory window that must be allocated
957 * @add_size : additional optional memory window 961 * @add_size: Additional optional memory window
958 * @realloc_head : track the additional memory window on this list 962 * @realloc_head: Track the additional memory window on this list
959 * 963 *
960 * Calculate the size of the bus and minimal alignment which 964 * Calculate the size of the bus and minimal alignment which guarantees
961 * guarantees that all child resources fit in this size. 965 * that all child resources fit in this size.
962 * 966 *
963 * Returns -ENOSPC if there's no available bus resource of the desired type. 967 * Return -ENOSPC if there's no available bus resource of the desired
964 * Otherwise, sets the bus resource start/end to indicate the required 968 * type. Otherwise, set the bus resource start/end to indicate the
965 * size, adds things to realloc_head (if supplied), and returns 0. 969 * required size, add things to realloc_head (if supplied), and return 0.
966 */ 970 */
967static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 971static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
968 unsigned long type, unsigned long type2, 972 unsigned long type, unsigned long type2,
969 unsigned long type3, 973 unsigned long type3, resource_size_t min_size,
970 resource_size_t min_size, resource_size_t add_size, 974 resource_size_t add_size,
971 struct list_head *realloc_head) 975 struct list_head *realloc_head)
972{ 976{
973 struct pci_dev *dev; 977 struct pci_dev *dev;
974 resource_size_t min_align, align, size, size0, size1; 978 resource_size_t min_align, align, size, size0, size1;
975 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ 979 resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
976 int order, max_order; 980 int order, max_order;
977 struct resource *b_res = find_free_bus_resource(bus, 981 struct resource *b_res = find_free_bus_resource(bus,
978 mask | IORESOURCE_PREFETCH, type); 982 mask | IORESOURCE_PREFETCH, type);
@@ -1001,12 +1005,12 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1001 continue; 1005 continue;
1002 r_size = resource_size(r); 1006 r_size = resource_size(r);
1003#ifdef CONFIG_PCI_IOV 1007#ifdef CONFIG_PCI_IOV
1004 /* put SRIOV requested res to the optional list */ 1008 /* Put SRIOV requested res to the optional list */
1005 if (realloc_head && i >= PCI_IOV_RESOURCES && 1009 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1006 i <= PCI_IOV_RESOURCE_END) { 1010 i <= PCI_IOV_RESOURCE_END) {
1007 add_align = max(pci_resource_alignment(dev, r), add_align); 1011 add_align = max(pci_resource_alignment(dev, r), add_align);
1008 r->end = r->start - 1; 1012 r->end = r->start - 1;
1009 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); 1013 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1010 children_add_size += r_size; 1014 children_add_size += r_size;
1011 continue; 1015 continue;
1012 } 1016 }
@@ -1028,8 +1032,10 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1028 continue; 1032 continue;
1029 } 1033 }
1030 size += max(r_size, align); 1034 size += max(r_size, align);
1031 /* Exclude ranges with size > align from 1035 /*
1032 calculation of the alignment. */ 1036 * Exclude ranges with size > align from calculation of
1037 * the alignment.
1038 */
1033 if (r_size <= align) 1039 if (r_size <= align)
1034 aligns[order] += align; 1040 aligns[order] += align;
1035 if (order > max_order) 1041 if (order > max_order)
@@ -1080,7 +1086,7 @@ unsigned long pci_cardbus_resource_alignment(struct resource *res)
1080} 1086}
1081 1087
1082static void pci_bus_size_cardbus(struct pci_bus *bus, 1088static void pci_bus_size_cardbus(struct pci_bus *bus,
1083 struct list_head *realloc_head) 1089 struct list_head *realloc_head)
1084{ 1090{
1085 struct pci_dev *bridge = bus->self; 1091 struct pci_dev *bridge = bus->self;
1086 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 1092 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
@@ -1090,8 +1096,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
1090 if (b_res[0].parent) 1096 if (b_res[0].parent)
1091 goto handle_b_res_1; 1097 goto handle_b_res_1;
1092 /* 1098 /*
1093 * Reserve some resources for CardBus. We reserve 1099 * Reserve some resources for CardBus. We reserve a fixed amount
1094 * a fixed amount of bus space for CardBus bridges. 1100 * of bus space for CardBus bridges.
1095 */ 1101 */
1096 b_res[0].start = pci_cardbus_io_size; 1102 b_res[0].start = pci_cardbus_io_size;
1097 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; 1103 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
@@ -1115,7 +1121,7 @@ handle_b_res_1:
1115 } 1121 }
1116 1122
1117handle_b_res_2: 1123handle_b_res_2:
1118 /* MEM1 must not be pref mmio */ 1124 /* MEM1 must not be pref MMIO */
1119 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1125 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1120 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1126 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1121 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1127 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
@@ -1123,10 +1129,7 @@ handle_b_res_2:
1123 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1129 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1124 } 1130 }
1125 1131
1126 /* 1132 /* Check whether prefetchable memory is supported by this bridge. */
1127 * Check whether prefetchable memory is supported
1128 * by this bridge.
1129 */
1130 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1133 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1131 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1134 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1132 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1135 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
@@ -1137,9 +1140,8 @@ handle_b_res_2:
1137 if (b_res[2].parent) 1140 if (b_res[2].parent)
1138 goto handle_b_res_3; 1141 goto handle_b_res_3;
1139 /* 1142 /*
1140 * If we have prefetchable memory support, allocate 1143 * If we have prefetchable memory support, allocate two regions.
1141 * two regions. Otherwise, allocate one region of 1144 * Otherwise, allocate one region of twice the size.
1142 * twice the size.
1143 */ 1145 */
1144 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1146 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1145 b_res[2].start = pci_cardbus_mem_size; 1147 b_res[2].start = pci_cardbus_mem_size;
@@ -1152,7 +1154,7 @@ handle_b_res_2:
1152 pci_cardbus_mem_size, pci_cardbus_mem_size); 1154 pci_cardbus_mem_size, pci_cardbus_mem_size);
1153 } 1155 }
1154 1156
1155 /* reduce that to half */ 1157 /* Reduce that to half */
1156 b_res_3_size = pci_cardbus_mem_size; 1158 b_res_3_size = pci_cardbus_mem_size;
1157 } 1159 }
1158 1160
@@ -1203,7 +1205,7 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1203 1205
1204 switch (bus->self->hdr_type) { 1206 switch (bus->self->hdr_type) {
1205 case PCI_HEADER_TYPE_CARDBUS: 1207 case PCI_HEADER_TYPE_CARDBUS:
1206 /* don't size cardbuses yet. */ 1208 /* Don't size CardBuses yet */
1207 break; 1209 break;
1208 1210
1209 case PCI_HEADER_TYPE_BRIDGE: 1211 case PCI_HEADER_TYPE_BRIDGE:
@@ -1270,18 +1272,17 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1270 1272
1271 /* 1273 /*
1272 * Compute the size required to put everything else in the 1274 * Compute the size required to put everything else in the
1273 * non-prefetchable window. This includes: 1275 * non-prefetchable window. This includes:
1274 * 1276 *
1275 * - all non-prefetchable resources 1277 * - all non-prefetchable resources
1276 * - 32-bit prefetchable resources if there's a 64-bit 1278 * - 32-bit prefetchable resources if there's a 64-bit
1277 * prefetchable window or no prefetchable window at all 1279 * prefetchable window or no prefetchable window at all
1278 * - 64-bit prefetchable resources if there's no 1280 * - 64-bit prefetchable resources if there's no prefetchable
1279 * prefetchable window at all 1281 * window at all
1280 * 1282 *
1281 * Note that the strategy in __pci_assign_resource() must 1283 * Note that the strategy in __pci_assign_resource() must match
1282 * match that used here. Specifically, we cannot put a 1284 * that used here. Specifically, we cannot put a 32-bit
1283 * 32-bit prefetchable resource in a 64-bit prefetchable 1285 * prefetchable resource in a 64-bit prefetchable window.
1284 * window.
1285 */ 1286 */
1286 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, 1287 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1287 realloc_head ? 0 : additional_mem_size, 1288 realloc_head ? 0 : additional_mem_size,
@@ -1314,8 +1315,8 @@ static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1314} 1315}
1315 1316
1316/* 1317/*
1317 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they 1318 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1318 * are skipped by pbus_assign_resources_sorted(). 1319 * skipped by pbus_assign_resources_sorted().
1319 */ 1320 */
1320static void pdev_assign_fixed_resources(struct pci_dev *dev) 1321static void pdev_assign_fixed_resources(struct pci_dev *dev)
1321{ 1322{
@@ -1426,10 +1427,9 @@ static void pci_bus_allocate_resources(struct pci_bus *b)
1426 struct pci_bus *child; 1427 struct pci_bus *child;
1427 1428
1428 /* 1429 /*
1429 * Carry out a depth-first search on the PCI bus 1430 * Carry out a depth-first search on the PCI bus tree to allocate
1430 * tree to allocate bridge apertures. Read the 1431 * bridge apertures. Read the programmed bridge bases and
1431 * programmed bridge bases and recursively claim 1432 * recursively claim the respective bridge resources.
1432 * the respective bridge resources.
1433 */ 1433 */
1434 if (b->self) { 1434 if (b->self) {
1435 pci_read_bridge_bases(b); 1435 pci_read_bridge_bases(b);
@@ -1483,7 +1483,7 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1483 IORESOURCE_MEM_64) 1483 IORESOURCE_MEM_64)
1484 1484
1485static void pci_bridge_release_resources(struct pci_bus *bus, 1485static void pci_bridge_release_resources(struct pci_bus *bus,
1486 unsigned long type) 1486 unsigned long type)
1487{ 1487{
1488 struct pci_dev *dev = bus->self; 1488 struct pci_dev *dev = bus->self;
1489 struct resource *r; 1489 struct resource *r;
@@ -1494,16 +1494,14 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
1494 b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; 1494 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1495 1495
1496 /* 1496 /*
1497 * 1. if there is io port assign fail, will release bridge 1497 * 1. If IO port assignment fails, release bridge IO port.
1498 * io port. 1498 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1499 * 2. if there is non pref mmio assign fail, release bridge 1499 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1500 * nonpref mmio. 1500 * release bridge pref MMIO.
1501 * 3. if there is 64bit pref mmio assign fail, and bridge pref 1501 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1502 * is 64bit, release bridge pref mmio. 1502 * release bridge pref MMIO.
1503 * 4. if there is pref mmio assign fail, and bridge pref is 1503 * 5. If pref MMIO assignment fails, and bridge pref is not
1504 * 32bit mmio, release bridge pref mmio 1504 * assigned, release bridge nonpref MMIO.
1505 * 5. if there is pref mmio assign fail, and bridge pref is not
1506 * assigned, release bridge nonpref mmio.
1507 */ 1505 */
1508 if (type & IORESOURCE_IO) 1506 if (type & IORESOURCE_IO)
1509 idx = 0; 1507 idx = 0;
@@ -1523,25 +1521,22 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
1523 if (!r->parent) 1521 if (!r->parent)
1524 return; 1522 return;
1525 1523
1526 /* 1524 /* If there are children, release them all */
1527 * if there are children under that, we should release them
1528 * all
1529 */
1530 release_child_resources(r); 1525 release_child_resources(r);
1531 if (!release_resource(r)) { 1526 if (!release_resource(r)) {
1532 type = old_flags = r->flags & PCI_RES_TYPE_MASK; 1527 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1533 pci_info(dev, "resource %d %pR released\n", 1528 pci_info(dev, "resource %d %pR released\n",
1534 PCI_BRIDGE_RESOURCES + idx, r); 1529 PCI_BRIDGE_RESOURCES + idx, r);
1535 /* keep the old size */ 1530 /* Keep the old size */
1536 r->end = resource_size(r) - 1; 1531 r->end = resource_size(r) - 1;
1537 r->start = 0; 1532 r->start = 0;
1538 r->flags = 0; 1533 r->flags = 0;
1539 1534
1540 /* avoiding touch the one without PREF */ 1535 /* Avoiding touch the one without PREF */
1541 if (type & IORESOURCE_PREFETCH) 1536 if (type & IORESOURCE_PREFETCH)
1542 type = IORESOURCE_PREFETCH; 1537 type = IORESOURCE_PREFETCH;
1543 __pci_setup_bridge(bus, type); 1538 __pci_setup_bridge(bus, type);
1544 /* for next child res under same bridge */ 1539 /* For next child res under same bridge */
1545 r->flags = old_flags; 1540 r->flags = old_flags;
1546 } 1541 }
1547} 1542}
@@ -1550,9 +1545,10 @@ enum release_type {
1550 leaf_only, 1545 leaf_only,
1551 whole_subtree, 1546 whole_subtree,
1552}; 1547};
1548
1553/* 1549/*
1554 * try to release pci bridge resources that is from leaf bridge, 1550 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1555 * so we can allocate big new one later 1551 * a larger window later.
1556 */ 1552 */
1557static void pci_bus_release_bridge_resources(struct pci_bus *bus, 1553static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1558 unsigned long type, 1554 unsigned long type,
@@ -1677,7 +1673,7 @@ static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1677 pcibios_resource_to_bus(dev->bus, &region, r); 1673 pcibios_resource_to_bus(dev->bus, &region, r);
1678 if (!region.start) { 1674 if (!region.start) {
1679 *unassigned = true; 1675 *unassigned = true;
1680 return 1; /* return early from pci_walk_bus() */ 1676 return 1; /* Return early from pci_walk_bus() */
1681 } 1677 }
1682 } 1678 }
1683 1679
@@ -1685,7 +1681,7 @@ static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1685} 1681}
1686 1682
1687static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1683static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1688 enum enable_type enable_local) 1684 enum enable_type enable_local)
1689{ 1685{
1690 bool unassigned = false; 1686 bool unassigned = false;
1691 1687
@@ -1700,21 +1696,21 @@ static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1700} 1696}
1701#else 1697#else
1702static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1698static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1703 enum enable_type enable_local) 1699 enum enable_type enable_local)
1704{ 1700{
1705 return enable_local; 1701 return enable_local;
1706} 1702}
1707#endif 1703#endif
1708 1704
1709/* 1705/*
1710 * first try will not touch pci bridge res 1706 * First try will not touch PCI bridge res.
1711 * second and later try will clear small leaf bridge res 1707 * Second and later try will clear small leaf bridge res.
1712 * will stop till to the max depth if can not find good one 1708 * Will stop till to the max depth if can not find good one.
1713 */ 1709 */
1714void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 1710void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1715{ 1711{
1716 LIST_HEAD(realloc_head); /* list of resources that 1712 LIST_HEAD(realloc_head);
1717 want additional resources */ 1713 /* List of resources that want additional resources */
1718 struct list_head *add_list = NULL; 1714 struct list_head *add_list = NULL;
1719 int tried_times = 0; 1715 int tried_times = 0;
1720 enum release_type rel_type = leaf_only; 1716 enum release_type rel_type = leaf_only;
@@ -1723,7 +1719,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1723 int pci_try_num = 1; 1719 int pci_try_num = 1;
1724 enum enable_type enable_local; 1720 enum enable_type enable_local;
1725 1721
1726 /* don't realloc if asked to do so */ 1722 /* Don't realloc if asked to do so */
1727 enable_local = pci_realloc_detect(bus, pci_realloc_enable); 1723 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1728 if (pci_realloc_enabled(enable_local)) { 1724 if (pci_realloc_enabled(enable_local)) {
1729 int max_depth = pci_bus_get_depth(bus); 1725 int max_depth = pci_bus_get_depth(bus);
@@ -1735,13 +1731,14 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1735 1731
1736again: 1732again:
1737 /* 1733 /*
1738 * last try will use add_list, otherwise will try good to have as 1734 * Last try will use add_list, otherwise will try good to have as must
1739 * must have, so can realloc parent bridge resource 1735 * have, so can realloc parent bridge resource
1740 */ 1736 */
1741 if (tried_times + 1 == pci_try_num) 1737 if (tried_times + 1 == pci_try_num)
1742 add_list = &realloc_head; 1738 add_list = &realloc_head;
1743 /* Depth first, calculate sizes and alignments of all 1739 /*
1744 subordinate buses. */ 1740 * Depth first, calculate sizes and alignments of all subordinate buses.
1741 */
1745 __pci_bus_size_bridges(bus, add_list); 1742 __pci_bus_size_bridges(bus, add_list);
1746 1743
1747 /* Depth last, allocate resources and update the hardware. */ 1744 /* Depth last, allocate resources and update the hardware. */
@@ -1750,7 +1747,7 @@ again:
1750 BUG_ON(!list_empty(add_list)); 1747 BUG_ON(!list_empty(add_list));
1751 tried_times++; 1748 tried_times++;
1752 1749
1753 /* any device complain? */ 1750 /* Any device complain? */
1754 if (list_empty(&fail_head)) 1751 if (list_empty(&fail_head))
1755 goto dump; 1752 goto dump;
1756 1753
@@ -1767,20 +1764,20 @@ again:
1767 dev_info(&bus->dev, "No. %d try to assign unassigned res\n", 1764 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1768 tried_times + 1); 1765 tried_times + 1);
1769 1766
1770 /* third times and later will not check if it is leaf */ 1767 /* Third times and later will not check if it is leaf */
1771 if ((tried_times + 1) > 2) 1768 if ((tried_times + 1) > 2)
1772 rel_type = whole_subtree; 1769 rel_type = whole_subtree;
1773 1770
1774 /* 1771 /*
1775 * Try to release leaf bridge's resources that doesn't fit resource of 1772 * Try to release leaf bridge's resources that doesn't fit resource of
1776 * child device under that bridge 1773 * child device under that bridge.
1777 */ 1774 */
1778 list_for_each_entry(fail_res, &fail_head, list) 1775 list_for_each_entry(fail_res, &fail_head, list)
1779 pci_bus_release_bridge_resources(fail_res->dev->bus, 1776 pci_bus_release_bridge_resources(fail_res->dev->bus,
1780 fail_res->flags & PCI_RES_TYPE_MASK, 1777 fail_res->flags & PCI_RES_TYPE_MASK,
1781 rel_type); 1778 rel_type);
1782 1779
1783 /* restore size and flags */ 1780 /* Restore size and flags */
1784 list_for_each_entry(fail_res, &fail_head, list) { 1781 list_for_each_entry(fail_res, &fail_head, list) {
1785 struct resource *res = fail_res->res; 1782 struct resource *res = fail_res->res;
1786 1783
@@ -1795,7 +1792,7 @@ again:
1795 goto again; 1792 goto again;
1796 1793
1797dump: 1794dump:
1798 /* dump the resource on buses */ 1795 /* Dump the resource on buses */
1799 pci_bus_dump_resources(bus); 1796 pci_bus_dump_resources(bus);
1800} 1797}
1801 1798
@@ -1806,14 +1803,15 @@ void __init pci_assign_unassigned_resources(void)
1806 list_for_each_entry(root_bus, &pci_root_buses, node) { 1803 list_for_each_entry(root_bus, &pci_root_buses, node) {
1807 pci_assign_unassigned_root_bus_resources(root_bus); 1804 pci_assign_unassigned_root_bus_resources(root_bus);
1808 1805
1809 /* Make sure the root bridge has a companion ACPI device: */ 1806 /* Make sure the root bridge has a companion ACPI device */
1810 if (ACPI_HANDLE(root_bus->bridge)) 1807 if (ACPI_HANDLE(root_bus->bridge))
1811 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); 1808 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1812 } 1809 }
1813} 1810}
1814 1811
1815static void extend_bridge_window(struct pci_dev *bridge, struct resource *res, 1812static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1816 struct list_head *add_list, resource_size_t available) 1813 struct list_head *add_list,
1814 resource_size_t available)
1817{ 1815{
1818 struct pci_dev_resource *dev_res; 1816 struct pci_dev_resource *dev_res;
1819 1817
@@ -1837,8 +1835,10 @@ static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1837} 1835}
1838 1836
1839static void pci_bus_distribute_available_resources(struct pci_bus *bus, 1837static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1840 struct list_head *add_list, resource_size_t available_io, 1838 struct list_head *add_list,
1841 resource_size_t available_mmio, resource_size_t available_mmio_pref) 1839 resource_size_t available_io,
1840 resource_size_t available_mmio,
1841 resource_size_t available_mmio_pref)
1842{ 1842{
1843 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref; 1843 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1844 unsigned int normal_bridges = 0, hotplug_bridges = 0; 1844 unsigned int normal_bridges = 0, hotplug_bridges = 0;
@@ -1862,7 +1862,7 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1862 1862
1863 /* 1863 /*
1864 * Calculate the total amount of extra resource space we can 1864 * Calculate the total amount of extra resource space we can
1865 * pass to bridges below this one. This is basically the 1865 * pass to bridges below this one. This is basically the
1866 * extra space reduced by the minimal required space for the 1866 * extra space reduced by the minimal required space for the
1867 * non-hotplug bridges. 1867 * non-hotplug bridges.
1868 */ 1868 */
@@ -1872,7 +1872,7 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1872 1872
1873 /* 1873 /*
1874 * Calculate how many hotplug bridges and normal bridges there 1874 * Calculate how many hotplug bridges and normal bridges there
1875 * are on this bus. We will distribute the additional available 1875 * are on this bus. We will distribute the additional available
1876 * resources between hotplug bridges. 1876 * resources between hotplug bridges.
1877 */ 1877 */
1878 for_each_pci_bridge(dev, bus) { 1878 for_each_pci_bridge(dev, bus) {
@@ -1907,8 +1907,8 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1907 1907
1908 /* 1908 /*
1909 * There is only one bridge on the bus so it gets all available 1909 * There is only one bridge on the bus so it gets all available
1910 * resources which it can then distribute to the possible 1910 * resources which it can then distribute to the possible hotplug
1911 * hotplug bridges below. 1911 * bridges below.
1912 */ 1912 */
1913 if (hotplug_bridges + normal_bridges == 1) { 1913 if (hotplug_bridges + normal_bridges == 1) {
1914 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list); 1914 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
@@ -1959,9 +1959,8 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1959 } 1959 }
1960} 1960}
1961 1961
1962static void 1962static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1963pci_bridge_distribute_available_resources(struct pci_dev *bridge, 1963 struct list_head *add_list)
1964 struct list_head *add_list)
1965{ 1964{
1966 resource_size_t available_io, available_mmio, available_mmio_pref; 1965 resource_size_t available_io, available_mmio, available_mmio_pref;
1967 const struct resource *res; 1966 const struct resource *res;
@@ -1978,14 +1977,17 @@ pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1978 available_mmio_pref = resource_size(res); 1977 available_mmio_pref = resource_size(res);
1979 1978
1980 pci_bus_distribute_available_resources(bridge->subordinate, 1979 pci_bus_distribute_available_resources(bridge->subordinate,
1981 add_list, available_io, available_mmio, available_mmio_pref); 1980 add_list, available_io,
1981 available_mmio,
1982 available_mmio_pref);
1982} 1983}
1983 1984
1984void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 1985void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1985{ 1986{
1986 struct pci_bus *parent = bridge->subordinate; 1987 struct pci_bus *parent = bridge->subordinate;
1987 LIST_HEAD(add_list); /* list of resources that 1988 /* List of resources that want additional resources */
1988 want additional resources */ 1989 LIST_HEAD(add_list);
1990
1989 int tried_times = 0; 1991 int tried_times = 0;
1990 LIST_HEAD(fail_head); 1992 LIST_HEAD(fail_head);
1991 struct pci_dev_resource *fail_res; 1993 struct pci_dev_resource *fail_res;
@@ -1995,9 +1997,9 @@ again:
1995 __pci_bus_size_bridges(parent, &add_list); 1997 __pci_bus_size_bridges(parent, &add_list);
1996 1998
1997 /* 1999 /*
1998 * Distribute remaining resources (if any) equally between 2000 * Distribute remaining resources (if any) equally between hotplug
1999 * hotplug bridges below. This makes it possible to extend the 2001 * bridges below. This makes it possible to extend the hierarchy
2000 * hierarchy later without running out of resources. 2002 * later without running out of resources.
2001 */ 2003 */
2002 pci_bridge_distribute_available_resources(bridge, &add_list); 2004 pci_bridge_distribute_available_resources(bridge, &add_list);
2003 2005
@@ -2009,7 +2011,7 @@ again:
2009 goto enable_all; 2011 goto enable_all;
2010 2012
2011 if (tried_times >= 2) { 2013 if (tried_times >= 2) {
2012 /* still fail, don't need to try more */ 2014 /* Still fail, don't need to try more */
2013 free_list(&fail_head); 2015 free_list(&fail_head);
2014 goto enable_all; 2016 goto enable_all;
2015 } 2017 }
@@ -2018,15 +2020,15 @@ again:
2018 tried_times + 1); 2020 tried_times + 1);
2019 2021
2020 /* 2022 /*
2021 * Try to release leaf bridge's resources that doesn't fit resource of 2023 * Try to release leaf bridge's resources that aren't big enough
2022 * child device under that bridge 2024 * to contain child device resources.
2023 */ 2025 */
2024 list_for_each_entry(fail_res, &fail_head, list) 2026 list_for_each_entry(fail_res, &fail_head, list)
2025 pci_bus_release_bridge_resources(fail_res->dev->bus, 2027 pci_bus_release_bridge_resources(fail_res->dev->bus,
2026 fail_res->flags & PCI_RES_TYPE_MASK, 2028 fail_res->flags & PCI_RES_TYPE_MASK,
2027 whole_subtree); 2029 whole_subtree);
2028 2030
2029 /* restore size and flags */ 2031 /* Restore size and flags */
2030 list_for_each_entry(fail_res, &fail_head, list) { 2032 list_for_each_entry(fail_res, &fail_head, list) {
2031 struct resource *res = fail_res->res; 2033 struct resource *res = fail_res->res;
2032 2034
@@ -2105,7 +2107,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2105 } 2107 }
2106 2108
2107 list_for_each_entry(dev_res, &saved, list) { 2109 list_for_each_entry(dev_res, &saved, list) {
2108 /* Skip the bridge we just assigned resources for. */ 2110 /* Skip the bridge we just assigned resources for */
2109 if (bridge == dev_res->dev) 2111 if (bridge == dev_res->dev)
2110 continue; 2112 continue;
2111 2113
@@ -2117,7 +2119,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2117 return 0; 2119 return 0;
2118 2120
2119cleanup: 2121cleanup:
2120 /* restore size and flags */ 2122 /* Restore size and flags */
2121 list_for_each_entry(dev_res, &failed, list) { 2123 list_for_each_entry(dev_res, &failed, list) {
2122 struct resource *res = dev_res->res; 2124 struct resource *res = dev_res->res;
2123 2125
@@ -2149,8 +2151,8 @@ cleanup:
2149void pci_assign_unassigned_bus_resources(struct pci_bus *bus) 2151void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2150{ 2152{
2151 struct pci_dev *dev; 2153 struct pci_dev *dev;
2152 LIST_HEAD(add_list); /* list of resources that 2154 /* List of resources that want additional resources */
2153 want additional resources */ 2155 LIST_HEAD(add_list);
2154 2156
2155 down_read(&pci_bus_sem); 2157 down_read(&pci_bus_sem);
2156 for_each_pci_bridge(dev, bus) 2158 for_each_pci_bridge(dev, bus)
diff --git a/include/linux/cper.h b/include/linux/cper.h
index 9c703a0abe6e..cc4980bb0f65 100644
--- a/include/linux/cper.h
+++ b/include/linux/cper.h
@@ -44,7 +44,7 @@
44 */ 44 */
45#define CPER_REC_LEN 256 45#define CPER_REC_LEN 256
46/* 46/*
47 * Severity difinition for error_severity in struct cper_record_header 47 * Severity definition for error_severity in struct cper_record_header
48 * and section_severity in struct cper_section_descriptor 48 * and section_severity in struct cper_section_descriptor
49 */ 49 */
50enum { 50enum {
@@ -55,24 +55,21 @@ enum {
55}; 55};
56 56
57/* 57/*
58 * Validation bits difinition for validation_bits in struct 58 * Validation bits definition for validation_bits in struct
59 * cper_record_header. If set, corresponding fields in struct 59 * cper_record_header. If set, corresponding fields in struct
60 * cper_record_header contain valid information. 60 * cper_record_header contain valid information.
61 *
62 * corresponds platform_id
63 */ 61 */
64#define CPER_VALID_PLATFORM_ID 0x0001 62#define CPER_VALID_PLATFORM_ID 0x0001
65/* corresponds timestamp */
66#define CPER_VALID_TIMESTAMP 0x0002 63#define CPER_VALID_TIMESTAMP 0x0002
67/* corresponds partition_id */
68#define CPER_VALID_PARTITION_ID 0x0004 64#define CPER_VALID_PARTITION_ID 0x0004
69 65
70/* 66/*
71 * Notification type used to generate error record, used in 67 * Notification type used to generate error record, used in
72 * notification_type in struct cper_record_header 68 * notification_type in struct cper_record_header. These UUIDs are defined
73 * 69 * in the UEFI spec v2.7, sec N.2.1.
74 * Corrected Machine Check
75 */ 70 */
71
72/* Corrected Machine Check */
76#define CPER_NOTIFY_CMC \ 73#define CPER_NOTIFY_CMC \
77 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ 74 GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
78 0xEB, 0xD4, 0xF8, 0x90) 75 0xEB, 0xD4, 0xF8, 0x90)
@@ -122,14 +119,11 @@ enum {
122#define CPER_SEC_REV 0x0100 119#define CPER_SEC_REV 0x0100
123 120
124/* 121/*
125 * Validation bits difinition for validation_bits in struct 122 * Validation bits definition for validation_bits in struct
126 * cper_section_descriptor. If set, corresponding fields in struct 123 * cper_section_descriptor. If set, corresponding fields in struct
127 * cper_section_descriptor contain valid information. 124 * cper_section_descriptor contain valid information.
128 *
129 * corresponds fru_id
130 */ 125 */
131#define CPER_SEC_VALID_FRU_ID 0x1 126#define CPER_SEC_VALID_FRU_ID 0x1
132/* corresponds fru_text */
133#define CPER_SEC_VALID_FRU_TEXT 0x2 127#define CPER_SEC_VALID_FRU_TEXT 0x2
134 128
135/* 129/*
@@ -165,10 +159,11 @@ enum {
165 159
166/* 160/*
167 * Section type definitions, used in section_type field in struct 161 * Section type definitions, used in section_type field in struct
168 * cper_section_descriptor 162 * cper_section_descriptor. These UUIDs are defined in the UEFI spec
169 * 163 * v2.7, sec N.2.2.
170 * Processor Generic
171 */ 164 */
165
166/* Processor Generic */
172#define CPER_SEC_PROC_GENERIC \ 167#define CPER_SEC_PROC_GENERIC \
173 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \ 168 GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
174 0x93, 0xC4, 0xF3, 0xDB) 169 0x93, 0xC4, 0xF3, 0xDB)
@@ -325,220 +320,223 @@ enum {
325 */ 320 */
326#pragma pack(1) 321#pragma pack(1)
327 322
323/* Record Header, UEFI v2.7 sec N.2.1 */
328struct cper_record_header { 324struct cper_record_header {
329 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */ 325 char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
330 __u16 revision; /* must be CPER_RECORD_REV */ 326 u16 revision; /* must be CPER_RECORD_REV */
331 __u32 signature_end; /* must be CPER_SIG_END */ 327 u32 signature_end; /* must be CPER_SIG_END */
332 __u16 section_count; 328 u16 section_count;
333 __u32 error_severity; 329 u32 error_severity;
334 __u32 validation_bits; 330 u32 validation_bits;
335 __u32 record_length; 331 u32 record_length;
336 __u64 timestamp; 332 u64 timestamp;
337 guid_t platform_id; 333 guid_t platform_id;
338 guid_t partition_id; 334 guid_t partition_id;
339 guid_t creator_id; 335 guid_t creator_id;
340 guid_t notification_type; 336 guid_t notification_type;
341 __u64 record_id; 337 u64 record_id;
342 __u32 flags; 338 u32 flags;
343 __u64 persistence_information; 339 u64 persistence_information;
344 __u8 reserved[12]; /* must be zero */ 340 u8 reserved[12]; /* must be zero */
345}; 341};
346 342
343/* Section Descriptor, UEFI v2.7 sec N.2.2 */
347struct cper_section_descriptor { 344struct cper_section_descriptor {
348 __u32 section_offset; /* Offset in bytes of the 345 u32 section_offset; /* Offset in bytes of the
349 * section body from the base 346 * section body from the base
350 * of the record header */ 347 * of the record header */
351 __u32 section_length; 348 u32 section_length;
352 __u16 revision; /* must be CPER_RECORD_REV */ 349 u16 revision; /* must be CPER_RECORD_REV */
353 __u8 validation_bits; 350 u8 validation_bits;
354 __u8 reserved; /* must be zero */ 351 u8 reserved; /* must be zero */
355 __u32 flags; 352 u32 flags;
356 guid_t section_type; 353 guid_t section_type;
357 guid_t fru_id; 354 guid_t fru_id;
358 __u32 section_severity; 355 u32 section_severity;
359 __u8 fru_text[20]; 356 u8 fru_text[20];
360}; 357};
361 358
362/* Generic Processor Error Section */ 359/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
363struct cper_sec_proc_generic { 360struct cper_sec_proc_generic {
364 __u64 validation_bits; 361 u64 validation_bits;
365 __u8 proc_type; 362 u8 proc_type;
366 __u8 proc_isa; 363 u8 proc_isa;
367 __u8 proc_error_type; 364 u8 proc_error_type;
368 __u8 operation; 365 u8 operation;
369 __u8 flags; 366 u8 flags;
370 __u8 level; 367 u8 level;
371 __u16 reserved; 368 u16 reserved;
372 __u64 cpu_version; 369 u64 cpu_version;
373 char cpu_brand[128]; 370 char cpu_brand[128];
374 __u64 proc_id; 371 u64 proc_id;
375 __u64 target_addr; 372 u64 target_addr;
376 __u64 requestor_id; 373 u64 requestor_id;
377 __u64 responder_id; 374 u64 responder_id;
378 __u64 ip; 375 u64 ip;
379}; 376};
380 377
381/* IA32/X64 Processor Error Section */ 378/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
382struct cper_sec_proc_ia { 379struct cper_sec_proc_ia {
383 __u64 validation_bits; 380 u64 validation_bits;
384 __u64 lapic_id; 381 u64 lapic_id;
385 __u8 cpuid[48]; 382 u8 cpuid[48];
386}; 383};
387 384
388/* IA32/X64 Processor Error Information Structure */ 385/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
389struct cper_ia_err_info { 386struct cper_ia_err_info {
390 guid_t err_type; 387 guid_t err_type;
391 __u64 validation_bits; 388 u64 validation_bits;
392 __u64 check_info; 389 u64 check_info;
393 __u64 target_id; 390 u64 target_id;
394 __u64 requestor_id; 391 u64 requestor_id;
395 __u64 responder_id; 392 u64 responder_id;
396 __u64 ip; 393 u64 ip;
397}; 394};
398 395
399/* IA32/X64 Processor Context Information Structure */ 396/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
400struct cper_ia_proc_ctx { 397struct cper_ia_proc_ctx {
401 __u16 reg_ctx_type; 398 u16 reg_ctx_type;
402 __u16 reg_arr_size; 399 u16 reg_arr_size;
403 __u32 msr_addr; 400 u32 msr_addr;
404 __u64 mm_reg_addr; 401 u64 mm_reg_addr;
405}; 402};
406 403
407/* ARM Processor Error Section */ 404/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
408struct cper_sec_proc_arm { 405struct cper_sec_proc_arm {
409 __u32 validation_bits; 406 u32 validation_bits;
410 __u16 err_info_num; /* Number of Processor Error Info */ 407 u16 err_info_num; /* Number of Processor Error Info */
411 __u16 context_info_num; /* Number of Processor Context Info Records*/ 408 u16 context_info_num; /* Number of Processor Context Info Records*/
412 __u32 section_length; 409 u32 section_length;
413 __u8 affinity_level; 410 u8 affinity_level;
414 __u8 reserved[3]; /* must be zero */ 411 u8 reserved[3]; /* must be zero */
415 __u64 mpidr; 412 u64 mpidr;
416 __u64 midr; 413 u64 midr;
417 __u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */ 414 u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
418 __u32 psci_state; 415 u32 psci_state;
419}; 416};
420 417
421/* ARM Processor Error Information Structure */ 418/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
422struct cper_arm_err_info { 419struct cper_arm_err_info {
423 __u8 version; 420 u8 version;
424 __u8 length; 421 u8 length;
425 __u16 validation_bits; 422 u16 validation_bits;
426 __u8 type; 423 u8 type;
427 __u16 multiple_error; 424 u16 multiple_error;
428 __u8 flags; 425 u8 flags;
429 __u64 error_info; 426 u64 error_info;
430 __u64 virt_fault_addr; 427 u64 virt_fault_addr;
431 __u64 physical_fault_addr; 428 u64 physical_fault_addr;
432}; 429};
433 430
434/* ARM Processor Context Information Structure */ 431/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
435struct cper_arm_ctx_info { 432struct cper_arm_ctx_info {
436 __u16 version; 433 u16 version;
437 __u16 type; 434 u16 type;
438 __u32 size; 435 u32 size;
439}; 436};
440 437
441/* Old Memory Error Section UEFI 2.1, 2.2 */ 438/* Old Memory Error Section, UEFI v2.1, v2.2 */
442struct cper_sec_mem_err_old { 439struct cper_sec_mem_err_old {
443 __u64 validation_bits; 440 u64 validation_bits;
444 __u64 error_status; 441 u64 error_status;
445 __u64 physical_addr; 442 u64 physical_addr;
446 __u64 physical_addr_mask; 443 u64 physical_addr_mask;
447 __u16 node; 444 u16 node;
448 __u16 card; 445 u16 card;
449 __u16 module; 446 u16 module;
450 __u16 bank; 447 u16 bank;
451 __u16 device; 448 u16 device;
452 __u16 row; 449 u16 row;
453 __u16 column; 450 u16 column;
454 __u16 bit_pos; 451 u16 bit_pos;
455 __u64 requestor_id; 452 u64 requestor_id;
456 __u64 responder_id; 453 u64 responder_id;
457 __u64 target_id; 454 u64 target_id;
458 __u8 error_type; 455 u8 error_type;
459}; 456};
460 457
461/* Memory Error Section UEFI >= 2.3 */ 458/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
462struct cper_sec_mem_err { 459struct cper_sec_mem_err {
463 __u64 validation_bits; 460 u64 validation_bits;
464 __u64 error_status; 461 u64 error_status;
465 __u64 physical_addr; 462 u64 physical_addr;
466 __u64 physical_addr_mask; 463 u64 physical_addr_mask;
467 __u16 node; 464 u16 node;
468 __u16 card; 465 u16 card;
469 __u16 module; 466 u16 module;
470 __u16 bank; 467 u16 bank;
471 __u16 device; 468 u16 device;
472 __u16 row; 469 u16 row;
473 __u16 column; 470 u16 column;
474 __u16 bit_pos; 471 u16 bit_pos;
475 __u64 requestor_id; 472 u64 requestor_id;
476 __u64 responder_id; 473 u64 responder_id;
477 __u64 target_id; 474 u64 target_id;
478 __u8 error_type; 475 u8 error_type;
479 __u8 reserved; 476 u8 reserved;
480 __u16 rank; 477 u16 rank;
481 __u16 mem_array_handle; /* card handle in UEFI 2.4 */ 478 u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
482 __u16 mem_dev_handle; /* module handle in UEFI 2.4 */ 479 u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
483}; 480};
484 481
485struct cper_mem_err_compact { 482struct cper_mem_err_compact {
486 __u64 validation_bits; 483 u64 validation_bits;
487 __u16 node; 484 u16 node;
488 __u16 card; 485 u16 card;
489 __u16 module; 486 u16 module;
490 __u16 bank; 487 u16 bank;
491 __u16 device; 488 u16 device;
492 __u16 row; 489 u16 row;
493 __u16 column; 490 u16 column;
494 __u16 bit_pos; 491 u16 bit_pos;
495 __u64 requestor_id; 492 u64 requestor_id;
496 __u64 responder_id; 493 u64 responder_id;
497 __u64 target_id; 494 u64 target_id;
498 __u16 rank; 495 u16 rank;
499 __u16 mem_array_handle; 496 u16 mem_array_handle;
500 __u16 mem_dev_handle; 497 u16 mem_dev_handle;
501}; 498};
502 499
500/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
503struct cper_sec_pcie { 501struct cper_sec_pcie {
504 __u64 validation_bits; 502 u64 validation_bits;
505 __u32 port_type; 503 u32 port_type;
506 struct { 504 struct {
507 __u8 minor; 505 u8 minor;
508 __u8 major; 506 u8 major;
509 __u8 reserved[2]; 507 u8 reserved[2];
510 } version; 508 } version;
511 __u16 command; 509 u16 command;
512 __u16 status; 510 u16 status;
513 __u32 reserved; 511 u32 reserved;
514 struct { 512 struct {
515 __u16 vendor_id; 513 u16 vendor_id;
516 __u16 device_id; 514 u16 device_id;
517 __u8 class_code[3]; 515 u8 class_code[3];
518 __u8 function; 516 u8 function;
519 __u8 device; 517 u8 device;
520 __u16 segment; 518 u16 segment;
521 __u8 bus; 519 u8 bus;
522 __u8 secondary_bus; 520 u8 secondary_bus;
523 __u16 slot; 521 u16 slot;
524 __u8 reserved; 522 u8 reserved;
525 } device_id; 523 } device_id;
526 struct { 524 struct {
527 __u32 lower; 525 u32 lower;
528 __u32 upper; 526 u32 upper;
529 } serial_number; 527 } serial_number;
530 struct { 528 struct {
531 __u16 secondary_status; 529 u16 secondary_status;
532 __u16 control; 530 u16 control;
533 } bridge; 531 } bridge;
534 __u8 capability[60]; 532 u8 capability[60];
535 __u8 aer_info[96]; 533 u8 aer_info[96];
536}; 534};
537 535
538/* Reset to default packing */ 536/* Reset to default packing */
539#pragma pack() 537#pragma pack()
540 538
541extern const char * const cper_proc_error_type_strs[4]; 539extern const char *const cper_proc_error_type_strs[4];
542 540
543u64 cper_next_record_id(void); 541u64 cper_next_record_id(void);
544const char *cper_severity_str(unsigned int); 542const char *cper_severity_str(unsigned int);
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index c51e0066de8b..27164769d184 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1,7 +1,5 @@
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/* 2/*
3 * pci_regs.h
4 *
5 * PCI standard defines 3 * PCI standard defines
6 * Copyright 1994, Drew Eckhardt 4 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
@@ -15,7 +13,7 @@
15 * PCI System Design Guide 13 * PCI System Design Guide
16 * 14 *
17 * For HyperTransport information, please consult the following manuals 15 * For HyperTransport information, please consult the following manuals
18 * from http://www.hypertransport.org 16 * from http://www.hypertransport.org :
19 * 17 *
20 * The HyperTransport I/O Link Specification 18 * The HyperTransport I/O Link Specification
21 */ 19 */
@@ -301,7 +299,7 @@
301#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 299#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
302#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 300#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
303 301
304/* Message Signalled Interrupts registers */ 302/* Message Signalled Interrupt registers */
305 303
306#define PCI_MSI_FLAGS 2 /* Message Control */ 304#define PCI_MSI_FLAGS 2 /* Message Control */
307#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 305#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
@@ -319,7 +317,7 @@
319#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ 317#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
320#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ 318#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
321 319
322/* MSI-X registers */ 320/* MSI-X registers (in MSI-X capability) */
323#define PCI_MSIX_FLAGS 2 /* Message Control */ 321#define PCI_MSIX_FLAGS 2 /* Message Control */
324#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ 322#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
325#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 323#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
@@ -333,13 +331,13 @@
333#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ 331#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
334#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 332#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
335 333
336/* MSI-X Table entry format */ 334/* MSI-X Table entry format (in memory mapped by a BAR) */
337#define PCI_MSIX_ENTRY_SIZE 16 335#define PCI_MSIX_ENTRY_SIZE 16
338#define PCI_MSIX_ENTRY_LOWER_ADDR 0 336#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
339#define PCI_MSIX_ENTRY_UPPER_ADDR 4 337#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
340#define PCI_MSIX_ENTRY_DATA 8 338#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
341#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 339#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
342#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 340#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
343 341
344/* CompactPCI Hotswap Register */ 342/* CompactPCI Hotswap Register */
345 343
@@ -471,19 +469,19 @@
471/* PCI Express capability registers */ 469/* PCI Express capability registers */
472 470
473#define PCI_EXP_FLAGS 2 /* Capabilities register */ 471#define PCI_EXP_FLAGS 2 /* Capabilities register */
474#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 472#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
475#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 473#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
476#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 474#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
477#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 475#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
478#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 476#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
479#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 477#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
480#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 478#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
481#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ 479#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
482#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 480#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
483#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ 481#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
484#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 482#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
485#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 483#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
486#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 484#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
487#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 485#define PCI_EXP_DEVCAP 4 /* Device capabilities */
488#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ 486#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
489#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ 487#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
@@ -622,8 +620,8 @@
622#define PCI_EXP_RTCAP 30 /* Root Capabilities */ 620#define PCI_EXP_RTCAP 30 /* Root Capabilities */
623#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 621#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
624#define PCI_EXP_RTSTA 32 /* Root Status */ 622#define PCI_EXP_RTSTA 32 /* Root Status */
625#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 623#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
626#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 624#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
627/* 625/*
628 * The Device Capabilities 2, Device Status 2, Device Control 2, 626 * The Device Capabilities 2, Device Status 2, Device Control 2,
629 * Link Capabilities 2, Link Status 2, Link Control 2, 627 * Link Capabilities 2, Link Status 2, Link Control 2,
@@ -643,13 +641,13 @@
643#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 641#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
644#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 642#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
645#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 643#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
646#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ 644#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
647#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 645#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
648#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 646#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
649#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ 647#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
650#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 648#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
651#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ 649#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
652#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ 650#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
653#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 651#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
654#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 652#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
655#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 653#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
@@ -665,11 +663,11 @@
665#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ 663#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
666#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 664#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
667#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 665#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
668#define PCI_EXP_LNKCTL2_TLS 0x000f 666#define PCI_EXP_LNKCTL2_TLS 0x000f
669#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 667#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
670#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 668#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
671#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 669#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
672#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 670#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
673#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ 671#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
674#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ 672#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
675#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ 673#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
@@ -758,18 +756,18 @@
758#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 756#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
759#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 757#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
760#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 758#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
761#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ 759#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
762#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ 760#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
763#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ 761#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
764#define PCI_ERR_ROOT_STATUS 48 762#define PCI_ERR_ROOT_STATUS 48
765#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 763#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
766#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ 764#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
767#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ 765#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
768#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ 766#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
769#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ 767#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
770#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 768#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
771#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 769#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
772#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ 770#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
773#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ 771#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
774 772
775/* Virtual Channel */ 773/* Virtual Channel */
@@ -881,12 +879,12 @@
881 879
882/* Page Request Interface */ 880/* Page Request Interface */
883#define PCI_PRI_CTRL 0x04 /* PRI control register */ 881#define PCI_PRI_CTRL 0x04 /* PRI control register */
884#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ 882#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
885#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ 883#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
886#define PCI_PRI_STATUS 0x06 /* PRI status register */ 884#define PCI_PRI_STATUS 0x06 /* PRI status register */
887#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ 885#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
888#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ 886#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
889#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ 887#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
890#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ 888#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
891#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 889#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
892#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 890#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
@@ -904,16 +902,16 @@
904 902
905/* Single Root I/O Virtualization */ 903/* Single Root I/O Virtualization */
906#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 904#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
907#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 905#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
908#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 906#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
909#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 907#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
910#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 908#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
911#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 909#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
912#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 910#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
913#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 911#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
914#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 912#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
915#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 913#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
916#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 914#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
917#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 915#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
918#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 916#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
919#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 917#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
@@ -943,13 +941,13 @@
943 941
944/* Access Control Service */ 942/* Access Control Service */
945#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 943#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
946#define PCI_ACS_SV 0x01 /* Source Validation */ 944#define PCI_ACS_SV 0x0001 /* Source Validation */
947#define PCI_ACS_TB 0x02 /* Translation Blocking */ 945#define PCI_ACS_TB 0x0002 /* Translation Blocking */
948#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ 946#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
949#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ 947#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
950#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ 948#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
951#define PCI_ACS_EC 0x20 /* P2P Egress Control */ 949#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
952#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ 950#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
953#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ 951#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
954#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 952#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
955#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 953#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
@@ -999,9 +997,9 @@
999#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ 997#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
1000 998
1001#define PCI_EXP_DPC_CTL 6 /* DPC control */ 999#define PCI_EXP_DPC_CTL 6 /* DPC control */
1002#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ 1000#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
1003#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ 1001#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
1004#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ 1002#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
1005 1003
1006#define PCI_EXP_DPC_STATUS 8 /* DPC Status */ 1004#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
1007#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ 1005#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 18:14:23 -0500