Merge tag 'pci-v4.20-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:

 - Fix a link speed checking interface that broke PCIe gen3 cards in
   gen1 slots (Mikulas Patocka)

 - Fix an imx6 link training error (Trent Piepho)

 - Fix a layerscape outbound window accessor calling error (Hou
   Zhiqiang)

 - Fix a DesignWare endpoint MSI-X address calculation error (Gustavo
   Pimentel)

* tag 'pci-v4.20-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: Fix incorrect value returned from pcie_get_speed_cap()
  PCI: dwc: Fix MSI-X EP framework address calculation bug
  PCI: layerscape: Fix wrong invocation of outbound window disable accessor
  PCI: imx6: Fix link training status detection in link up check

4 files changed, 13 insertions, 24 deletions

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 2cbef2d7c207..88af6bff945f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -81,8 +81,6 @@ struct imx6_pcie {
 #define PCIE_PL_PFLR_FORCE_LINK                 (1 << 15)
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
-#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP          (1 << 4)
 
 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 #define PCIE_PHY_CTRL_DATA_LOC 0
@@ -711,12 +709,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp)
         return 0;
 }
 
-static int imx6_pcie_link_up(struct dw_pcie *pci)
-{
-        return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
-                        PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
-}
-
 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
         .host_init = imx6_pcie_host_init,
 };
@@ -749,7 +741,7 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
 }
 
 static const struct dw_pcie_ops dw_pcie_ops = {
-        .link_up = imx6_pcie_link_up,
+        /* No special ops needed, but pcie-designware still expects this struct */
 };
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index 3724d3ef7008..7aa9a82b7ebd 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -88,7 +88,7 @@ static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
         int i;
 
         for (i = 0; i < PCIE_IATU_NUM; i++)
-                dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+                dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND);
 }
 
 static int ls1021_pcie_link_up(struct dw_pcie *pci)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1e7b02221eac..de8635af4cde 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -440,7 +440,6 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
         tbl_offset = dw_pcie_readl_dbi(pci, reg);
         bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
         tbl_offset &= PCI_MSIX_TABLE_OFFSET;
-        tbl_offset >>= 3;
 
         reg = PCI_BASE_ADDRESS_0 + (4 * bir);
         bar_addr_upper = 0;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d068f11d08a7..c9d8e3c837de 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5556,9 +5556,13 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
         u32 lnkcap2, lnkcap;
 
         /*
-         * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
-         * Speeds Vector in Link Capabilities 2 when supported, falling
-         * back to Max Link Speed in Link Capabilities otherwise.
+         * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18.  The
+         * implementation note there recommends using the Supported Link
+         * Speeds Vector in Link Capabilities 2 when supported.
+         *
+         * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
+         * should use the Supported Link Speeds field in Link Capabilities,
+         * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
          */
         pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
         if (lnkcap2) { /* PCIe r3.0-compliant */
@@ -5574,16 +5578,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
         }
 
         pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
-        if (lnkcap) {
-                if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
-                        return PCIE_SPEED_16_0GT;
-                else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
-                        return PCIE_SPEED_8_0GT;
-                else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
-                        return PCIE_SPEED_5_0GT;
-                else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
-                        return PCIE_SPEED_2_5GT;
-        }
+        if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
+                return PCIE_SPEED_5_0GT;
+        else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
+                return PCIE_SPEED_2_5GT;
 
         return PCI_SPEED_UNKNOWN;
 }