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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2018-08-27 14:54:35 -0400
committerSimon Horman <horms+renesas@verge.net.au>2018-09-13 03:47:45 -0400
commitc6eb20473f0b296c671dc6f7a7766ea6bedf2d59 (patch)
treefcc5d1f7d9359346631e3c47afcd63f4a10544b5
parentffa967e24c5817b48a3d5ecea2c12b9cdd807f0c (diff)
arm64: dts: renesas: condor: add PCIe support
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor board. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-condor.dts12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 59db4c152fb8..fe2e2c051cc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
223 status = "okay"; 223 status = "okay";
224}; 224};
225 225
226&pciec {
227 status = "okay";
228};
229
230&pcie_bus_clk {
231 clock-frequency = <100000000>;
232};
233
234&pcie_phy {
235 status = "okay";
236};
237
226&pfc { 238&pfc {
227 avb_pins: avb { 239 avb_pins: avb {
228 groups = "avb_mdio", "avb_rgmii"; 240 groups = "avb_mdio", "avb_rgmii";