diff options
author | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-30 15:32:03 -0500 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-30 15:32:03 -0500 |
commit | c6bb9cece632f4cad804b3b574364bb68a4c363b (patch) | |
tree | 11282181bbf244bdabd3a45509ea39766b3f1d83 | |
parent | c21ac06648a7a9985fa81a53ba3a65569a1de388 (diff) | |
parent | 167af5ef2cdba14ff14a13c91e5532ed479083d8 (diff) |
Merge branch 'for-4.4-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm into clk-fixes
Pull TI clock driver fixes from Tero Kristo:
* 'for-4.4-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm:
clk: ti: drop locking code from mux/divider drivers
clk: ti816x: Add missing dmtimer clkdev entries
clk: ti: fapll: fix wrong do_div() usage
clk: ti: clkt_dpll: fix wrong do_div() usage
-rw-r--r-- | drivers/clk/ti/clk-816x.c | 2 | ||||
-rw-r--r-- | drivers/clk/ti/clkt_dpll.c | 4 | ||||
-rw-r--r-- | drivers/clk/ti/divider.c | 16 | ||||
-rw-r--r-- | drivers/clk/ti/fapll.c | 4 | ||||
-rw-r--r-- | drivers/clk/ti/mux.c | 15 |
5 files changed, 12 insertions, 29 deletions
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 1dfad0c712cd..2a5d84fdddc5 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c | |||
@@ -20,6 +20,8 @@ static struct ti_dt_clk dm816x_clks[] = { | |||
20 | DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), | 20 | DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), |
21 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), | 21 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), |
22 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), | 22 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), |
23 | DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), | ||
24 | DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), | ||
23 | DT_CLK(NULL, "mpu_ck", "mpu_ck"), | 25 | DT_CLK(NULL, "mpu_ck", "mpu_ck"), |
24 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), | 26 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), |
25 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), | 27 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), |
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index 9023ca9caf84..b5cc6f66ae5d 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c | |||
@@ -240,7 +240,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) | |||
240 | */ | 240 | */ |
241 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | 241 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) |
242 | { | 242 | { |
243 | long long dpll_clk; | 243 | u64 dpll_clk; |
244 | u32 dpll_mult, dpll_div, v; | 244 | u32 dpll_mult, dpll_div, v; |
245 | struct dpll_data *dd; | 245 | struct dpll_data *dd; |
246 | 246 | ||
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | |||
262 | dpll_div = v & dd->div1_mask; | 262 | dpll_div = v & dd->div1_mask; |
263 | dpll_div >>= __ffs(dd->div1_mask); | 263 | dpll_div >>= __ffs(dd->div1_mask); |
264 | 264 | ||
265 | dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult; | 265 | dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult; |
266 | do_div(dpll_clk, dpll_div + 1); | 266 | do_div(dpll_clk, dpll_div + 1); |
267 | 267 | ||
268 | return dpll_clk; | 268 | return dpll_clk; |
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 5b1726829e6d..df2558350fc1 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c | |||
@@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
214 | { | 214 | { |
215 | struct clk_divider *divider; | 215 | struct clk_divider *divider; |
216 | unsigned int div, value; | 216 | unsigned int div, value; |
217 | unsigned long flags = 0; | ||
218 | u32 val; | 217 | u32 val; |
219 | 218 | ||
220 | if (!hw || !rate) | 219 | if (!hw || !rate) |
@@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
228 | if (value > div_mask(divider)) | 227 | if (value > div_mask(divider)) |
229 | value = div_mask(divider); | 228 | value = div_mask(divider); |
230 | 229 | ||
231 | if (divider->lock) | ||
232 | spin_lock_irqsave(divider->lock, flags); | ||
233 | |||
234 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { | 230 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
235 | val = div_mask(divider) << (divider->shift + 16); | 231 | val = div_mask(divider) << (divider->shift + 16); |
236 | } else { | 232 | } else { |
@@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
240 | val |= value << divider->shift; | 236 | val |= value << divider->shift; |
241 | ti_clk_ll_ops->clk_writel(val, divider->reg); | 237 | ti_clk_ll_ops->clk_writel(val, divider->reg); |
242 | 238 | ||
243 | if (divider->lock) | ||
244 | spin_unlock_irqrestore(divider->lock, flags); | ||
245 | |||
246 | return 0; | 239 | return 0; |
247 | } | 240 | } |
248 | 241 | ||
@@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
256 | const char *parent_name, | 249 | const char *parent_name, |
257 | unsigned long flags, void __iomem *reg, | 250 | unsigned long flags, void __iomem *reg, |
258 | u8 shift, u8 width, u8 clk_divider_flags, | 251 | u8 shift, u8 width, u8 clk_divider_flags, |
259 | const struct clk_div_table *table, | 252 | const struct clk_div_table *table) |
260 | spinlock_t *lock) | ||
261 | { | 253 | { |
262 | struct clk_divider *div; | 254 | struct clk_divider *div; |
263 | struct clk *clk; | 255 | struct clk *clk; |
@@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
288 | div->shift = shift; | 280 | div->shift = shift; |
289 | div->width = width; | 281 | div->width = width; |
290 | div->flags = clk_divider_flags; | 282 | div->flags = clk_divider_flags; |
291 | div->lock = lock; | ||
292 | div->hw.init = &init; | 283 | div->hw.init = &init; |
293 | div->table = table; | 284 | div->table = table; |
294 | 285 | ||
@@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) | |||
421 | 412 | ||
422 | clk = _register_divider(NULL, setup->name, div->parent, | 413 | clk = _register_divider(NULL, setup->name, div->parent, |
423 | flags, (void __iomem *)reg, div->bit_shift, | 414 | flags, (void __iomem *)reg, div->bit_shift, |
424 | width, div_flags, table, NULL); | 415 | width, div_flags, table); |
425 | 416 | ||
426 | if (IS_ERR(clk)) | 417 | if (IS_ERR(clk)) |
427 | kfree(table); | 418 | kfree(table); |
@@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) | |||
584 | goto cleanup; | 575 | goto cleanup; |
585 | 576 | ||
586 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, | 577 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, |
587 | shift, width, clk_divider_flags, table, | 578 | shift, width, clk_divider_flags, table); |
588 | NULL); | ||
589 | 579 | ||
590 | if (!IS_ERR(clk)) { | 580 | if (!IS_ERR(clk)) { |
591 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 581 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index f4b2e9888bdf..66a0d0ed8b55 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c | |||
@@ -168,7 +168,7 @@ static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, | |||
168 | { | 168 | { |
169 | struct fapll_data *fd = to_fapll(hw); | 169 | struct fapll_data *fd = to_fapll(hw); |
170 | u32 fapll_n, fapll_p, v; | 170 | u32 fapll_n, fapll_p, v; |
171 | long long rate; | 171 | u64 rate; |
172 | 172 | ||
173 | if (ti_fapll_clock_is_bypass(fd)) | 173 | if (ti_fapll_clock_is_bypass(fd)) |
174 | return parent_rate; | 174 | return parent_rate; |
@@ -314,7 +314,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, | |||
314 | { | 314 | { |
315 | struct fapll_synth *synth = to_synth(hw); | 315 | struct fapll_synth *synth = to_synth(hw); |
316 | u32 synth_div_m; | 316 | u32 synth_div_m; |
317 | long long rate; | 317 | u64 rate; |
318 | 318 | ||
319 | /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ | 319 | /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ |
320 | if (!synth->div) | 320 | if (!synth->div) |
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 69f08a1d047d..dab9ba88b9d6 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c | |||
@@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
69 | { | 69 | { |
70 | struct clk_mux *mux = to_clk_mux(hw); | 70 | struct clk_mux *mux = to_clk_mux(hw); |
71 | u32 val; | 71 | u32 val; |
72 | unsigned long flags = 0; | ||
73 | 72 | ||
74 | if (mux->table) { | 73 | if (mux->table) { |
75 | index = mux->table[index]; | 74 | index = mux->table[index]; |
@@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
81 | index++; | 80 | index++; |
82 | } | 81 | } |
83 | 82 | ||
84 | if (mux->lock) | ||
85 | spin_lock_irqsave(mux->lock, flags); | ||
86 | |||
87 | if (mux->flags & CLK_MUX_HIWORD_MASK) { | 83 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
88 | val = mux->mask << (mux->shift + 16); | 84 | val = mux->mask << (mux->shift + 16); |
89 | } else { | 85 | } else { |
@@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
93 | val |= index << mux->shift; | 89 | val |= index << mux->shift; |
94 | ti_clk_ll_ops->clk_writel(val, mux->reg); | 90 | ti_clk_ll_ops->clk_writel(val, mux->reg); |
95 | 91 | ||
96 | if (mux->lock) | ||
97 | spin_unlock_irqrestore(mux->lock, flags); | ||
98 | |||
99 | return 0; | 92 | return 0; |
100 | } | 93 | } |
101 | 94 | ||
@@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
109 | const char **parent_names, u8 num_parents, | 102 | const char **parent_names, u8 num_parents, |
110 | unsigned long flags, void __iomem *reg, | 103 | unsigned long flags, void __iomem *reg, |
111 | u8 shift, u32 mask, u8 clk_mux_flags, | 104 | u8 shift, u32 mask, u8 clk_mux_flags, |
112 | u32 *table, spinlock_t *lock) | 105 | u32 *table) |
113 | { | 106 | { |
114 | struct clk_mux *mux; | 107 | struct clk_mux *mux; |
115 | struct clk *clk; | 108 | struct clk *clk; |
@@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
133 | mux->shift = shift; | 126 | mux->shift = shift; |
134 | mux->mask = mask; | 127 | mux->mask = mask; |
135 | mux->flags = clk_mux_flags; | 128 | mux->flags = clk_mux_flags; |
136 | mux->lock = lock; | ||
137 | mux->table = table; | 129 | mux->table = table; |
138 | mux->hw.init = &init; | 130 | mux->hw.init = &init; |
139 | 131 | ||
@@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) | |||
175 | 167 | ||
176 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, | 168 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, |
177 | flags, (void __iomem *)reg, mux->bit_shift, mask, | 169 | flags, (void __iomem *)reg, mux->bit_shift, mask, |
178 | mux_flags, NULL, NULL); | 170 | mux_flags, NULL); |
179 | } | 171 | } |
180 | 172 | ||
181 | /** | 173 | /** |
@@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node) | |||
227 | mask = (1 << fls(mask)) - 1; | 219 | mask = (1 << fls(mask)) - 1; |
228 | 220 | ||
229 | clk = _register_mux(NULL, node->name, parent_names, num_parents, | 221 | clk = _register_mux(NULL, node->name, parent_names, num_parents, |
230 | flags, reg, shift, mask, clk_mux_flags, NULL, | 222 | flags, reg, shift, mask, clk_mux_flags, NULL); |
231 | NULL); | ||
232 | 223 | ||
233 | if (!IS_ERR(clk)) | 224 | if (!IS_ERR(clk)) |
234 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 225 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |