diff options
author | Thierry Reding <treding@nvidia.com> | 2017-08-30 06:42:34 -0400 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 07:06:44 -0500 |
commit | c641ec6eab8587a78160d37f085a5ed6e542ca88 (patch) | |
tree | d7454e767b570258e53a096aae9d90db778ed7ea | |
parent | 5be2255676bf2bc69170f05cfe15f771e5aeef24 (diff) |
soc/tegra: pmc: Consolidate Tegra186 support
Move Tegra186 support to the consolidated PMC driver to reduce some of
the duplication and also gain I/O pad functionality on the new SoC as a
side-effect.
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | drivers/soc/tegra/Kconfig | 5 | ||||
-rw-r--r-- | drivers/soc/tegra/Makefile | 1 | ||||
-rw-r--r-- | drivers/soc/tegra/pmc-tegra186.c | 169 | ||||
-rw-r--r-- | drivers/soc/tegra/pmc.c | 131 | ||||
-rw-r--r-- | include/soc/tegra/pmc.h | 12 |
5 files changed, 143 insertions, 175 deletions
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index e9e277178c94..89ebe22a3e27 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig | |||
@@ -95,7 +95,7 @@ config ARCH_TEGRA_186_SOC | |||
95 | select TEGRA_BPMP | 95 | select TEGRA_BPMP |
96 | select TEGRA_HSP_MBOX | 96 | select TEGRA_HSP_MBOX |
97 | select TEGRA_IVC | 97 | select TEGRA_IVC |
98 | select SOC_TEGRA_PMC_TEGRA186 | 98 | select SOC_TEGRA_PMC |
99 | help | 99 | help |
100 | Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a | 100 | Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a |
101 | combination of Denver and Cortex-A57 CPU cores and a GPU based on | 101 | combination of Denver and Cortex-A57 CPU cores and a GPU based on |
@@ -118,9 +118,6 @@ config SOC_TEGRA_FLOWCTRL | |||
118 | config SOC_TEGRA_PMC | 118 | config SOC_TEGRA_PMC |
119 | bool | 119 | bool |
120 | 120 | ||
121 | config SOC_TEGRA_PMC_TEGRA186 | ||
122 | bool | ||
123 | |||
124 | config SOC_TEGRA_POWERGATE_BPMP | 121 | config SOC_TEGRA_POWERGATE_BPMP |
125 | def_bool y | 122 | def_bool y |
126 | depends on PM_GENERIC_DOMAINS | 123 | depends on PM_GENERIC_DOMAINS |
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index 482e108d28aa..902759fe5f4d 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile | |||
@@ -4,5 +4,4 @@ obj-y += fuse/ | |||
4 | obj-y += common.o | 4 | obj-y += common.o |
5 | obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o | 5 | obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o |
6 | obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o | 6 | obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o |
7 | obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o | ||
8 | obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o | 7 | obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o |
diff --git a/drivers/soc/tegra/pmc-tegra186.c b/drivers/soc/tegra/pmc-tegra186.c deleted file mode 100644 index 6f5c6f98ba92..000000000000 --- a/drivers/soc/tegra/pmc-tegra186.c +++ /dev/null | |||
@@ -1,169 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #define pr_fmt(fmt) "tegra-pmc: " fmt | ||
15 | |||
16 | #include <linux/io.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/of.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/reboot.h> | ||
21 | |||
22 | #include <asm/system_misc.h> | ||
23 | |||
24 | #define PMC_CNTRL 0x000 | ||
25 | #define PMC_CNTRL_MAIN_RST BIT(4) | ||
26 | |||
27 | #define PMC_RST_STATUS 0x070 | ||
28 | |||
29 | #define WAKE_AOWAKE_CTRL 0x4f4 | ||
30 | #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) | ||
31 | |||
32 | #define SCRATCH_SCRATCH0 0x2000 | ||
33 | #define SCRATCH_SCRATCH0_MODE_RECOVERY BIT(31) | ||
34 | #define SCRATCH_SCRATCH0_MODE_BOOTLOADER BIT(30) | ||
35 | #define SCRATCH_SCRATCH0_MODE_RCM BIT(1) | ||
36 | #define SCRATCH_SCRATCH0_MODE_MASK (SCRATCH_SCRATCH0_MODE_RECOVERY | \ | ||
37 | SCRATCH_SCRATCH0_MODE_BOOTLOADER | \ | ||
38 | SCRATCH_SCRATCH0_MODE_RCM) | ||
39 | |||
40 | struct tegra_pmc { | ||
41 | struct device *dev; | ||
42 | void __iomem *regs; | ||
43 | void __iomem *wake; | ||
44 | void __iomem *aotag; | ||
45 | void __iomem *scratch; | ||
46 | |||
47 | void (*system_restart)(enum reboot_mode mode, const char *cmd); | ||
48 | struct notifier_block restart; | ||
49 | }; | ||
50 | |||
51 | static int tegra186_pmc_restart_notify(struct notifier_block *nb, | ||
52 | unsigned long action, | ||
53 | void *data) | ||
54 | { | ||
55 | struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, restart); | ||
56 | const char *cmd = data; | ||
57 | u32 value; | ||
58 | |||
59 | value = readl(pmc->scratch + SCRATCH_SCRATCH0); | ||
60 | value &= ~SCRATCH_SCRATCH0_MODE_MASK; | ||
61 | |||
62 | if (cmd) { | ||
63 | if (strcmp(cmd, "recovery") == 0) | ||
64 | value |= SCRATCH_SCRATCH0_MODE_RECOVERY; | ||
65 | |||
66 | if (strcmp(cmd, "bootloader") == 0) | ||
67 | value |= SCRATCH_SCRATCH0_MODE_BOOTLOADER; | ||
68 | |||
69 | if (strcmp(cmd, "forced-recovery") == 0) | ||
70 | value |= SCRATCH_SCRATCH0_MODE_RCM; | ||
71 | } | ||
72 | |||
73 | writel(value, pmc->scratch + SCRATCH_SCRATCH0); | ||
74 | |||
75 | /* | ||
76 | * If available, call the system restart implementation that was | ||
77 | * registered earlier (typically PSCI). | ||
78 | */ | ||
79 | if (pmc->system_restart) { | ||
80 | pmc->system_restart(reboot_mode, cmd); | ||
81 | return NOTIFY_DONE; | ||
82 | } | ||
83 | |||
84 | /* reset everything but SCRATCH0_SCRATCH0 and PMC_RST_STATUS */ | ||
85 | value = readl(pmc->regs + PMC_CNTRL); | ||
86 | value |= PMC_CNTRL_MAIN_RST; | ||
87 | writel(value, pmc->regs + PMC_CNTRL); | ||
88 | |||
89 | return NOTIFY_DONE; | ||
90 | } | ||
91 | |||
92 | static int tegra186_pmc_setup(struct tegra_pmc *pmc) | ||
93 | { | ||
94 | struct device_node *np = pmc->dev->of_node; | ||
95 | bool invert; | ||
96 | u32 value; | ||
97 | |||
98 | invert = of_property_read_bool(np, "nvidia,invert-interrupt"); | ||
99 | |||
100 | value = readl(pmc->wake + WAKE_AOWAKE_CTRL); | ||
101 | |||
102 | if (invert) | ||
103 | value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; | ||
104 | else | ||
105 | value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; | ||
106 | |||
107 | writel(value, pmc->wake + WAKE_AOWAKE_CTRL); | ||
108 | |||
109 | /* | ||
110 | * We need to hook any system restart implementation registered | ||
111 | * previously so we can write SCRATCH_SCRATCH0 before reset. | ||
112 | */ | ||
113 | pmc->system_restart = arm_pm_restart; | ||
114 | arm_pm_restart = NULL; | ||
115 | |||
116 | pmc->restart.notifier_call = tegra186_pmc_restart_notify; | ||
117 | pmc->restart.priority = 128; | ||
118 | |||
119 | return register_restart_handler(&pmc->restart); | ||
120 | } | ||
121 | |||
122 | static int tegra186_pmc_probe(struct platform_device *pdev) | ||
123 | { | ||
124 | struct tegra_pmc *pmc; | ||
125 | struct resource *res; | ||
126 | |||
127 | pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL); | ||
128 | if (!pmc) | ||
129 | return -ENOMEM; | ||
130 | |||
131 | pmc->dev = &pdev->dev; | ||
132 | |||
133 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmc"); | ||
134 | pmc->regs = devm_ioremap_resource(&pdev->dev, res); | ||
135 | if (IS_ERR(pmc->regs)) | ||
136 | return PTR_ERR(pmc->regs); | ||
137 | |||
138 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); | ||
139 | pmc->wake = devm_ioremap_resource(&pdev->dev, res); | ||
140 | if (IS_ERR(pmc->wake)) | ||
141 | return PTR_ERR(pmc->wake); | ||
142 | |||
143 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); | ||
144 | pmc->aotag = devm_ioremap_resource(&pdev->dev, res); | ||
145 | if (IS_ERR(pmc->aotag)) | ||
146 | return PTR_ERR(pmc->aotag); | ||
147 | |||
148 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); | ||
149 | pmc->scratch = devm_ioremap_resource(&pdev->dev, res); | ||
150 | if (IS_ERR(pmc->scratch)) | ||
151 | return PTR_ERR(pmc->scratch); | ||
152 | |||
153 | return tegra186_pmc_setup(pmc); | ||
154 | } | ||
155 | |||
156 | static const struct of_device_id tegra186_pmc_of_match[] = { | ||
157 | { .compatible = "nvidia,tegra186-pmc" }, | ||
158 | { /* sentinel */ } | ||
159 | }; | ||
160 | MODULE_DEVICE_TABLE(of, tegra186_pmc_of_match); | ||
161 | |||
162 | static struct platform_driver tegra186_pmc_driver = { | ||
163 | .driver = { | ||
164 | .name = "tegra186-pmc", | ||
165 | .of_match_table = tegra186_pmc_of_match, | ||
166 | }, | ||
167 | .probe = tegra186_pmc_probe, | ||
168 | }; | ||
169 | builtin_platform_driver(tegra186_pmc_driver); | ||
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 363b4b9c3aaf..ce62a47a6647 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c | |||
@@ -117,6 +117,10 @@ | |||
117 | 117 | ||
118 | #define GPU_RG_CNTRL 0x2d4 | 118 | #define GPU_RG_CNTRL 0x2d4 |
119 | 119 | ||
120 | /* Tegra186 and later */ | ||
121 | #define WAKE_AOWAKE_CTRL 0x4f4 | ||
122 | #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) | ||
123 | |||
120 | struct tegra_powergate { | 124 | struct tegra_powergate { |
121 | struct generic_pm_domain genpd; | 125 | struct generic_pm_domain genpd; |
122 | struct tegra_pmc *pmc; | 126 | struct tegra_pmc *pmc; |
@@ -186,6 +190,8 @@ struct tegra_pmc_soc { | |||
186 | struct tegra_pmc { | 190 | struct tegra_pmc { |
187 | struct device *dev; | 191 | struct device *dev; |
188 | void __iomem *base; | 192 | void __iomem *base; |
193 | void __iomem *wake; | ||
194 | void __iomem *aotag; | ||
189 | void __iomem *scratch; | 195 | void __iomem *scratch; |
190 | struct clk *clk; | 196 | struct clk *clk; |
191 | struct dentry *debugfs; | 197 | struct dentry *debugfs; |
@@ -1408,7 +1414,32 @@ static int tegra_pmc_probe(struct platform_device *pdev) | |||
1408 | if (IS_ERR(base)) | 1414 | if (IS_ERR(base)) |
1409 | return PTR_ERR(base); | 1415 | return PTR_ERR(base); |
1410 | 1416 | ||
1411 | pmc->scratch = base; | 1417 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); |
1418 | if (res) { | ||
1419 | pmc->wake = devm_ioremap_resource(&pdev->dev, res); | ||
1420 | if (IS_ERR(pmc->wake)) | ||
1421 | return PTR_ERR(pmc->wake); | ||
1422 | } else { | ||
1423 | pmc->wake = base; | ||
1424 | } | ||
1425 | |||
1426 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); | ||
1427 | if (res) { | ||
1428 | pmc->aotag = devm_ioremap_resource(&pdev->dev, res); | ||
1429 | if (IS_ERR(pmc->aotag)) | ||
1430 | return PTR_ERR(pmc->aotag); | ||
1431 | } else { | ||
1432 | pmc->aotag = base; | ||
1433 | } | ||
1434 | |||
1435 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); | ||
1436 | if (res) { | ||
1437 | pmc->scratch = devm_ioremap_resource(&pdev->dev, res); | ||
1438 | if (IS_ERR(pmc->scratch)) | ||
1439 | return PTR_ERR(pmc->scratch); | ||
1440 | } else { | ||
1441 | pmc->scratch = base; | ||
1442 | } | ||
1412 | 1443 | ||
1413 | pmc->clk = devm_clk_get(&pdev->dev, "pclk"); | 1444 | pmc->clk = devm_clk_get(&pdev->dev, "pclk"); |
1414 | if (IS_ERR(pmc->clk)) { | 1445 | if (IS_ERR(pmc->clk)) { |
@@ -1791,7 +1822,105 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { | |||
1791 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, | 1822 | .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, |
1792 | }; | 1823 | }; |
1793 | 1824 | ||
1825 | static const struct tegra_io_pad_soc tegra186_io_pads[] = { | ||
1826 | { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, | ||
1827 | { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, | ||
1828 | { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, | ||
1829 | { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, | ||
1830 | { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, | ||
1831 | { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, | ||
1832 | { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, | ||
1833 | { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, | ||
1834 | { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, | ||
1835 | { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, | ||
1836 | { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, | ||
1837 | { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, | ||
1838 | { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, | ||
1839 | { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, | ||
1840 | { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, | ||
1841 | { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, | ||
1842 | { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, | ||
1843 | { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, | ||
1844 | { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, | ||
1845 | { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX }, | ||
1846 | { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, | ||
1847 | { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX }, | ||
1848 | { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX }, | ||
1849 | { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX }, | ||
1850 | { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX }, | ||
1851 | { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, | ||
1852 | { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, | ||
1853 | { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, | ||
1854 | { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, | ||
1855 | { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, | ||
1856 | { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, | ||
1857 | { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX }, | ||
1858 | { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, | ||
1859 | { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, | ||
1860 | { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, | ||
1861 | { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, | ||
1862 | { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, | ||
1863 | }; | ||
1864 | |||
1865 | static const struct tegra_pmc_regs tegra186_pmc_regs = { | ||
1866 | .scratch0 = 0x2000, | ||
1867 | .dpd_req = 0x74, | ||
1868 | .dpd_status = 0x78, | ||
1869 | .dpd2_req = 0x7c, | ||
1870 | .dpd2_status = 0x80, | ||
1871 | }; | ||
1872 | |||
1873 | static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, | ||
1874 | struct device_node *np, | ||
1875 | bool invert) | ||
1876 | { | ||
1877 | struct resource regs; | ||
1878 | void __iomem *wake; | ||
1879 | u32 value; | ||
1880 | int index; | ||
1881 | |||
1882 | index = of_property_match_string(np, "reg-names", "wake"); | ||
1883 | if (index < 0) { | ||
1884 | pr_err("failed to find PMC wake registers\n"); | ||
1885 | return; | ||
1886 | } | ||
1887 | |||
1888 | of_address_to_resource(np, index, ®s); | ||
1889 | |||
1890 | wake = ioremap_nocache(regs.start, resource_size(®s)); | ||
1891 | if (!wake) { | ||
1892 | pr_err("failed to map PMC wake registers\n"); | ||
1893 | return; | ||
1894 | } | ||
1895 | |||
1896 | value = readl(wake + WAKE_AOWAKE_CTRL); | ||
1897 | |||
1898 | if (invert) | ||
1899 | value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; | ||
1900 | else | ||
1901 | value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; | ||
1902 | |||
1903 | writel(value, wake + WAKE_AOWAKE_CTRL); | ||
1904 | |||
1905 | iounmap(wake); | ||
1906 | } | ||
1907 | |||
1908 | static const struct tegra_pmc_soc tegra186_pmc_soc = { | ||
1909 | .num_powergates = 0, | ||
1910 | .powergates = NULL, | ||
1911 | .num_cpu_powergates = 0, | ||
1912 | .cpu_powergates = NULL, | ||
1913 | .has_tsense_reset = false, | ||
1914 | .has_gpu_clamps = false, | ||
1915 | .num_io_pads = ARRAY_SIZE(tegra186_io_pads), | ||
1916 | .io_pads = tegra186_io_pads, | ||
1917 | .regs = &tegra186_pmc_regs, | ||
1918 | .init = NULL, | ||
1919 | .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, | ||
1920 | }; | ||
1921 | |||
1794 | static const struct of_device_id tegra_pmc_match[] = { | 1922 | static const struct of_device_id tegra_pmc_match[] = { |
1923 | { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, | ||
1795 | { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, | 1924 | { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, |
1796 | { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, | 1925 | { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, |
1797 | { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, | 1926 | { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, |
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 1c3982bc558f..c32bf91c23e6 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h | |||
@@ -83,6 +83,7 @@ enum tegra_io_pad { | |||
83 | TEGRA_IO_PAD_BB, | 83 | TEGRA_IO_PAD_BB, |
84 | TEGRA_IO_PAD_CAM, | 84 | TEGRA_IO_PAD_CAM, |
85 | TEGRA_IO_PAD_COMP, | 85 | TEGRA_IO_PAD_COMP, |
86 | TEGRA_IO_PAD_CONN, | ||
86 | TEGRA_IO_PAD_CSIA, | 87 | TEGRA_IO_PAD_CSIA, |
87 | TEGRA_IO_PAD_CSIB, | 88 | TEGRA_IO_PAD_CSIB, |
88 | TEGRA_IO_PAD_CSIC, | 89 | TEGRA_IO_PAD_CSIC, |
@@ -92,31 +93,42 @@ enum tegra_io_pad { | |||
92 | TEGRA_IO_PAD_DBG, | 93 | TEGRA_IO_PAD_DBG, |
93 | TEGRA_IO_PAD_DEBUG_NONAO, | 94 | TEGRA_IO_PAD_DEBUG_NONAO, |
94 | TEGRA_IO_PAD_DMIC, | 95 | TEGRA_IO_PAD_DMIC, |
96 | TEGRA_IO_PAD_DMIC_HV, | ||
95 | TEGRA_IO_PAD_DP, | 97 | TEGRA_IO_PAD_DP, |
96 | TEGRA_IO_PAD_DSI, | 98 | TEGRA_IO_PAD_DSI, |
97 | TEGRA_IO_PAD_DSIB, | 99 | TEGRA_IO_PAD_DSIB, |
98 | TEGRA_IO_PAD_DSIC, | 100 | TEGRA_IO_PAD_DSIC, |
99 | TEGRA_IO_PAD_DSID, | 101 | TEGRA_IO_PAD_DSID, |
102 | TEGRA_IO_PAD_EDP, | ||
100 | TEGRA_IO_PAD_EMMC, | 103 | TEGRA_IO_PAD_EMMC, |
101 | TEGRA_IO_PAD_EMMC2, | 104 | TEGRA_IO_PAD_EMMC2, |
102 | TEGRA_IO_PAD_GPIO, | 105 | TEGRA_IO_PAD_GPIO, |
103 | TEGRA_IO_PAD_HDMI, | 106 | TEGRA_IO_PAD_HDMI, |
107 | TEGRA_IO_PAD_HDMI_DP0, | ||
108 | TEGRA_IO_PAD_HDMI_DP1, | ||
104 | TEGRA_IO_PAD_HSIC, | 109 | TEGRA_IO_PAD_HSIC, |
105 | TEGRA_IO_PAD_HV, | 110 | TEGRA_IO_PAD_HV, |
106 | TEGRA_IO_PAD_LVDS, | 111 | TEGRA_IO_PAD_LVDS, |
107 | TEGRA_IO_PAD_MIPI_BIAS, | 112 | TEGRA_IO_PAD_MIPI_BIAS, |
108 | TEGRA_IO_PAD_NAND, | 113 | TEGRA_IO_PAD_NAND, |
109 | TEGRA_IO_PAD_PEX_BIAS, | 114 | TEGRA_IO_PAD_PEX_BIAS, |
115 | TEGRA_IO_PAD_PEX_CLK_BIAS, | ||
110 | TEGRA_IO_PAD_PEX_CLK1, | 116 | TEGRA_IO_PAD_PEX_CLK1, |
111 | TEGRA_IO_PAD_PEX_CLK2, | 117 | TEGRA_IO_PAD_PEX_CLK2, |
118 | TEGRA_IO_PAD_PEX_CLK3, | ||
112 | TEGRA_IO_PAD_PEX_CNTRL, | 119 | TEGRA_IO_PAD_PEX_CNTRL, |
113 | TEGRA_IO_PAD_SDMMC1, | 120 | TEGRA_IO_PAD_SDMMC1, |
121 | TEGRA_IO_PAD_SDMMC1_HV, | ||
122 | TEGRA_IO_PAD_SDMMC2, | ||
123 | TEGRA_IO_PAD_SDMMC2_HV, | ||
114 | TEGRA_IO_PAD_SDMMC3, | 124 | TEGRA_IO_PAD_SDMMC3, |
125 | TEGRA_IO_PAD_SDMMC3_HV, | ||
115 | TEGRA_IO_PAD_SDMMC4, | 126 | TEGRA_IO_PAD_SDMMC4, |
116 | TEGRA_IO_PAD_SPI, | 127 | TEGRA_IO_PAD_SPI, |
117 | TEGRA_IO_PAD_SPI_HV, | 128 | TEGRA_IO_PAD_SPI_HV, |
118 | TEGRA_IO_PAD_SYS_DDC, | 129 | TEGRA_IO_PAD_SYS_DDC, |
119 | TEGRA_IO_PAD_UART, | 130 | TEGRA_IO_PAD_UART, |
131 | TEGRA_IO_PAD_UFS, | ||
120 | TEGRA_IO_PAD_USB0, | 132 | TEGRA_IO_PAD_USB0, |
121 | TEGRA_IO_PAD_USB1, | 133 | TEGRA_IO_PAD_USB1, |
122 | TEGRA_IO_PAD_USB2, | 134 | TEGRA_IO_PAD_USB2, |