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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-10-16 05:41:19 -0400
committerGeert Uytterhoeven <geert+renesas@glider.be>2015-12-08 08:33:06 -0500
commitc5dae0df298120e0a331d749d77fd472c253b5b3 (patch)
treee020b6c7f0cfb17f4675a608297785da6e637424
parentf793d1e51705b276f083c1dc0dc75fb4cc4375c7 (diff)
clk: shmobile: r8a7795: Add new CPG/MSSR driver
Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software Reset driver, using the new CPG/MSSR driver core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/shmobile/Makefile2
-rw-r--r--drivers/clk/shmobile/r8a7795-cpg-mssr.c382
-rw-r--r--drivers/clk/shmobile/renesas-cpg-mssr.c6
-rw-r--r--drivers/clk/shmobile/renesas-cpg-mssr.h1
5 files changed, 392 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 820714c72d36..366350a4a1ee 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
69obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 69obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
70obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 70obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
71obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ 71obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
72obj-$(CONFIG_ARCH_RENESAS) += shmobile/
72obj-$(CONFIG_ARCH_SIRF) += sirf/ 73obj-$(CONFIG_ARCH_SIRF) += sirf/
73obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 74obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
74obj-$(CONFIG_PLAT_SPEAR) += spear/ 75obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 1eb947db6f59..7e2579b30326 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -8,4 +8,6 @@ obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o 8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o 9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o 10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
11obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
12 r8a7795-cpg-mssr.o clk-div6.o
11obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o 13obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
new file mode 100644
index 000000000000..57c413635d1a
--- /dev/null
+++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c
@@ -0,0 +1,382 @@
1/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2015 Glider bvba
5 *
6 * Based on clk-rcar-gen3.c
7 *
8 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <linux/bug.h>
16#include <linux/clk-provider.h>
17#include <linux/device.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/of.h>
23
24#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
25
26#include "renesas-cpg-mssr.h"
27
28
29enum clk_ids {
30 /* Core Clock Outputs exported to DT */
31 LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
32
33 /* External Input Clocks */
34 CLK_EXTAL,
35 CLK_EXTALR,
36
37 /* Internal Core Clocks */
38 CLK_MAIN,
39 CLK_PLL0,
40 CLK_PLL1,
41 CLK_PLL2,
42 CLK_PLL3,
43 CLK_PLL4,
44 CLK_PLL1_DIV2,
45 CLK_PLL1_DIV4,
46 CLK_S0,
47 CLK_S1,
48 CLK_S2,
49 CLK_S3,
50 CLK_SDSRC,
51 CLK_SSPSRC,
52
53 /* Module Clocks */
54 MOD_CLK_BASE
55};
56
57enum r8a7795_clk_types {
58 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
59 CLK_TYPE_GEN3_PLL0,
60 CLK_TYPE_GEN3_PLL1,
61 CLK_TYPE_GEN3_PLL2,
62 CLK_TYPE_GEN3_PLL3,
63 CLK_TYPE_GEN3_PLL4,
64};
65
66static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
67 /* External Clock Inputs */
68 DEF_INPUT("extal", CLK_EXTAL),
69 DEF_INPUT("extalr", CLK_EXTALR),
70
71 /* Internal Core Clocks */
72 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
73 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
74 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
75 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
76 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
77 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
78
79 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
80 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
81 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
82 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
83 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
84 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
85
86 /* Core Clock Outputs */
87 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
88 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
89 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
90 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
91 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
92 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
93 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
94 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
95 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
96 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
97 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
98 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
99 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
100 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
101 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
102 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
103 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
104
105 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
106 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
107};
108
109static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
110 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
111 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
112 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
113 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
114 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
115 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
116 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
117 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
118 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
119 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
120 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
121 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
122 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
123 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
124 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
125 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
126 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
127 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
128 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
129 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
130 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
131 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
132 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
133 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
134 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
135 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
136 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
137 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
138 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
139 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
140 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
141 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
142 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
143 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
144 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
145 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
146 DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
147 DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
148 DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
149 DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
150 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
151 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
152 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
153 DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
154 DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
155 DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
156 DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
157 DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
158 DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
159 DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
160 DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
161 DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
162 DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
163 DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
164 DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
165 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
166 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
167 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
168 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
169 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
170 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
171 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
172 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
173 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
174 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
175 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
176 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
177 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
178 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
179 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
180 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
181 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
182 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
183 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
184 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
185 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
186 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
187 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
188 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
189 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
190 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
191 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
192 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
193 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
194};
195
196static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
197 MOD_CLK_ID(408), /* INTC-AP (GIC) */
198};
199
200
201#define CPG_PLL0CR 0x00d8
202#define CPG_PLL2CR 0x002c
203#define CPG_PLL4CR 0x01f4
204
205/*
206 * CPG Clock Data
207 */
208
209/*
210 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
211 * 14 13 19 17 (MHz)
212 *-------------------------------------------------------------------
213 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
214 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
215 * 0 0 1 0 Prohibited setting
216 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
217 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
218 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
219 * 0 1 1 0 Prohibited setting
220 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
221 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
222 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
223 * 1 0 1 0 Prohibited setting
224 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
225 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
226 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
227 * 1 1 1 0 Prohibited setting
228 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
229 */
230#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
231 (((md) & BIT(13)) >> 11) | \
232 (((md) & BIT(19)) >> 18) | \
233 (((md) & BIT(17)) >> 17))
234
235struct cpg_pll_config {
236 unsigned int extal_div;
237 unsigned int pll1_mult;
238 unsigned int pll3_mult;
239};
240
241static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
242 /* EXTAL div PLL1 mult PLL3 mult */
243 { 1, 192, 192, },
244 { 1, 192, 128, },
245 { 0, /* Prohibited setting */ },
246 { 1, 192, 192, },
247 { 1, 160, 160, },
248 { 1, 160, 106, },
249 { 0, /* Prohibited setting */ },
250 { 1, 160, 160, },
251 { 1, 128, 128, },
252 { 1, 128, 84, },
253 { 0, /* Prohibited setting */ },
254 { 1, 128, 128, },
255 { 2, 192, 192, },
256 { 2, 192, 128, },
257 { 0, /* Prohibited setting */ },
258 { 2, 192, 192, },
259};
260
261static const struct cpg_pll_config *cpg_pll_config __initdata;
262
263static
264struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
265 const struct cpg_core_clk *core,
266 const struct cpg_mssr_info *info,
267 struct clk **clks,
268 void __iomem *base)
269{
270 const struct clk *parent;
271 unsigned int mult = 1;
272 unsigned int div = 1;
273 u32 value;
274
275 parent = clks[core->parent];
276 if (IS_ERR(parent))
277 return ERR_CAST(parent);
278
279 switch (core->type) {
280 case CLK_TYPE_GEN3_MAIN:
281 div = cpg_pll_config->extal_div;
282 break;
283
284 case CLK_TYPE_GEN3_PLL0:
285 /*
286 * PLL0 is a configurable multiplier clock. Register it as a
287 * fixed factor clock for now as there's no generic multiplier
288 * clock implementation and we currently have no need to change
289 * the multiplier value.
290 */
291 value = readl(base + CPG_PLL0CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2;
293 break;
294
295 case CLK_TYPE_GEN3_PLL1:
296 mult = cpg_pll_config->pll1_mult;
297 break;
298
299 case CLK_TYPE_GEN3_PLL2:
300 /*
301 * PLL2 is a configurable multiplier clock. Register it as a
302 * fixed factor clock for now as there's no generic multiplier
303 * clock implementation and we currently have no need to change
304 * the multiplier value.
305 */
306 value = readl(base + CPG_PLL2CR);
307 mult = (((value >> 24) & 0x7f) + 1) * 2;
308 break;
309
310 case CLK_TYPE_GEN3_PLL3:
311 mult = cpg_pll_config->pll3_mult;
312 break;
313
314 case CLK_TYPE_GEN3_PLL4:
315 /*
316 * PLL4 is a configurable multiplier clock. Register it as a
317 * fixed factor clock for now as there's no generic multiplier
318 * clock implementation and we currently have no need to change
319 * the multiplier value.
320 */
321 value = readl(base + CPG_PLL4CR);
322 mult = (((value >> 24) & 0x7f) + 1) * 2;
323 break;
324
325 default:
326 return ERR_PTR(-EINVAL);
327 }
328
329 return clk_register_fixed_factor(NULL, core->name,
330 __clk_get_name(parent), 0, mult, div);
331}
332
333/*
334 * Reset register definitions.
335 */
336#define MODEMR 0xe6160060
337
338static u32 rcar_gen3_read_mode_pins(void)
339{
340 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
341 u32 mode;
342
343 BUG_ON(!modemr);
344 mode = ioread32(modemr);
345 iounmap(modemr);
346
347 return mode;
348}
349
350static int __init r8a7795_cpg_mssr_init(struct device *dev)
351{
352 u32 cpg_mode = rcar_gen3_read_mode_pins();
353
354 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
355 if (!cpg_pll_config->extal_div) {
356 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
357 return -EINVAL;
358 }
359
360 return 0;
361}
362
363const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
364 /* Core Clocks */
365 .core_clks = r8a7795_core_clks,
366 .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
367 .last_dt_core_clk = LAST_DT_CORE_CLK,
368 .num_total_core_clks = MOD_CLK_BASE,
369
370 /* Module Clocks */
371 .mod_clks = r8a7795_mod_clks,
372 .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
373 .num_hw_mod_clks = 12 * 32,
374
375 /* Critical Module Clocks */
376 .crit_mod_clks = r8a7795_crit_mod_clks,
377 .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
378
379 /* Callbacks */
380 .init = r8a7795_cpg_mssr_init,
381 .cpg_clk_register = r8a7795_cpg_clk_register,
382};
diff --git a/drivers/clk/shmobile/renesas-cpg-mssr.c b/drivers/clk/shmobile/renesas-cpg-mssr.c
index 4e066110cb8a..9a4d888164bb 100644
--- a/drivers/clk/shmobile/renesas-cpg-mssr.c
+++ b/drivers/clk/shmobile/renesas-cpg-mssr.c
@@ -501,6 +501,12 @@ static inline int cpg_mssr_add_clk_domain(struct device *dev,
501 501
502 502
503static const struct of_device_id cpg_mssr_match[] = { 503static const struct of_device_id cpg_mssr_match[] = {
504#ifdef CONFIG_ARCH_R8A7795
505 {
506 .compatible = "renesas,r8a7795-cpg-mssr",
507 .data = &r8a7795_cpg_mssr_info,
508 },
509#endif
504 { /* sentinel */ } 510 { /* sentinel */ }
505}; 511};
506 512
diff --git a/drivers/clk/shmobile/renesas-cpg-mssr.h b/drivers/clk/shmobile/renesas-cpg-mssr.h
index e6d24875b56f..e09f03cbf086 100644
--- a/drivers/clk/shmobile/renesas-cpg-mssr.h
+++ b/drivers/clk/shmobile/renesas-cpg-mssr.h
@@ -128,4 +128,5 @@ struct cpg_mssr_info {
128 struct clk **clks, void __iomem *base); 128 struct clk **clks, void __iomem *base);
129}; 129};
130 130
131extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
131#endif 132#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 14:06:15 -0400