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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-03-10 07:15:21 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-17 17:30:19 -0400
commitc5da514588c48c99d9e0f4014348115496aef938 (patch)
tree3aa9c726bec0e87f018050efe1b2e948480f58f7
parent41659ab7935e53f3a094168c47000bbc33cf2690 (diff)
drm/i915: Remove debug prints from primary plane update funcs
These are now called from the plane commit hooks, so they really need to be fast or else we risk atomic update failures. So kill the debug prints which are slowing things down massively. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 75e8c8c93cec..d6c9fb417e05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2658,9 +2658,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2658 2658
2659 I915_WRITE(reg, dspcntr); 2659 I915_WRITE(reg, dspcntr);
2660 2660
2661 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2662 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2663 fb->pitches[0]);
2664 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2661 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2665 if (INTEL_INFO(dev)->gen >= 4) { 2662 if (INTEL_INFO(dev)->gen >= 4) {
2666 I915_WRITE(DSPSURF(plane), 2663 I915_WRITE(DSPSURF(plane),
@@ -2762,9 +2759,6 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 2759
2763 I915_WRITE(reg, dspcntr); 2760 I915_WRITE(reg, dspcntr);
2764 2761
2765 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2766 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2767 fb->pitches[0]);
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2762 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 I915_WRITE(DSPSURF(plane), 2763 I915_WRITE(DSPSURF(plane),
2770 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); 2764 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
@@ -2890,11 +2884,6 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
2890 2884
2891 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); 2885 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2892 2886
2893 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2894 i915_gem_obj_ggtt_offset(obj),
2895 x, y, fb->width, fb->height,
2896 fb->pitches[0]);
2897
2898 I915_WRITE(PLANE_POS(pipe, 0), 0); 2887 I915_WRITE(PLANE_POS(pipe, 0), 0);
2899 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); 2888 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2900 I915_WRITE(PLANE_SIZE(pipe, 0), 2889 I915_WRITE(PLANE_SIZE(pipe, 0),