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authorLinus Torvalds <torvalds@linux-foundation.org>2015-11-29 20:38:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-11-29 20:38:08 -0500
commitc5bc1c9305e87d84c20415cc5ed2d3944d5bad8d (patch)
tree91b35672d7419548d0c532e72eb09a1f2c82b9f4
parent818aba30b3a178b350b1d7bd12c3430fbf9c212f (diff)
parent8c14f72b57570d71afda03c5c51b06f0b4af4367 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull nouveau and radeon fixes from Dave Airlie: "Just some nouveau and radeon/amdgpu fixes. The nouveau fixes look large as the firmware context files are regenerated, but the actual change is quite small" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: make some dpm errors debug only drm/nouveau/volt/pwm/gk104: fix an off-by-one resulting in the voltage not being set drm/nouveau/nvif: allow userspace access to its own client object drm/nouveau/gr/gf100-: fix oops when calling zbc methods drm/nouveau/gr/gf117-: assume no PPC if NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK is zero drm/nouveau/gr/gf117-: read NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK from correct GPC drm/nouveau/gr/gf100-: split out per-gpc address calculation macro drm/nouveau/bios: return actual size of the buffer retrieved via _ROM drm/nouveau/instmem: protect instobj list with a spinlock drm/nouveau/pci: enable c800 magic for some unknown Samsung laptop drm/nouveau/pci: enable c800 magic for Clevo P157SM drm/radeon: make rv770_set_sw_state failures non-fatal drm/amdgpu: move dependency handling out of atomic section v2 drm/amdgpu: optimize scheduler fence handling drm/amdgpu: remove vm->mutex drm/amdgpu: add mutex for ba_va->valids/invalids drm/amdgpu: adapt vce session create interface changes drm/amdgpu: vce use multiple cache surface starting from stoney drm/amdgpu: reset vce trap interrupt flag
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c19
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c24
-rw-r--r--drivers/gpu/drm/amd/scheduler/gpu_scheduler.c122
-rw-r--r--drivers/gpu/drm/amd/scheduler/gpu_scheduler.h5
-rw-r--r--drivers/gpu/drm/amd/scheduler/sched_fence.c13
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.h4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_usif.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h344
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h344
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h344
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h308
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h474
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c2
-rw-r--r--drivers/gpu/drm/radeon/rv730_dpm.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c4
27 files changed, 1093 insertions, 993 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 306f75700bf8..251b14736de9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -496,6 +496,7 @@ struct amdgpu_bo_va_mapping {
496 496
497/* bo virtual addresses in a specific vm */ 497/* bo virtual addresses in a specific vm */
498struct amdgpu_bo_va { 498struct amdgpu_bo_va {
499 struct mutex mutex;
499 /* protected by bo being reserved */ 500 /* protected by bo being reserved */
500 struct list_head bo_list; 501 struct list_head bo_list;
501 struct fence *last_pt_update; 502 struct fence *last_pt_update;
@@ -928,8 +929,6 @@ struct amdgpu_vm_id {
928}; 929};
929 930
930struct amdgpu_vm { 931struct amdgpu_vm {
931 struct mutex mutex;
932
933 struct rb_root va; 932 struct rb_root va;
934 933
935 /* protecting invalidated */ 934 /* protecting invalidated */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 3afcf0237c25..1d44d508d4d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -784,8 +784,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
784{ 784{
785 struct amdgpu_device *adev = dev->dev_private; 785 struct amdgpu_device *adev = dev->dev_private;
786 union drm_amdgpu_cs *cs = data; 786 union drm_amdgpu_cs *cs = data;
787 struct amdgpu_fpriv *fpriv = filp->driver_priv;
788 struct amdgpu_vm *vm = &fpriv->vm;
789 struct amdgpu_cs_parser parser = {}; 787 struct amdgpu_cs_parser parser = {};
790 bool reserved_buffers = false; 788 bool reserved_buffers = false;
791 int i, r; 789 int i, r;
@@ -803,7 +801,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
803 r = amdgpu_cs_handle_lockup(adev, r); 801 r = amdgpu_cs_handle_lockup(adev, r);
804 return r; 802 return r;
805 } 803 }
806 mutex_lock(&vm->mutex);
807 r = amdgpu_cs_parser_relocs(&parser); 804 r = amdgpu_cs_parser_relocs(&parser);
808 if (r == -ENOMEM) 805 if (r == -ENOMEM)
809 DRM_ERROR("Not enough memory for command submission!\n"); 806 DRM_ERROR("Not enough memory for command submission!\n");
@@ -888,7 +885,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
888 885
889out: 886out:
890 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 887 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
891 mutex_unlock(&vm->mutex);
892 r = amdgpu_cs_handle_lockup(adev, r); 888 r = amdgpu_cs_handle_lockup(adev, r);
893 return r; 889 return r;
894} 890}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 00c5b580f56c..fc32fc01a64b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -115,12 +115,9 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
115 struct amdgpu_vm *vm = &fpriv->vm; 115 struct amdgpu_vm *vm = &fpriv->vm;
116 struct amdgpu_bo_va *bo_va; 116 struct amdgpu_bo_va *bo_va;
117 int r; 117 int r;
118 mutex_lock(&vm->mutex);
119 r = amdgpu_bo_reserve(rbo, false); 118 r = amdgpu_bo_reserve(rbo, false);
120 if (r) { 119 if (r)
121 mutex_unlock(&vm->mutex);
122 return r; 120 return r;
123 }
124 121
125 bo_va = amdgpu_vm_bo_find(vm, rbo); 122 bo_va = amdgpu_vm_bo_find(vm, rbo);
126 if (!bo_va) { 123 if (!bo_va) {
@@ -129,7 +126,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
129 ++bo_va->ref_count; 126 ++bo_va->ref_count;
130 } 127 }
131 amdgpu_bo_unreserve(rbo); 128 amdgpu_bo_unreserve(rbo);
132 mutex_unlock(&vm->mutex);
133 return 0; 129 return 0;
134} 130}
135 131
@@ -142,10 +138,8 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
142 struct amdgpu_vm *vm = &fpriv->vm; 138 struct amdgpu_vm *vm = &fpriv->vm;
143 struct amdgpu_bo_va *bo_va; 139 struct amdgpu_bo_va *bo_va;
144 int r; 140 int r;
145 mutex_lock(&vm->mutex);
146 r = amdgpu_bo_reserve(rbo, true); 141 r = amdgpu_bo_reserve(rbo, true);
147 if (r) { 142 if (r) {
148 mutex_unlock(&vm->mutex);
149 dev_err(adev->dev, "leaking bo va because " 143 dev_err(adev->dev, "leaking bo va because "
150 "we fail to reserve bo (%d)\n", r); 144 "we fail to reserve bo (%d)\n", r);
151 return; 145 return;
@@ -157,7 +151,6 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
157 } 151 }
158 } 152 }
159 amdgpu_bo_unreserve(rbo); 153 amdgpu_bo_unreserve(rbo);
160 mutex_unlock(&vm->mutex);
161} 154}
162 155
163static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 156static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
@@ -553,7 +546,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
553 gobj = drm_gem_object_lookup(dev, filp, args->handle); 546 gobj = drm_gem_object_lookup(dev, filp, args->handle);
554 if (gobj == NULL) 547 if (gobj == NULL)
555 return -ENOENT; 548 return -ENOENT;
556 mutex_lock(&fpriv->vm.mutex);
557 rbo = gem_to_amdgpu_bo(gobj); 549 rbo = gem_to_amdgpu_bo(gobj);
558 INIT_LIST_HEAD(&list); 550 INIT_LIST_HEAD(&list);
559 INIT_LIST_HEAD(&duplicates); 551 INIT_LIST_HEAD(&duplicates);
@@ -568,7 +560,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
568 } 560 }
569 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 561 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
570 if (r) { 562 if (r) {
571 mutex_unlock(&fpriv->vm.mutex);
572 drm_gem_object_unreference_unlocked(gobj); 563 drm_gem_object_unreference_unlocked(gobj);
573 return r; 564 return r;
574 } 565 }
@@ -577,7 +568,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
577 if (!bo_va) { 568 if (!bo_va) {
578 ttm_eu_backoff_reservation(&ticket, &list); 569 ttm_eu_backoff_reservation(&ticket, &list);
579 drm_gem_object_unreference_unlocked(gobj); 570 drm_gem_object_unreference_unlocked(gobj);
580 mutex_unlock(&fpriv->vm.mutex);
581 return -ENOENT; 571 return -ENOENT;
582 } 572 }
583 573
@@ -602,7 +592,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
602 ttm_eu_backoff_reservation(&ticket, &list); 592 ttm_eu_backoff_reservation(&ticket, &list);
603 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 593 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
604 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 594 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
605 mutex_unlock(&fpriv->vm.mutex); 595
606 drm_gem_object_unreference_unlocked(gobj); 596 drm_gem_object_unreference_unlocked(gobj);
607 return r; 597 return r;
608} 598}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 03f0c3bae516..a745eeeb5d82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -392,7 +392,10 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
392 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */ 392 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
393 ib->ptr[ib->length_dw++] = handle; 393 ib->ptr[ib->length_dw++] = handle;
394 394
395 ib->ptr[ib->length_dw++] = 0x00000030; /* len */ 395 if ((ring->adev->vce.fw_version >> 24) >= 52)
396 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
397 else
398 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
396 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */ 399 ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
397 ib->ptr[ib->length_dw++] = 0x00000000; 400 ib->ptr[ib->length_dw++] = 0x00000000;
398 ib->ptr[ib->length_dw++] = 0x00000042; 401 ib->ptr[ib->length_dw++] = 0x00000042;
@@ -404,6 +407,12 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
404 ib->ptr[ib->length_dw++] = 0x00000100; 407 ib->ptr[ib->length_dw++] = 0x00000100;
405 ib->ptr[ib->length_dw++] = 0x0000000c; 408 ib->ptr[ib->length_dw++] = 0x0000000c;
406 ib->ptr[ib->length_dw++] = 0x00000000; 409 ib->ptr[ib->length_dw++] = 0x00000000;
410 if ((ring->adev->vce.fw_version >> 24) >= 52) {
411 ib->ptr[ib->length_dw++] = 0x00000000;
412 ib->ptr[ib->length_dw++] = 0x00000000;
413 ib->ptr[ib->length_dw++] = 0x00000000;
414 ib->ptr[ib->length_dw++] = 0x00000000;
415 }
407 416
408 ib->ptr[ib->length_dw++] = 0x00000014; /* len */ 417 ib->ptr[ib->length_dw++] = 0x00000014; /* len */
409 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */ 418 ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 159ce54bbd8d..ae037e5b6ad0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -922,8 +922,9 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
922 bo_va = list_first_entry(&vm->invalidated, 922 bo_va = list_first_entry(&vm->invalidated,
923 struct amdgpu_bo_va, vm_status); 923 struct amdgpu_bo_va, vm_status);
924 spin_unlock(&vm->status_lock); 924 spin_unlock(&vm->status_lock);
925 925 mutex_lock(&bo_va->mutex);
926 r = amdgpu_vm_bo_update(adev, bo_va, NULL); 926 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
927 mutex_unlock(&bo_va->mutex);
927 if (r) 928 if (r)
928 return r; 929 return r;
929 930
@@ -967,7 +968,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
967 INIT_LIST_HEAD(&bo_va->valids); 968 INIT_LIST_HEAD(&bo_va->valids);
968 INIT_LIST_HEAD(&bo_va->invalids); 969 INIT_LIST_HEAD(&bo_va->invalids);
969 INIT_LIST_HEAD(&bo_va->vm_status); 970 INIT_LIST_HEAD(&bo_va->vm_status);
970 971 mutex_init(&bo_va->mutex);
971 list_add_tail(&bo_va->bo_list, &bo->va); 972 list_add_tail(&bo_va->bo_list, &bo->va);
972 973
973 return bo_va; 974 return bo_va;
@@ -1045,7 +1046,9 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1045 mapping->offset = offset; 1046 mapping->offset = offset;
1046 mapping->flags = flags; 1047 mapping->flags = flags;
1047 1048
1049 mutex_lock(&bo_va->mutex);
1048 list_add(&mapping->list, &bo_va->invalids); 1050 list_add(&mapping->list, &bo_va->invalids);
1051 mutex_unlock(&bo_va->mutex);
1049 spin_lock(&vm->it_lock); 1052 spin_lock(&vm->it_lock);
1050 interval_tree_insert(&mapping->it, &vm->va); 1053 interval_tree_insert(&mapping->it, &vm->va);
1051 spin_unlock(&vm->it_lock); 1054 spin_unlock(&vm->it_lock);
@@ -1121,7 +1124,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1121 bool valid = true; 1124 bool valid = true;
1122 1125
1123 saddr /= AMDGPU_GPU_PAGE_SIZE; 1126 saddr /= AMDGPU_GPU_PAGE_SIZE;
1124 1127 mutex_lock(&bo_va->mutex);
1125 list_for_each_entry(mapping, &bo_va->valids, list) { 1128 list_for_each_entry(mapping, &bo_va->valids, list) {
1126 if (mapping->it.start == saddr) 1129 if (mapping->it.start == saddr)
1127 break; 1130 break;
@@ -1135,10 +1138,12 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1135 break; 1138 break;
1136 } 1139 }
1137 1140
1138 if (&mapping->list == &bo_va->invalids) 1141 if (&mapping->list == &bo_va->invalids) {
1142 mutex_unlock(&bo_va->mutex);
1139 return -ENOENT; 1143 return -ENOENT;
1144 }
1140 } 1145 }
1141 1146 mutex_unlock(&bo_va->mutex);
1142 list_del(&mapping->list); 1147 list_del(&mapping->list);
1143 spin_lock(&vm->it_lock); 1148 spin_lock(&vm->it_lock);
1144 interval_tree_remove(&mapping->it, &vm->va); 1149 interval_tree_remove(&mapping->it, &vm->va);
@@ -1190,8 +1195,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1190 spin_unlock(&vm->it_lock); 1195 spin_unlock(&vm->it_lock);
1191 kfree(mapping); 1196 kfree(mapping);
1192 } 1197 }
1193
1194 fence_put(bo_va->last_pt_update); 1198 fence_put(bo_va->last_pt_update);
1199 mutex_destroy(&bo_va->mutex);
1195 kfree(bo_va); 1200 kfree(bo_va);
1196} 1201}
1197 1202
@@ -1236,7 +1241,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1236 vm->ids[i].id = 0; 1241 vm->ids[i].id = 0;
1237 vm->ids[i].flushed_updates = NULL; 1242 vm->ids[i].flushed_updates = NULL;
1238 } 1243 }
1239 mutex_init(&vm->mutex);
1240 vm->va = RB_ROOT; 1244 vm->va = RB_ROOT;
1241 spin_lock_init(&vm->status_lock); 1245 spin_lock_init(&vm->status_lock);
1242 INIT_LIST_HEAD(&vm->invalidated); 1246 INIT_LIST_HEAD(&vm->invalidated);
@@ -1320,7 +1324,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1320 fence_put(vm->ids[i].flushed_updates); 1324 fence_put(vm->ids[i].flushed_updates);
1321 } 1325 }
1322 1326
1323 mutex_destroy(&vm->mutex);
1324} 1327}
1325 1328
1326/** 1329/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 6a52db6ad8d7..370c6c9d81c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -40,6 +40,9 @@
40 40
41#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 41#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
42#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 42#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
43#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
44#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
45#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
43 46
44#define VCE_V3_0_FW_SIZE (384 * 1024) 47#define VCE_V3_0_FW_SIZE (384 * 1024)
45#define VCE_V3_0_STACK_SIZE (64 * 1024) 48#define VCE_V3_0_STACK_SIZE (64 * 1024)
@@ -130,9 +133,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
130 133
131 /* set BUSY flag */ 134 /* set BUSY flag */
132 WREG32_P(mmVCE_STATUS, 1, ~1); 135 WREG32_P(mmVCE_STATUS, 1, ~1);
133 136 if (adev->asic_type >= CHIP_STONEY)
134 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, 137 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
135 ~VCE_VCPU_CNTL__CLK_EN_MASK); 138 else
139 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
140 ~VCE_VCPU_CNTL__CLK_EN_MASK);
136 141
137 WREG32_P(mmVCE_SOFT_RESET, 142 WREG32_P(mmVCE_SOFT_RESET,
138 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, 143 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
@@ -391,8 +396,12 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
391 WREG32(mmVCE_LMI_SWAP_CNTL, 0); 396 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
392 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); 397 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
393 WREG32(mmVCE_LMI_VM_CTRL, 0); 398 WREG32(mmVCE_LMI_VM_CTRL, 0);
394 399 if (adev->asic_type >= CHIP_STONEY) {
395 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); 400 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
401 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
402 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
403 } else
404 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
396 offset = AMDGPU_VCE_FIRMWARE_OFFSET; 405 offset = AMDGPU_VCE_FIRMWARE_OFFSET;
397 size = VCE_V3_0_FW_SIZE; 406 size = VCE_V3_0_FW_SIZE;
398 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); 407 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
@@ -576,6 +585,11 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
576 struct amdgpu_iv_entry *entry) 585 struct amdgpu_iv_entry *entry)
577{ 586{
578 DRM_DEBUG("IH: VCE\n"); 587 DRM_DEBUG("IH: VCE\n");
588
589 WREG32_P(mmVCE_SYS_INT_STATUS,
590 VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
591 ~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
592
579 switch (entry->src_data) { 593 switch (entry->src_data) {
580 case 0: 594 case 0:
581 amdgpu_fence_process(&adev->vce.ring[0]); 595 amdgpu_fence_process(&adev->vce.ring[0]);
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index ea30d6ad4c13..651129f2ec1d 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -30,8 +30,7 @@
30#define CREATE_TRACE_POINTS 30#define CREATE_TRACE_POINTS
31#include "gpu_sched_trace.h" 31#include "gpu_sched_trace.h"
32 32
33static struct amd_sched_job * 33static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
34amd_sched_entity_pop_job(struct amd_sched_entity *entity);
35static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); 34static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
36 35
37struct kmem_cache *sched_fence_slab; 36struct kmem_cache *sched_fence_slab;
@@ -64,36 +63,36 @@ static void amd_sched_rq_remove_entity(struct amd_sched_rq *rq,
64} 63}
65 64
66/** 65/**
67 * Select next job from a specified run queue with round robin policy. 66 * Select an entity which could provide a job to run
68 * Return NULL if nothing available. 67 *
68 * @rq The run queue to check.
69 *
70 * Try to find a ready entity, returns NULL if none found.
69 */ 71 */
70static struct amd_sched_job * 72static struct amd_sched_entity *
71amd_sched_rq_select_job(struct amd_sched_rq *rq) 73amd_sched_rq_select_entity(struct amd_sched_rq *rq)
72{ 74{
73 struct amd_sched_entity *entity; 75 struct amd_sched_entity *entity;
74 struct amd_sched_job *sched_job;
75 76
76 spin_lock(&rq->lock); 77 spin_lock(&rq->lock);
77 78
78 entity = rq->current_entity; 79 entity = rq->current_entity;
79 if (entity) { 80 if (entity) {
80 list_for_each_entry_continue(entity, &rq->entities, list) { 81 list_for_each_entry_continue(entity, &rq->entities, list) {
81 sched_job = amd_sched_entity_pop_job(entity); 82 if (amd_sched_entity_is_ready(entity)) {
82 if (sched_job) {
83 rq->current_entity = entity; 83 rq->current_entity = entity;
84 spin_unlock(&rq->lock); 84 spin_unlock(&rq->lock);
85 return sched_job; 85 return entity;
86 } 86 }
87 } 87 }
88 } 88 }
89 89
90 list_for_each_entry(entity, &rq->entities, list) { 90 list_for_each_entry(entity, &rq->entities, list) {
91 91
92 sched_job = amd_sched_entity_pop_job(entity); 92 if (amd_sched_entity_is_ready(entity)) {
93 if (sched_job) {
94 rq->current_entity = entity; 93 rq->current_entity = entity;
95 spin_unlock(&rq->lock); 94 spin_unlock(&rq->lock);
96 return sched_job; 95 return entity;
97 } 96 }
98 97
99 if (entity == rq->current_entity) 98 if (entity == rq->current_entity)
@@ -177,6 +176,24 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
177} 176}
178 177
179/** 178/**
179 * Check if entity is ready
180 *
181 * @entity The pointer to a valid scheduler entity
182 *
183 * Return true if entity could provide a job.
184 */
185static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
186{
187 if (kfifo_is_empty(&entity->job_queue))
188 return false;
189
190 if (ACCESS_ONCE(entity->dependency))
191 return false;
192
193 return true;
194}
195
196/**
180 * Destroy a context entity 197 * Destroy a context entity
181 * 198 *
182 * @sched Pointer to scheduler instance 199 * @sched Pointer to scheduler instance
@@ -211,32 +228,53 @@ static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb)
211 amd_sched_wakeup(entity->sched); 228 amd_sched_wakeup(entity->sched);
212} 229}
213 230
231static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity)
232{
233 struct amd_gpu_scheduler *sched = entity->sched;
234 struct fence * fence = entity->dependency;
235 struct amd_sched_fence *s_fence;
236
237 if (fence->context == entity->fence_context) {
238 /* We can ignore fences from ourself */
239 fence_put(entity->dependency);
240 return false;
241 }
242
243 s_fence = to_amd_sched_fence(fence);
244 if (s_fence && s_fence->sched == sched) {
245 /* Fence is from the same scheduler */
246 if (test_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &fence->flags)) {
247 /* Ignore it when it is already scheduled */
248 fence_put(entity->dependency);
249 return false;
250 }
251
252 /* Wait for fence to be scheduled */
253 entity->cb.func = amd_sched_entity_wakeup;
254 list_add_tail(&entity->cb.node, &s_fence->scheduled_cb);
255 return true;
256 }
257
258 if (!fence_add_callback(entity->dependency, &entity->cb,
259 amd_sched_entity_wakeup))
260 return true;
261
262 fence_put(entity->dependency);
263 return false;
264}
265
214static struct amd_sched_job * 266static struct amd_sched_job *
215amd_sched_entity_pop_job(struct amd_sched_entity *entity) 267amd_sched_entity_pop_job(struct amd_sched_entity *entity)
216{ 268{
217 struct amd_gpu_scheduler *sched = entity->sched; 269 struct amd_gpu_scheduler *sched = entity->sched;
218 struct amd_sched_job *sched_job; 270 struct amd_sched_job *sched_job;
219 271
220 if (ACCESS_ONCE(entity->dependency))
221 return NULL;
222
223 if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job))) 272 if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job)))
224 return NULL; 273 return NULL;
225 274
226 while ((entity->dependency = sched->ops->dependency(sched_job))) { 275 while ((entity->dependency = sched->ops->dependency(sched_job)))
227 276 if (amd_sched_entity_add_dependency_cb(entity))
228 if (entity->dependency->context == entity->fence_context) {
229 /* We can ignore fences from ourself */
230 fence_put(entity->dependency);
231 continue;
232 }
233
234 if (fence_add_callback(entity->dependency, &entity->cb,
235 amd_sched_entity_wakeup))
236 fence_put(entity->dependency);
237 else
238 return NULL; 277 return NULL;
239 }
240 278
241 return sched_job; 279 return sched_job;
242} 280}
@@ -304,22 +342,22 @@ static void amd_sched_wakeup(struct amd_gpu_scheduler *sched)
304} 342}
305 343
306/** 344/**
307 * Select next to run 345 * Select next entity to process
308*/ 346*/
309static struct amd_sched_job * 347static struct amd_sched_entity *
310amd_sched_select_job(struct amd_gpu_scheduler *sched) 348amd_sched_select_entity(struct amd_gpu_scheduler *sched)
311{ 349{
312 struct amd_sched_job *sched_job; 350 struct amd_sched_entity *entity;
313 351
314 if (!amd_sched_ready(sched)) 352 if (!amd_sched_ready(sched))
315 return NULL; 353 return NULL;
316 354
317 /* Kernel run queue has higher priority than normal run queue*/ 355 /* Kernel run queue has higher priority than normal run queue*/
318 sched_job = amd_sched_rq_select_job(&sched->kernel_rq); 356 entity = amd_sched_rq_select_entity(&sched->kernel_rq);
319 if (sched_job == NULL) 357 if (entity == NULL)
320 sched_job = amd_sched_rq_select_job(&sched->sched_rq); 358 entity = amd_sched_rq_select_entity(&sched->sched_rq);
321 359
322 return sched_job; 360 return entity;
323} 361}
324 362
325static void amd_sched_process_job(struct fence *f, struct fence_cb *cb) 363static void amd_sched_process_job(struct fence *f, struct fence_cb *cb)
@@ -381,13 +419,16 @@ static int amd_sched_main(void *param)
381 unsigned long flags; 419 unsigned long flags;
382 420
383 wait_event_interruptible(sched->wake_up_worker, 421 wait_event_interruptible(sched->wake_up_worker,
384 kthread_should_stop() || 422 (entity = amd_sched_select_entity(sched)) ||
385 (sched_job = amd_sched_select_job(sched))); 423 kthread_should_stop());
386 424
425 if (!entity)
426 continue;
427
428 sched_job = amd_sched_entity_pop_job(entity);
387 if (!sched_job) 429 if (!sched_job)
388 continue; 430 continue;
389 431
390 entity = sched_job->s_entity;
391 s_fence = sched_job->s_fence; 432 s_fence = sched_job->s_fence;
392 433
393 if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { 434 if (sched->timeout != MAX_SCHEDULE_TIMEOUT) {
@@ -400,6 +441,7 @@ static int amd_sched_main(void *param)
400 441
401 atomic_inc(&sched->hw_rq_count); 442 atomic_inc(&sched->hw_rq_count);
402 fence = sched->ops->run_job(sched_job); 443 fence = sched->ops->run_job(sched_job);
444 amd_sched_fence_scheduled(s_fence);
403 if (fence) { 445 if (fence) {
404 r = fence_add_callback(fence, &s_fence->cb, 446 r = fence_add_callback(fence, &s_fence->cb,
405 amd_sched_process_job); 447 amd_sched_process_job);
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
index 939692b14f4b..a0f0ae53aacd 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
@@ -27,6 +27,8 @@
27#include <linux/kfifo.h> 27#include <linux/kfifo.h>
28#include <linux/fence.h> 28#include <linux/fence.h>
29 29
30#define AMD_SCHED_FENCE_SCHEDULED_BIT FENCE_FLAG_USER_BITS
31
30struct amd_gpu_scheduler; 32struct amd_gpu_scheduler;
31struct amd_sched_rq; 33struct amd_sched_rq;
32 34
@@ -68,6 +70,7 @@ struct amd_sched_rq {
68struct amd_sched_fence { 70struct amd_sched_fence {
69 struct fence base; 71 struct fence base;
70 struct fence_cb cb; 72 struct fence_cb cb;
73 struct list_head scheduled_cb;
71 struct amd_gpu_scheduler *sched; 74 struct amd_gpu_scheduler *sched;
72 spinlock_t lock; 75 spinlock_t lock;
73 void *owner; 76 void *owner;
@@ -134,7 +137,7 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
134 137
135struct amd_sched_fence *amd_sched_fence_create( 138struct amd_sched_fence *amd_sched_fence_create(
136 struct amd_sched_entity *s_entity, void *owner); 139 struct amd_sched_entity *s_entity, void *owner);
140void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
137void amd_sched_fence_signal(struct amd_sched_fence *fence); 141void amd_sched_fence_signal(struct amd_sched_fence *fence);
138 142
139
140#endif 143#endif
diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c
index 8d2130b9ff05..87c78eecea64 100644
--- a/drivers/gpu/drm/amd/scheduler/sched_fence.c
+++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c
@@ -35,6 +35,8 @@ struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *s_entity
35 fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL); 35 fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL);
36 if (fence == NULL) 36 if (fence == NULL)
37 return NULL; 37 return NULL;
38
39 INIT_LIST_HEAD(&fence->scheduled_cb);
38 fence->owner = owner; 40 fence->owner = owner;
39 fence->sched = s_entity->sched; 41 fence->sched = s_entity->sched;
40 spin_lock_init(&fence->lock); 42 spin_lock_init(&fence->lock);
@@ -55,6 +57,17 @@ void amd_sched_fence_signal(struct amd_sched_fence *fence)
55 FENCE_TRACE(&fence->base, "was already signaled\n"); 57 FENCE_TRACE(&fence->base, "was already signaled\n");
56} 58}
57 59
60void amd_sched_fence_scheduled(struct amd_sched_fence *s_fence)
61{
62 struct fence_cb *cur, *tmp;
63
64 set_bit(AMD_SCHED_FENCE_SCHEDULED_BIT, &s_fence->base.flags);
65 list_for_each_entry_safe(cur, tmp, &s_fence->scheduled_cb, node) {
66 list_del_init(&cur->node);
67 cur->func(&s_fence->base, cur);
68 }
69}
70
58static const char *amd_sched_fence_get_driver_name(struct fence *fence) 71static const char *amd_sched_fence_get_driver_name(struct fence *fence)
59{ 72{
60 return "amd_sched"; 73 return "amd_sched";
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
index 28bc202f9753..40f845e31272 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
@@ -7,6 +7,7 @@ struct nvkm_instmem {
7 const struct nvkm_instmem_func *func; 7 const struct nvkm_instmem_func *func;
8 struct nvkm_subdev subdev; 8 struct nvkm_subdev subdev;
9 9
10 spinlock_t lock;
10 struct list_head list; 11 struct list_head list;
11 u32 reserved; 12 u32 reserved;
12 13
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 8b8332e46f24..d5e6938cc6bc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -367,6 +367,7 @@ static int nouveau_rom_call(acpi_handle rom_handle, uint8_t *bios,
367 return -ENODEV; 367 return -ENODEV;
368 } 368 }
369 obj = (union acpi_object *)buffer.pointer; 369 obj = (union acpi_object *)buffer.pointer;
370 len = min(len, (int)obj->buffer.length);
370 memcpy(bios+offset, obj->buffer.pointer, len); 371 memcpy(bios+offset, obj->buffer.pointer, len);
371 kfree(buffer.pointer); 372 kfree(buffer.pointer);
372 return len; 373 return len;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index 3050042e6c6d..a02813e994ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -39,6 +39,7 @@
39 39
40#include <nvif/client.h> 40#include <nvif/client.h>
41#include <nvif/device.h> 41#include <nvif/device.h>
42#include <nvif/ioctl.h>
42 43
43#include <drmP.h> 44#include <drmP.h>
44 45
@@ -65,9 +66,10 @@ struct nouveau_drm_tile {
65}; 66};
66 67
67enum nouveau_drm_object_route { 68enum nouveau_drm_object_route {
68 NVDRM_OBJECT_NVIF = 0, 69 NVDRM_OBJECT_NVIF = NVIF_IOCTL_V0_OWNER_NVIF,
69 NVDRM_OBJECT_USIF, 70 NVDRM_OBJECT_USIF,
70 NVDRM_OBJECT_ABI16, 71 NVDRM_OBJECT_ABI16,
72 NVDRM_OBJECT_ANY = NVIF_IOCTL_V0_OWNER_ANY,
71}; 73};
72 74
73enum nouveau_drm_notify_route { 75enum nouveau_drm_notify_route {
diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c
index 89dc4ce63490..6ae1b3494bcd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_usif.c
+++ b/drivers/gpu/drm/nouveau/nouveau_usif.c
@@ -313,7 +313,10 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc)
313 if (nvif_unpack(argv->v0, 0, 0, true)) { 313 if (nvif_unpack(argv->v0, 0, 0, true)) {
314 /* block access to objects not created via this interface */ 314 /* block access to objects not created via this interface */
315 owner = argv->v0.owner; 315 owner = argv->v0.owner;
316 argv->v0.owner = NVDRM_OBJECT_USIF; 316 if (argv->v0.object == 0ULL)
317 argv->v0.owner = NVDRM_OBJECT_ANY; /* except client */
318 else
319 argv->v0.owner = NVDRM_OBJECT_USIF;
317 } else 320 } else
318 goto done; 321 goto done;
319 322
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
index e3c783d0e2ab..caf22b589edc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
@@ -279,6 +279,12 @@ nvkm_device_pci_10de_0fe3[] = {
279}; 279};
280 280
281static const struct nvkm_device_pci_vendor 281static const struct nvkm_device_pci_vendor
282nvkm_device_pci_10de_0fe4[] = {
283 { 0x144d, 0xc740, NULL, { .War00C800_0 = true } },
284 {}
285};
286
287static const struct nvkm_device_pci_vendor
282nvkm_device_pci_10de_104b[] = { 288nvkm_device_pci_10de_104b[] = {
283 { 0x1043, 0x844c, "GeForce GT 625" }, 289 { 0x1043, 0x844c, "GeForce GT 625" },
284 { 0x1043, 0x846b, "GeForce GT 625" }, 290 { 0x1043, 0x846b, "GeForce GT 625" },
@@ -689,6 +695,12 @@ nvkm_device_pci_10de_1199[] = {
689}; 695};
690 696
691static const struct nvkm_device_pci_vendor 697static const struct nvkm_device_pci_vendor
698nvkm_device_pci_10de_11e0[] = {
699 { 0x1558, 0x5106, NULL, { .War00C800_0 = true } },
700 {}
701};
702
703static const struct nvkm_device_pci_vendor
692nvkm_device_pci_10de_11e3[] = { 704nvkm_device_pci_10de_11e3[] = {
693 { 0x17aa, 0x3683, "GeForce GTX 760A" }, 705 { 0x17aa, 0x3683, "GeForce GTX 760A" },
694 {} 706 {}
@@ -1370,7 +1382,7 @@ nvkm_device_pci_10de[] = {
1370 { 0x0fe1, "GeForce GT 730M" }, 1382 { 0x0fe1, "GeForce GT 730M" },
1371 { 0x0fe2, "GeForce GT 745M" }, 1383 { 0x0fe2, "GeForce GT 745M" },
1372 { 0x0fe3, "GeForce GT 745M", nvkm_device_pci_10de_0fe3 }, 1384 { 0x0fe3, "GeForce GT 745M", nvkm_device_pci_10de_0fe3 },
1373 { 0x0fe4, "GeForce GT 750M" }, 1385 { 0x0fe4, "GeForce GT 750M", nvkm_device_pci_10de_0fe4 },
1374 { 0x0fe9, "GeForce GT 750M" }, 1386 { 0x0fe9, "GeForce GT 750M" },
1375 { 0x0fea, "GeForce GT 755M" }, 1387 { 0x0fea, "GeForce GT 755M" },
1376 { 0x0fec, "GeForce 710A" }, 1388 { 0x0fec, "GeForce 710A" },
@@ -1485,7 +1497,7 @@ nvkm_device_pci_10de[] = {
1485 { 0x11c6, "GeForce GTX 650 Ti" }, 1497 { 0x11c6, "GeForce GTX 650 Ti" },
1486 { 0x11c8, "GeForce GTX 650" }, 1498 { 0x11c8, "GeForce GTX 650" },
1487 { 0x11cb, "GeForce GT 740" }, 1499 { 0x11cb, "GeForce GT 740" },
1488 { 0x11e0, "GeForce GTX 770M" }, 1500 { 0x11e0, "GeForce GTX 770M", nvkm_device_pci_10de_11e0 },
1489 { 0x11e1, "GeForce GTX 765M" }, 1501 { 0x11e1, "GeForce GTX 765M" },
1490 { 0x11e2, "GeForce GTX 765M" }, 1502 { 0x11e2, "GeForce GTX 765M" },
1491 { 0x11e3, "GeForce GTX 760M", nvkm_device_pci_10de_11e3 }, 1503 { 0x11e3, "GeForce GTX 760M", nvkm_device_pci_10de_11e3 },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
index b5b875928aba..74de7a96c22a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
@@ -207,6 +207,8 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info)
207 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; 207 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
208 const u32 t = timeslice_mode; 208 const u32 t = timeslice_mode;
209 const u32 o = PPC_UNIT(gpc, ppc, 0); 209 const u32 o = PPC_UNIT(gpc, ppc, 0);
210 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
211 continue;
210 mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); 212 mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
211 mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); 213 mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
212 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; 214 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc];
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
index 194afe910d21..7dacb3cc0668 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
@@ -52,10 +52,12 @@ mmio_list_base:
52#endif 52#endif
53 53
54#ifdef INCLUDE_CODE 54#ifdef INCLUDE_CODE
55#define gpc_addr(reg,addr) /*
56*/ imm32(reg,addr) /*
57*/ or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
55#define gpc_wr32(addr,reg) /* 58#define gpc_wr32(addr,reg) /*
59*/ gpc_addr($r14,addr) /*
56*/ mov b32 $r15 reg /* 60*/ mov b32 $r15 reg /*
57*/ imm32($r14, addr) /*
58*/ or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE /*
59*/ call(nv_wr32) 61*/ call(nv_wr32)
60 62
61// reports an exception to the host 63// reports an exception to the host
@@ -161,7 +163,7 @@ init:
161 163
162#if NV_PGRAPH_GPCX_UNK__SIZE > 0 164#if NV_PGRAPH_GPCX_UNK__SIZE > 0
163 // figure out which, and how many, UNKs are actually present 165 // figure out which, and how many, UNKs are actually present
164 imm32($r14, 0x500c30) 166 gpc_addr($r14, 0x500c30)
165 clear b32 $r2 167 clear b32 $r2
166 clear b32 $r3 168 clear b32 $r3
167 clear b32 $r4 169 clear b32 $r4
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
index 64d07df4b8b1..bb820ff28621 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gf117_grgpc_code[] = {
314 0x03f01200, 314 0x03f01200,
315 0x0002d000, 315 0x0002d000,
316 0x17f104bd, 316 0x17f104bd,
317 0x10fe0542, 317 0x10fe0545,
318 0x0007f100, 318 0x0007f100,
319 0x0003f007, 319 0x0003f007,
320 0xbd0000d0, 320 0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gf117_grgpc_code[] = {
338 0x02d00103, 338 0x02d00103,
339 0xf104bd00, 339 0xf104bd00,
340 0xf00c30e7, 340 0xf00c30e7,
341 0x24bd50e3, 341 0xe5f050e3,
342 0x44bd34bd, 342 0xbd24bd01,
343/* 0x0430: init_unk_loop */ 343/* 0x0433: init_unk_loop */
344 0xb06821f4, 344 0xf444bd34,
345 0x0bf400f6, 345 0xf6b06821,
346 0x01f7f00f, 346 0x0f0bf400,
347 0xfd04f2bb, 347 0xbb01f7f0,
348 0x30b6054f, 348 0x4ffd04f2,
349/* 0x0445: init_unk_next */ 349 0x0130b605,
350 0x0120b601, 350/* 0x0448: init_unk_next */
351 0xb004e0b6, 351 0xb60120b6,
352 0x1bf40126, 352 0x26b004e0,
353/* 0x0451: init_unk_done */ 353 0xe21bf401,
354 0x070380e2, 354/* 0x0454: init_unk_done */
355 0xf1080480, 355 0x80070380,
356 0xf0010027, 356 0x27f10804,
357 0x22cf0223, 357 0x23f00100,
358 0x9534bd00, 358 0x0022cf02,
359 0x07f10825, 359 0x259534bd,
360 0x03f0c000, 360 0x0007f108,
361 0x0005d001, 361 0x0103f0c0,
362 0x07f104bd, 362 0xbd0005d0,
363 0x03f0c100, 363 0x0007f104,
364 0x0005d001, 364 0x0103f0c1,
365 0x0e9804bd, 365 0xbd0005d0,
366 0x010f9800, 366 0x000e9804,
367 0x015021f5, 367 0xf5010f98,
368 0xbb002fbb, 368 0xbb015021,
369 0x0e98003f, 369 0x3fbb002f,
370 0x020f9801, 370 0x010e9800,
371 0x015021f5, 371 0xf5020f98,
372 0xfd050e98, 372 0x98015021,
373 0x2ebb00ef, 373 0xeffd050e,
374 0x003ebb00, 374 0x002ebb00,
375 0x98020e98, 375 0x98003ebb,
376 0x21f5030f, 376 0x0f98020e,
377 0x0e980150, 377 0x5021f503,
378 0x00effd07, 378 0x070e9801,
379 0xbb002ebb, 379 0xbb00effd,
380 0x35b6003e, 380 0x3ebb002e,
381 0x0007f102, 381 0x0235b600,
382 0x0103f0d3, 382 0xd30007f1,
383 0xbd0003d0, 383 0xd00103f0,
384 0x0825b604,
385 0xb60635b6,
386 0x30b60120,
387 0x0824b601,
388 0xb90834b6,
389 0x21f5022f,
390 0x2fbb02d3,
391 0x003fbb00,
392 0x010007f1,
393 0xd00203f0,
394 0x04bd0003, 384 0x04bd0003,
395 0x29f024bd, 385 0xb60825b6,
396 0x0007f11f, 386 0x20b60635,
397 0x0203f008, 387 0x0130b601,
398 0xbd0002d0, 388 0xb60824b6,
399/* 0x0505: main */ 389 0x2fb90834,
400 0x0031f404, 390 0xd321f502,
401 0xf00028f4, 391 0x002fbb02,
402 0x21f424d7, 392 0xf1003fbb,
403 0xf401f439, 393 0xf0010007,
404 0xf404e4b0, 394 0x03d00203,
405 0x81fe1e18, 395 0xbd04bd00,
406 0x0627f001, 396 0x1f29f024,
407 0x12fd20bd, 397 0x080007f1,
408 0x01e4b604, 398 0xd00203f0,
409 0xfe051efd, 399 0x04bd0002,
410 0x21f50018, 400/* 0x0508: main */
411 0x0ef405fa, 401 0xf40031f4,
412/* 0x0535: main_not_ctx_xfer */ 402 0xd7f00028,
413 0x10ef94d3, 403 0x3921f424,
414 0xf501f5f0, 404 0xb0f401f4,
415 0xf4037e21, 405 0x18f404e4,
416/* 0x0542: ih */ 406 0x0181fe1e,
417 0x80f9c60e, 407 0xbd0627f0,
418 0xf90188fe, 408 0x0412fd20,
419 0xf990f980, 409 0xfd01e4b6,
420 0xf9b0f9a0, 410 0x18fe051e,
421 0xf9e0f9d0, 411 0xfd21f500,
422 0xf104bdf0, 412 0xd30ef405,
423 0xf00200a7, 413/* 0x0538: main_not_ctx_xfer */
424 0xaacf00a3, 414 0xf010ef94,
425 0x04abc400, 415 0x21f501f5,
426 0xf02c0bf4, 416 0x0ef4037e,
427 0xe7f124d7, 417/* 0x0545: ih */
428 0xe3f01a00, 418 0xfe80f9c6,
429 0x00eecf00, 419 0x80f90188,
430 0x1900f7f1, 420 0xa0f990f9,
431 0xcf00f3f0, 421 0xd0f9b0f9,
432 0x21f400ff, 422 0xf0f9e0f9,
433 0x01e7f004, 423 0xa7f104bd,
434 0x1d0007f1, 424 0xa3f00200,
435 0xd00003f0, 425 0x00aacf00,
436 0x04bd000e, 426 0xf404abc4,
437/* 0x0590: ih_no_fifo */ 427 0xd7f02c0b,
438 0x010007f1, 428 0x00e7f124,
439 0xd00003f0, 429 0x00e3f01a,
440 0x04bd000a, 430 0xf100eecf,
441 0xe0fcf0fc, 431 0xf01900f7,
442 0xb0fcd0fc, 432 0xffcf00f3,
443 0x90fca0fc, 433 0x0421f400,
444 0x88fe80fc, 434 0xf101e7f0,
445 0xf480fc00, 435 0xf01d0007,
446 0x01f80032, 436 0x0ed00003,
447/* 0x05b4: hub_barrier_done */ 437/* 0x0593: ih_no_fifo */
448 0x9801f7f0, 438 0xf104bd00,
449 0xfebb040e, 439 0xf0010007,
450 0x02ffb904, 440 0x0ad00003,
451 0x9418e7f1, 441 0xfc04bd00,
452 0xf440e3f0, 442 0xfce0fcf0,
453 0x00f89d21, 443 0xfcb0fcd0,
454/* 0x05cc: ctx_redswitch */ 444 0xfc90fca0,
455 0xf120f7f0, 445 0x0088fe80,
446 0x32f480fc,
447/* 0x05b7: hub_barrier_done */
448 0xf001f800,
449 0x0e9801f7,
450 0x04febb04,
451 0xf102ffb9,
452 0xf09418e7,
453 0x21f440e3,
454/* 0x05cf: ctx_redswitch */
455 0xf000f89d,
456 0x07f120f7,
457 0x03f08500,
458 0x000fd001,
459 0xe7f004bd,
460/* 0x05e1: ctx_redswitch_delay */
461 0x01e2b608,
462 0xf1fd1bf4,
463 0xf10800f5,
464 0xf10200f5,
456 0xf0850007, 465 0xf0850007,
457 0x0fd00103, 466 0x0fd00103,
458 0xf004bd00, 467 0xf804bd00,
459/* 0x05de: ctx_redswitch_delay */ 468/* 0x05fd: ctx_xfer */
460 0xe2b608e7, 469 0x0007f100,
461 0xfd1bf401, 470 0x0203f081,
462 0x0800f5f1, 471 0xbd000fd0,
463 0x0200f5f1, 472 0x0711f404,
464 0x850007f1, 473 0x05cf21f5,
465 0xd00103f0, 474/* 0x0610: ctx_xfer_not_load */
466 0x04bd000f, 475 0x026a21f5,
467/* 0x05fa: ctx_xfer */ 476 0x07f124bd,
468 0x07f100f8, 477 0x03f047fc,
469 0x03f08100, 478 0x0002d002,
470 0x000fd002, 479 0x2cf004bd,
471 0x11f404bd, 480 0x0320b601,
472 0xcc21f507, 481 0x4afc07f1,
473/* 0x060d: ctx_xfer_not_load */ 482 0xd00203f0,
474 0x6a21f505, 483 0x04bd0002,
475 0xf124bd02,
476 0xf047fc07,
477 0x02d00203,
478 0xf004bd00,
479 0x20b6012c,
480 0xfc07f103,
481 0x0203f04a,
482 0xbd0002d0,
483 0x01acf004,
484 0xf102a5f0,
485 0xf00000b7,
486 0x0c9850b3,
487 0x0fc4b604,
488 0x9800bcbb,
489 0x0d98000c,
490 0x00e7f001,
491 0x016f21f5,
492 0xf101acf0,
493 0xf04000b7,
494 0x0c9850b3,
495 0x0fc4b604,
496 0x9800bcbb,
497 0x0d98010c,
498 0x060f9802,
499 0x0800e7f1,
500 0x016f21f5,
501 0xf001acf0, 484 0xf001acf0,
502 0xb7f104a5, 485 0xb7f102a5,
503 0xb3f03000, 486 0xb3f00000,
504 0x040c9850, 487 0x040c9850,
505 0xbb0fc4b6, 488 0xbb0fc4b6,
506 0x0c9800bc, 489 0x0c9800bc,
507 0x030d9802, 490 0x010d9800,
508 0xf1080f98, 491 0xf500e7f0,
509 0xf50200e7, 492 0xf0016f21,
510 0xf5016f21, 493 0xb7f101ac,
511 0xf4025e21, 494 0xb3f04000,
512 0x12f40601, 495 0x040c9850,
513/* 0x06a9: ctx_xfer_post */ 496 0xbb0fc4b6,
514 0x7f21f507, 497 0x0c9800bc,
515/* 0x06ad: ctx_xfer_done */ 498 0x020d9801,
516 0xb421f502, 499 0xf1060f98,
517 0x0000f805, 500 0xf50800e7,
518 0x00000000, 501 0xf0016f21,
502 0xa5f001ac,
503 0x00b7f104,
504 0x50b3f030,
505 0xb6040c98,
506 0xbcbb0fc4,
507 0x020c9800,
508 0x98030d98,
509 0xe7f1080f,
510 0x21f50200,
511 0x21f5016f,
512 0x01f4025e,
513 0x0712f406,
514/* 0x06ac: ctx_xfer_post */
515 0x027f21f5,
516/* 0x06b0: ctx_xfer_done */
517 0x05b721f5,
518 0x000000f8,
519 0x00000000, 519 0x00000000,
520 0x00000000, 520 0x00000000,
521 0x00000000, 521 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
index 2f596433c222..911976d20940 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gk104_grgpc_code[] = {
314 0x03f01200, 314 0x03f01200,
315 0x0002d000, 315 0x0002d000,
316 0x17f104bd, 316 0x17f104bd,
317 0x10fe0542, 317 0x10fe0545,
318 0x0007f100, 318 0x0007f100,
319 0x0003f007, 319 0x0003f007,
320 0xbd0000d0, 320 0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gk104_grgpc_code[] = {
338 0x02d00103, 338 0x02d00103,
339 0xf104bd00, 339 0xf104bd00,
340 0xf00c30e7, 340 0xf00c30e7,
341 0x24bd50e3, 341 0xe5f050e3,
342 0x44bd34bd, 342 0xbd24bd01,
343/* 0x0430: init_unk_loop */ 343/* 0x0433: init_unk_loop */
344 0xb06821f4, 344 0xf444bd34,
345 0x0bf400f6, 345 0xf6b06821,
346 0x01f7f00f, 346 0x0f0bf400,
347 0xfd04f2bb, 347 0xbb01f7f0,
348 0x30b6054f, 348 0x4ffd04f2,
349/* 0x0445: init_unk_next */ 349 0x0130b605,
350 0x0120b601, 350/* 0x0448: init_unk_next */
351 0xb004e0b6, 351 0xb60120b6,
352 0x1bf40126, 352 0x26b004e0,
353/* 0x0451: init_unk_done */ 353 0xe21bf401,
354 0x070380e2, 354/* 0x0454: init_unk_done */
355 0xf1080480, 355 0x80070380,
356 0xf0010027, 356 0x27f10804,
357 0x22cf0223, 357 0x23f00100,
358 0x9534bd00, 358 0x0022cf02,
359 0x07f10825, 359 0x259534bd,
360 0x03f0c000, 360 0x0007f108,
361 0x0005d001, 361 0x0103f0c0,
362 0x07f104bd, 362 0xbd0005d0,
363 0x03f0c100, 363 0x0007f104,
364 0x0005d001, 364 0x0103f0c1,
365 0x0e9804bd, 365 0xbd0005d0,
366 0x010f9800, 366 0x000e9804,
367 0x015021f5, 367 0xf5010f98,
368 0xbb002fbb, 368 0xbb015021,
369 0x0e98003f, 369 0x3fbb002f,
370 0x020f9801, 370 0x010e9800,
371 0x015021f5, 371 0xf5020f98,
372 0xfd050e98, 372 0x98015021,
373 0x2ebb00ef, 373 0xeffd050e,
374 0x003ebb00, 374 0x002ebb00,
375 0x98020e98, 375 0x98003ebb,
376 0x21f5030f, 376 0x0f98020e,
377 0x0e980150, 377 0x5021f503,
378 0x00effd07, 378 0x070e9801,
379 0xbb002ebb, 379 0xbb00effd,
380 0x35b6003e, 380 0x3ebb002e,
381 0x0007f102, 381 0x0235b600,
382 0x0103f0d3, 382 0xd30007f1,
383 0xbd0003d0, 383 0xd00103f0,
384 0x0825b604,
385 0xb60635b6,
386 0x30b60120,
387 0x0824b601,
388 0xb90834b6,
389 0x21f5022f,
390 0x2fbb02d3,
391 0x003fbb00,
392 0x010007f1,
393 0xd00203f0,
394 0x04bd0003, 384 0x04bd0003,
395 0x29f024bd, 385 0xb60825b6,
396 0x0007f11f, 386 0x20b60635,
397 0x0203f008, 387 0x0130b601,
398 0xbd0002d0, 388 0xb60824b6,
399/* 0x0505: main */ 389 0x2fb90834,
400 0x0031f404, 390 0xd321f502,
401 0xf00028f4, 391 0x002fbb02,
402 0x21f424d7, 392 0xf1003fbb,
403 0xf401f439, 393 0xf0010007,
404 0xf404e4b0, 394 0x03d00203,
405 0x81fe1e18, 395 0xbd04bd00,
406 0x0627f001, 396 0x1f29f024,
407 0x12fd20bd, 397 0x080007f1,
408 0x01e4b604, 398 0xd00203f0,
409 0xfe051efd, 399 0x04bd0002,
410 0x21f50018, 400/* 0x0508: main */
411 0x0ef405fa, 401 0xf40031f4,
412/* 0x0535: main_not_ctx_xfer */ 402 0xd7f00028,
413 0x10ef94d3, 403 0x3921f424,
414 0xf501f5f0, 404 0xb0f401f4,
415 0xf4037e21, 405 0x18f404e4,
416/* 0x0542: ih */ 406 0x0181fe1e,
417 0x80f9c60e, 407 0xbd0627f0,
418 0xf90188fe, 408 0x0412fd20,
419 0xf990f980, 409 0xfd01e4b6,
420 0xf9b0f9a0, 410 0x18fe051e,
421 0xf9e0f9d0, 411 0xfd21f500,
422 0xf104bdf0, 412 0xd30ef405,
423 0xf00200a7, 413/* 0x0538: main_not_ctx_xfer */
424 0xaacf00a3, 414 0xf010ef94,
425 0x04abc400, 415 0x21f501f5,
426 0xf02c0bf4, 416 0x0ef4037e,
427 0xe7f124d7, 417/* 0x0545: ih */
428 0xe3f01a00, 418 0xfe80f9c6,
429 0x00eecf00, 419 0x80f90188,
430 0x1900f7f1, 420 0xa0f990f9,
431 0xcf00f3f0, 421 0xd0f9b0f9,
432 0x21f400ff, 422 0xf0f9e0f9,
433 0x01e7f004, 423 0xa7f104bd,
434 0x1d0007f1, 424 0xa3f00200,
435 0xd00003f0, 425 0x00aacf00,
436 0x04bd000e, 426 0xf404abc4,
437/* 0x0590: ih_no_fifo */ 427 0xd7f02c0b,
438 0x010007f1, 428 0x00e7f124,
439 0xd00003f0, 429 0x00e3f01a,
440 0x04bd000a, 430 0xf100eecf,
441 0xe0fcf0fc, 431 0xf01900f7,
442 0xb0fcd0fc, 432 0xffcf00f3,
443 0x90fca0fc, 433 0x0421f400,
444 0x88fe80fc, 434 0xf101e7f0,
445 0xf480fc00, 435 0xf01d0007,
446 0x01f80032, 436 0x0ed00003,
447/* 0x05b4: hub_barrier_done */ 437/* 0x0593: ih_no_fifo */
448 0x9801f7f0, 438 0xf104bd00,
449 0xfebb040e, 439 0xf0010007,
450 0x02ffb904, 440 0x0ad00003,
451 0x9418e7f1, 441 0xfc04bd00,
452 0xf440e3f0, 442 0xfce0fcf0,
453 0x00f89d21, 443 0xfcb0fcd0,
454/* 0x05cc: ctx_redswitch */ 444 0xfc90fca0,
455 0xf120f7f0, 445 0x0088fe80,
446 0x32f480fc,
447/* 0x05b7: hub_barrier_done */
448 0xf001f800,
449 0x0e9801f7,
450 0x04febb04,
451 0xf102ffb9,
452 0xf09418e7,
453 0x21f440e3,
454/* 0x05cf: ctx_redswitch */
455 0xf000f89d,
456 0x07f120f7,
457 0x03f08500,
458 0x000fd001,
459 0xe7f004bd,
460/* 0x05e1: ctx_redswitch_delay */
461 0x01e2b608,
462 0xf1fd1bf4,
463 0xf10800f5,
464 0xf10200f5,
456 0xf0850007, 465 0xf0850007,
457 0x0fd00103, 466 0x0fd00103,
458 0xf004bd00, 467 0xf804bd00,
459/* 0x05de: ctx_redswitch_delay */ 468/* 0x05fd: ctx_xfer */
460 0xe2b608e7, 469 0x0007f100,
461 0xfd1bf401, 470 0x0203f081,
462 0x0800f5f1, 471 0xbd000fd0,
463 0x0200f5f1, 472 0x0711f404,
464 0x850007f1, 473 0x05cf21f5,
465 0xd00103f0, 474/* 0x0610: ctx_xfer_not_load */
466 0x04bd000f, 475 0x026a21f5,
467/* 0x05fa: ctx_xfer */ 476 0x07f124bd,
468 0x07f100f8, 477 0x03f047fc,
469 0x03f08100, 478 0x0002d002,
470 0x000fd002, 479 0x2cf004bd,
471 0x11f404bd, 480 0x0320b601,
472 0xcc21f507, 481 0x4afc07f1,
473/* 0x060d: ctx_xfer_not_load */ 482 0xd00203f0,
474 0x6a21f505, 483 0x04bd0002,
475 0xf124bd02,
476 0xf047fc07,
477 0x02d00203,
478 0xf004bd00,
479 0x20b6012c,
480 0xfc07f103,
481 0x0203f04a,
482 0xbd0002d0,
483 0x01acf004,
484 0xf102a5f0,
485 0xf00000b7,
486 0x0c9850b3,
487 0x0fc4b604,
488 0x9800bcbb,
489 0x0d98000c,
490 0x00e7f001,
491 0x016f21f5,
492 0xf101acf0,
493 0xf04000b7,
494 0x0c9850b3,
495 0x0fc4b604,
496 0x9800bcbb,
497 0x0d98010c,
498 0x060f9802,
499 0x0800e7f1,
500 0x016f21f5,
501 0xf001acf0, 484 0xf001acf0,
502 0xb7f104a5, 485 0xb7f102a5,
503 0xb3f03000, 486 0xb3f00000,
504 0x040c9850, 487 0x040c9850,
505 0xbb0fc4b6, 488 0xbb0fc4b6,
506 0x0c9800bc, 489 0x0c9800bc,
507 0x030d9802, 490 0x010d9800,
508 0xf1080f98, 491 0xf500e7f0,
509 0xf50200e7, 492 0xf0016f21,
510 0xf5016f21, 493 0xb7f101ac,
511 0xf4025e21, 494 0xb3f04000,
512 0x12f40601, 495 0x040c9850,
513/* 0x06a9: ctx_xfer_post */ 496 0xbb0fc4b6,
514 0x7f21f507, 497 0x0c9800bc,
515/* 0x06ad: ctx_xfer_done */ 498 0x020d9801,
516 0xb421f502, 499 0xf1060f98,
517 0x0000f805, 500 0xf50800e7,
518 0x00000000, 501 0xf0016f21,
502 0xa5f001ac,
503 0x00b7f104,
504 0x50b3f030,
505 0xb6040c98,
506 0xbcbb0fc4,
507 0x020c9800,
508 0x98030d98,
509 0xe7f1080f,
510 0x21f50200,
511 0x21f5016f,
512 0x01f4025e,
513 0x0712f406,
514/* 0x06ac: ctx_xfer_post */
515 0x027f21f5,
516/* 0x06b0: ctx_xfer_done */
517 0x05b721f5,
518 0x000000f8,
519 0x00000000, 519 0x00000000,
520 0x00000000, 520 0x00000000,
521 0x00000000, 521 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
index ee8e54db8fc9..1c6e11b05df2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
@@ -314,7 +314,7 @@ uint32_t gk110_grgpc_code[] = {
314 0x03f01200, 314 0x03f01200,
315 0x0002d000, 315 0x0002d000,
316 0x17f104bd, 316 0x17f104bd,
317 0x10fe0542, 317 0x10fe0545,
318 0x0007f100, 318 0x0007f100,
319 0x0003f007, 319 0x0003f007,
320 0xbd0000d0, 320 0xbd0000d0,
@@ -338,184 +338,184 @@ uint32_t gk110_grgpc_code[] = {
338 0x02d00103, 338 0x02d00103,
339 0xf104bd00, 339 0xf104bd00,
340 0xf00c30e7, 340 0xf00c30e7,
341 0x24bd50e3, 341 0xe5f050e3,
342 0x44bd34bd, 342 0xbd24bd01,
343/* 0x0430: init_unk_loop */ 343/* 0x0433: init_unk_loop */
344 0xb06821f4, 344 0xf444bd34,
345 0x0bf400f6, 345 0xf6b06821,
346 0x01f7f00f, 346 0x0f0bf400,
347 0xfd04f2bb, 347 0xbb01f7f0,
348 0x30b6054f, 348 0x4ffd04f2,
349/* 0x0445: init_unk_next */ 349 0x0130b605,
350 0x0120b601, 350/* 0x0448: init_unk_next */
351 0xb004e0b6, 351 0xb60120b6,
352 0x1bf40226, 352 0x26b004e0,
353/* 0x0451: init_unk_done */ 353 0xe21bf402,
354 0x070380e2, 354/* 0x0454: init_unk_done */
355 0xf1080480, 355 0x80070380,
356 0xf0010027, 356 0x27f10804,
357 0x22cf0223, 357 0x23f00100,
358 0x9534bd00, 358 0x0022cf02,
359 0x07f10825, 359 0x259534bd,
360 0x03f0c000, 360 0x0007f108,
361 0x0005d001, 361 0x0103f0c0,
362 0x07f104bd, 362 0xbd0005d0,
363 0x03f0c100, 363 0x0007f104,
364 0x0005d001, 364 0x0103f0c1,
365 0x0e9804bd, 365 0xbd0005d0,
366 0x010f9800, 366 0x000e9804,
367 0x015021f5, 367 0xf5010f98,
368 0xbb002fbb, 368 0xbb015021,
369 0x0e98003f, 369 0x3fbb002f,
370 0x020f9801, 370 0x010e9800,
371 0x015021f5, 371 0xf5020f98,
372 0xfd050e98, 372 0x98015021,
373 0x2ebb00ef, 373 0xeffd050e,
374 0x003ebb00, 374 0x002ebb00,
375 0x98020e98, 375 0x98003ebb,
376 0x21f5030f, 376 0x0f98020e,
377 0x0e980150, 377 0x5021f503,
378 0x00effd07, 378 0x070e9801,
379 0xbb002ebb, 379 0xbb00effd,
380 0x35b6003e, 380 0x3ebb002e,
381 0x0007f102, 381 0x0235b600,
382 0x0103f0d3, 382 0xd30007f1,
383 0xbd0003d0, 383 0xd00103f0,
384 0x0825b604,
385 0xb60635b6,
386 0x30b60120,
387 0x0824b601,
388 0xb90834b6,
389 0x21f5022f,
390 0x2fbb02d3,
391 0x003fbb00,
392 0x010007f1,
393 0xd00203f0,
394 0x04bd0003, 384 0x04bd0003,
395 0x29f024bd, 385 0xb60825b6,
396 0x0007f11f, 386 0x20b60635,
397 0x0203f030, 387 0x0130b601,
398 0xbd0002d0, 388 0xb60824b6,
399/* 0x0505: main */ 389 0x2fb90834,
400 0x0031f404, 390 0xd321f502,
401 0xf00028f4, 391 0x002fbb02,
402 0x21f424d7, 392 0xf1003fbb,
403 0xf401f439, 393 0xf0010007,
404 0xf404e4b0, 394 0x03d00203,
405 0x81fe1e18, 395 0xbd04bd00,
406 0x0627f001, 396 0x1f29f024,
407 0x12fd20bd, 397 0x300007f1,
408 0x01e4b604, 398 0xd00203f0,
409 0xfe051efd, 399 0x04bd0002,
410 0x21f50018, 400/* 0x0508: main */
411 0x0ef405fa, 401 0xf40031f4,
412/* 0x0535: main_not_ctx_xfer */ 402 0xd7f00028,
413 0x10ef94d3, 403 0x3921f424,
414 0xf501f5f0, 404 0xb0f401f4,
415 0xf4037e21, 405 0x18f404e4,
416/* 0x0542: ih */ 406 0x0181fe1e,
417 0x80f9c60e, 407 0xbd0627f0,
418 0xf90188fe, 408 0x0412fd20,
419 0xf990f980, 409 0xfd01e4b6,
420 0xf9b0f9a0, 410 0x18fe051e,
421 0xf9e0f9d0, 411 0xfd21f500,
422 0xf104bdf0, 412 0xd30ef405,
423 0xf00200a7, 413/* 0x0538: main_not_ctx_xfer */
424 0xaacf00a3, 414 0xf010ef94,
425 0x04abc400, 415 0x21f501f5,
426 0xf02c0bf4, 416 0x0ef4037e,
427 0xe7f124d7, 417/* 0x0545: ih */
428 0xe3f01a00, 418 0xfe80f9c6,
429 0x00eecf00, 419 0x80f90188,
430 0x1900f7f1, 420 0xa0f990f9,
431 0xcf00f3f0, 421 0xd0f9b0f9,
432 0x21f400ff, 422 0xf0f9e0f9,
433 0x01e7f004, 423 0xa7f104bd,
434 0x1d0007f1, 424 0xa3f00200,
435 0xd00003f0, 425 0x00aacf00,
436 0x04bd000e, 426 0xf404abc4,
437/* 0x0590: ih_no_fifo */ 427 0xd7f02c0b,
438 0x010007f1, 428 0x00e7f124,
439 0xd00003f0, 429 0x00e3f01a,
440 0x04bd000a, 430 0xf100eecf,
441 0xe0fcf0fc, 431 0xf01900f7,
442 0xb0fcd0fc, 432 0xffcf00f3,
443 0x90fca0fc, 433 0x0421f400,
444 0x88fe80fc, 434 0xf101e7f0,
445 0xf480fc00, 435 0xf01d0007,
446 0x01f80032, 436 0x0ed00003,
447/* 0x05b4: hub_barrier_done */ 437/* 0x0593: ih_no_fifo */
448 0x9801f7f0, 438 0xf104bd00,
449 0xfebb040e, 439 0xf0010007,
450 0x02ffb904, 440 0x0ad00003,
451 0x9418e7f1, 441 0xfc04bd00,
452 0xf440e3f0, 442 0xfce0fcf0,
453 0x00f89d21, 443 0xfcb0fcd0,
454/* 0x05cc: ctx_redswitch */ 444 0xfc90fca0,
455 0xf120f7f0, 445 0x0088fe80,
446 0x32f480fc,
447/* 0x05b7: hub_barrier_done */
448 0xf001f800,
449 0x0e9801f7,
450 0x04febb04,
451 0xf102ffb9,
452 0xf09418e7,
453 0x21f440e3,
454/* 0x05cf: ctx_redswitch */
455 0xf000f89d,
456 0x07f120f7,
457 0x03f08500,
458 0x000fd001,
459 0xe7f004bd,
460/* 0x05e1: ctx_redswitch_delay */
461 0x01e2b608,
462 0xf1fd1bf4,
463 0xf10800f5,
464 0xf10200f5,
456 0xf0850007, 465 0xf0850007,
457 0x0fd00103, 466 0x0fd00103,
458 0xf004bd00, 467 0xf804bd00,
459/* 0x05de: ctx_redswitch_delay */ 468/* 0x05fd: ctx_xfer */
460 0xe2b608e7, 469 0x0007f100,
461 0xfd1bf401, 470 0x0203f081,
462 0x0800f5f1, 471 0xbd000fd0,
463 0x0200f5f1, 472 0x0711f404,
464 0x850007f1, 473 0x05cf21f5,
465 0xd00103f0, 474/* 0x0610: ctx_xfer_not_load */
466 0x04bd000f, 475 0x026a21f5,
467/* 0x05fa: ctx_xfer */ 476 0x07f124bd,
468 0x07f100f8, 477 0x03f047fc,
469 0x03f08100, 478 0x0002d002,
470 0x000fd002, 479 0x2cf004bd,
471 0x11f404bd, 480 0x0320b601,
472 0xcc21f507, 481 0x4afc07f1,
473/* 0x060d: ctx_xfer_not_load */ 482 0xd00203f0,
474 0x6a21f505, 483 0x04bd0002,
475 0xf124bd02,
476 0xf047fc07,
477 0x02d00203,
478 0xf004bd00,
479 0x20b6012c,
480 0xfc07f103,
481 0x0203f04a,
482 0xbd0002d0,
483 0x01acf004,
484 0xf102a5f0,
485 0xf00000b7,
486 0x0c9850b3,
487 0x0fc4b604,
488 0x9800bcbb,
489 0x0d98000c,
490 0x00e7f001,
491 0x016f21f5,
492 0xf101acf0,
493 0xf04000b7,
494 0x0c9850b3,
495 0x0fc4b604,
496 0x9800bcbb,
497 0x0d98010c,
498 0x060f9802,
499 0x0800e7f1,
500 0x016f21f5,
501 0xf001acf0, 484 0xf001acf0,
502 0xb7f104a5, 485 0xb7f102a5,
503 0xb3f03000, 486 0xb3f00000,
504 0x040c9850, 487 0x040c9850,
505 0xbb0fc4b6, 488 0xbb0fc4b6,
506 0x0c9800bc, 489 0x0c9800bc,
507 0x030d9802, 490 0x010d9800,
508 0xf1080f98, 491 0xf500e7f0,
509 0xf50200e7, 492 0xf0016f21,
510 0xf5016f21, 493 0xb7f101ac,
511 0xf4025e21, 494 0xb3f04000,
512 0x12f40601, 495 0x040c9850,
513/* 0x06a9: ctx_xfer_post */ 496 0xbb0fc4b6,
514 0x7f21f507, 497 0x0c9800bc,
515/* 0x06ad: ctx_xfer_done */ 498 0x020d9801,
516 0xb421f502, 499 0xf1060f98,
517 0x0000f805, 500 0xf50800e7,
518 0x00000000, 501 0xf0016f21,
502 0xa5f001ac,
503 0x00b7f104,
504 0x50b3f030,
505 0xb6040c98,
506 0xbcbb0fc4,
507 0x020c9800,
508 0x98030d98,
509 0xe7f1080f,
510 0x21f50200,
511 0x21f5016f,
512 0x01f4025e,
513 0x0712f406,
514/* 0x06ac: ctx_xfer_post */
515 0x027f21f5,
516/* 0x06b0: ctx_xfer_done */
517 0x05b721f5,
518 0x000000f8,
519 0x00000000, 519 0x00000000,
520 0x00000000, 520 0x00000000,
521 0x00000000, 521 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
index fbcc342f896f..84af7ec6a78e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
@@ -276,7 +276,7 @@ uint32_t gk208_grgpc_code[] = {
276 0x02020014, 276 0x02020014,
277 0xf6120040, 277 0xf6120040,
278 0x04bd0002, 278 0x04bd0002,
279 0xfe048141, 279 0xfe048441,
280 0x00400010, 280 0x00400010,
281 0x0000f607, 281 0x0000f607,
282 0x040204bd, 282 0x040204bd,
@@ -295,165 +295,165 @@ uint32_t gk208_grgpc_code[] = {
295 0x01c90080, 295 0x01c90080,
296 0xbd0002f6, 296 0xbd0002f6,
297 0x0c308e04, 297 0x0c308e04,
298 0xbd24bd50, 298 0x01e5f050,
299/* 0x0383: init_unk_loop */ 299 0x34bd24bd,
300 0x7e44bd34, 300/* 0x0386: init_unk_loop */
301 0xb0000065, 301 0x657e44bd,
302 0x0bf400f6, 302 0xf6b00000,
303 0xbb010f0e, 303 0x0e0bf400,
304 0x4ffd04f2, 304 0xf2bb010f,
305 0x0130b605, 305 0x054ffd04,
306/* 0x0398: init_unk_next */ 306/* 0x039b: init_unk_next */
307 0xb60120b6, 307 0xb60130b6,
308 0x26b004e0, 308 0xe0b60120,
309 0xe21bf401, 309 0x0126b004,
310/* 0x03a4: init_unk_done */ 310/* 0x03a7: init_unk_done */
311 0xb50703b5, 311 0xb5e21bf4,
312 0x00820804, 312 0x04b50703,
313 0x22cf0201, 313 0x01008208,
314 0x9534bd00, 314 0x0022cf02,
315 0x00800825, 315 0x259534bd,
316 0x05f601c0, 316 0xc0008008,
317 0x8004bd00, 317 0x0005f601,
318 0xf601c100, 318 0x008004bd,
319 0x04bd0005, 319 0x05f601c1,
320 0x98000e98, 320 0x9804bd00,
321 0x207e010f, 321 0x0f98000e,
322 0x2fbb0001, 322 0x01207e01,
323 0x003fbb00, 323 0x002fbb00,
324 0x98010e98, 324 0x98003fbb,
325 0x207e020f, 325 0x0f98010e,
326 0x0e980001, 326 0x01207e02,
327 0x00effd05, 327 0x050e9800,
328 0xbb002ebb, 328 0xbb00effd,
329 0x0e98003e, 329 0x3ebb002e,
330 0x030f9802, 330 0x020e9800,
331 0x0001207e, 331 0x7e030f98,
332 0xfd070e98, 332 0x98000120,
333 0x2ebb00ef, 333 0xeffd070e,
334 0x003ebb00, 334 0x002ebb00,
335 0x800235b6, 335 0xb6003ebb,
336 0xf601d300, 336 0x00800235,
337 0x04bd0003, 337 0x03f601d3,
338 0xb60825b6, 338 0xb604bd00,
339 0x20b60635, 339 0x35b60825,
340 0x0130b601, 340 0x0120b606,
341 0xb60824b6, 341 0xb60130b6,
342 0x2fb20834, 342 0x34b60824,
343 0x0002687e, 343 0x7e2fb208,
344 0xbb002fbb, 344 0xbb000268,
345 0x0080003f, 345 0x3fbb002f,
346 0x03f60201, 346 0x01008000,
347 0xbd04bd00, 347 0x0003f602,
348 0x1f29f024, 348 0x24bd04bd,
349 0x02300080, 349 0x801f29f0,
350 0xbd0002f6, 350 0xf6023000,
351/* 0x0445: main */ 351 0x04bd0002,
352 0x0031f404, 352/* 0x0448: main */
353 0x0d0028f4, 353 0xf40031f4,
354 0x00377e24, 354 0x240d0028,
355 0xf401f400, 355 0x0000377e,
356 0xf404e4b0, 356 0xb0f401f4,
357 0x81fe1d18, 357 0x18f404e4,
358 0xbd060201, 358 0x0181fe1d,
359 0x0412fd20, 359 0x20bd0602,
360 0xfd01e4b6, 360 0xb60412fd,
361 0x18fe051e, 361 0x1efd01e4,
362 0x05187e00, 362 0x0018fe05,
363 0xd40ef400, 363 0x00051b7e,
364/* 0x0474: main_not_ctx_xfer */ 364/* 0x0477: main_not_ctx_xfer */
365 0xf010ef94, 365 0x94d40ef4,
366 0xf87e01f5, 366 0xf5f010ef,
367 0x0ef40002, 367 0x02f87e01,
368/* 0x0481: ih */ 368 0xc70ef400,
369 0xfe80f9c7, 369/* 0x0484: ih */
370 0x80f90188, 370 0x88fe80f9,
371 0xa0f990f9, 371 0xf980f901,
372 0xd0f9b0f9, 372 0xf9a0f990,
373 0xf0f9e0f9, 373 0xf9d0f9b0,
374 0x004a04bd, 374 0xbdf0f9e0,
375 0x00aacf02, 375 0x02004a04,
376 0xf404abc4, 376 0xc400aacf,
377 0x240d1f0b, 377 0x0bf404ab,
378 0xcf1a004e, 378 0x4e240d1f,
379 0x004f00ee, 379 0xeecf1a00,
380 0x00ffcf19, 380 0x19004f00,
381 0x0000047e, 381 0x7e00ffcf,
382 0x0040010e, 382 0x0e000004,
383 0x000ef61d, 383 0x1d004001,
384/* 0x04be: ih_no_fifo */ 384 0xbd000ef6,
385 0x004004bd, 385/* 0x04c1: ih_no_fifo */
386 0x000af601, 386 0x01004004,
387 0xf0fc04bd, 387 0xbd000af6,
388 0xd0fce0fc, 388 0xfcf0fc04,
389 0xa0fcb0fc, 389 0xfcd0fce0,
390 0x80fc90fc, 390 0xfca0fcb0,
391 0xfc0088fe, 391 0xfe80fc90,
392 0x0032f480, 392 0x80fc0088,
393/* 0x04de: hub_barrier_done */ 393 0xf80032f4,
394 0x010f01f8, 394/* 0x04e1: hub_barrier_done */
395 0xbb040e98, 395 0x98010f01,
396 0xffb204fe, 396 0xfebb040e,
397 0x4094188e, 397 0x8effb204,
398 0x00008f7e, 398 0x7e409418,
399/* 0x04f2: ctx_redswitch */ 399 0xf800008f,
400 0x200f00f8, 400/* 0x04f5: ctx_redswitch */
401 0x80200f00,
402 0xf6018500,
403 0x04bd000f,
404/* 0x0502: ctx_redswitch_delay */
405 0xe2b6080e,
406 0xfd1bf401,
407 0x0800f5f1,
408 0x0200f5f1,
401 0x01850080, 409 0x01850080,
402 0xbd000ff6, 410 0xbd000ff6,
403/* 0x04ff: ctx_redswitch_delay */ 411/* 0x051b: ctx_xfer */
404 0xb6080e04, 412 0x8000f804,
405 0x1bf401e2, 413 0xf6028100,
406 0x00f5f1fd, 414 0x04bd000f,
407 0x00f5f108, 415 0x7e0711f4,
408 0x85008002, 416/* 0x052b: ctx_xfer_not_load */
409 0x000ff601, 417 0x7e0004f5,
410 0x00f804bd, 418 0xbd000216,
411/* 0x0518: ctx_xfer */ 419 0x47fc8024,
412 0x02810080,
413 0xbd000ff6,
414 0x0711f404,
415 0x0004f27e,
416/* 0x0528: ctx_xfer_not_load */
417 0x0002167e,
418 0xfc8024bd,
419 0x02f60247,
420 0xf004bd00,
421 0x20b6012c,
422 0x4afc8003,
423 0x0002f602, 420 0x0002f602,
424 0xacf004bd, 421 0x2cf004bd,
425 0x02a5f001, 422 0x0320b601,
426 0x5000008b, 423 0x024afc80,
427 0xb6040c98, 424 0xbd0002f6,
428 0xbcbb0fc4, 425 0x01acf004,
429 0x000c9800, 426 0x8b02a5f0,
430 0x0e010d98, 427 0x98500000,
431 0x013d7e00,
432 0x01acf000,
433 0x5040008b,
434 0xb6040c98,
435 0xbcbb0fc4,
436 0x010c9800,
437 0x98020d98,
438 0x004e060f,
439 0x013d7e08,
440 0x01acf000,
441 0x8b04a5f0,
442 0x98503000,
443 0xc4b6040c, 428 0xc4b6040c,
444 0x00bcbb0f, 429 0x00bcbb0f,
445 0x98020c98, 430 0x98000c98,
446 0x0f98030d, 431 0x000e010d,
447 0x02004e08,
448 0x00013d7e, 432 0x00013d7e,
449 0x00020a7e, 433 0x8b01acf0,
450 0xf40601f4, 434 0x98504000,
451/* 0x05b2: ctx_xfer_post */ 435 0xc4b6040c,
452 0x277e0712, 436 0x00bcbb0f,
453/* 0x05b6: ctx_xfer_done */ 437 0x98010c98,
454 0xde7e0002, 438 0x0f98020d,
455 0x00f80004, 439 0x08004e06,
456 0x00000000, 440 0x00013d7e,
441 0xf001acf0,
442 0x008b04a5,
443 0x0c985030,
444 0x0fc4b604,
445 0x9800bcbb,
446 0x0d98020c,
447 0x080f9803,
448 0x7e02004e,
449 0x7e00013d,
450 0xf400020a,
451 0x12f40601,
452/* 0x05b5: ctx_xfer_post */
453 0x02277e07,
454/* 0x05b9: ctx_xfer_done */
455 0x04e17e00,
456 0x0000f800,
457 0x00000000, 457 0x00000000,
458 0x00000000, 458 0x00000000,
459 0x00000000, 459 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
index 51f5c3c6e966..11bf363a6ae9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
@@ -289,7 +289,7 @@ uint32_t gm107_grgpc_code[] = {
289 0x020014fe, 289 0x020014fe,
290 0x12004002, 290 0x12004002,
291 0xbd0002f6, 291 0xbd0002f6,
292 0x05b04104, 292 0x05b34104,
293 0x400010fe, 293 0x400010fe,
294 0x00f60700, 294 0x00f60700,
295 0x0204bd00, 295 0x0204bd00,
@@ -308,259 +308,259 @@ uint32_t gm107_grgpc_code[] = {
308 0xc900800f, 308 0xc900800f,
309 0x0002f601, 309 0x0002f601,
310 0x308e04bd, 310 0x308e04bd,
311 0x24bd500c, 311 0xe5f0500c,
312 0x44bd34bd, 312 0xbd24bd01,
313/* 0x03b0: init_unk_loop */ 313/* 0x03b3: init_unk_loop */
314 0x0000657e, 314 0x7e44bd34,
315 0xf400f6b0, 315 0xb0000065,
316 0x010f0e0b, 316 0x0bf400f6,
317 0xfd04f2bb, 317 0xbb010f0e,
318 0x30b6054f, 318 0x4ffd04f2,
319/* 0x03c5: init_unk_next */ 319 0x0130b605,
320 0x0120b601, 320/* 0x03c8: init_unk_next */
321 0xb004e0b6, 321 0xb60120b6,
322 0x1bf40226, 322 0x26b004e0,
323/* 0x03d1: init_unk_done */ 323 0xe21bf402,
324 0x0703b5e2, 324/* 0x03d4: init_unk_done */
325 0x820804b5, 325 0xb50703b5,
326 0xcf020100, 326 0x00820804,
327 0x34bd0022, 327 0x22cf0201,
328 0x80082595, 328 0x9534bd00,
329 0xf601c000, 329 0x00800825,
330 0x05f601c0,
331 0x8004bd00,
332 0xf601c100,
330 0x04bd0005, 333 0x04bd0005,
331 0x01c10080, 334 0x98000e98,
332 0xbd0005f6, 335 0x207e010f,
333 0x000e9804, 336 0x2fbb0001,
334 0x7e010f98, 337 0x003fbb00,
335 0xbb000120, 338 0x98010e98,
336 0x3fbb002f, 339 0x207e020f,
337 0x010e9800, 340 0x0e980001,
338 0x7e020f98, 341 0x00effd05,
339 0x98000120, 342 0xbb002ebb,
340 0xeffd050e, 343 0x0e98003e,
341 0x002ebb00, 344 0x030f9802,
342 0x98003ebb, 345 0x0001207e,
343 0x0f98020e, 346 0xfd070e98,
344 0x01207e03, 347 0x2ebb00ef,
345 0x070e9800, 348 0x003ebb00,
346 0xbb00effd, 349 0x800235b6,
347 0x3ebb002e, 350 0xf601d300,
348 0x0235b600, 351 0x04bd0003,
349 0x01d30080, 352 0xb60825b6,
350 0xbd0003f6, 353 0x20b60635,
351 0x0825b604, 354 0x0130b601,
352 0xb60635b6, 355 0xb60824b6,
353 0x30b60120, 356 0x2fb20834,
354 0x0824b601, 357 0x0002687e,
355 0xb20834b6, 358 0xbb002fbb,
356 0x02687e2f, 359 0x3f0f003f,
357 0x002fbb00, 360 0x501d608e,
358 0x0f003fbb, 361 0xb201e5f0,
359 0x8effb23f, 362 0x008f7eff,
360 0xf0501d60, 363 0x8e0c0f00,
361 0x8f7e01e5,
362 0x0c0f0000,
363 0xa88effb2,
364 0xe5f0501d,
365 0x008f7e01,
366 0x03147e00,
367 0xb23f0f00,
368 0x1d608eff,
369 0x01e5f050,
370 0x00008f7e,
371 0xffb2000f,
372 0x501d9c8e,
373 0x7e01e5f0,
374 0x0f00008f,
375 0x03147e01,
376 0x8effb200,
377 0xf0501da8, 364 0xf0501da8,
378 0x8f7e01e5, 365 0xffb201e5,
379 0xff0f0000, 366 0x00008f7e,
380 0x988effb2, 367 0x0003147e,
368 0x608e3f0f,
381 0xe5f0501d, 369 0xe5f0501d,
382 0x008f7e01, 370 0x7effb201,
383 0xb2020f00, 371 0x0f00008f,
384 0x1da88eff, 372 0x1d9c8e00,
385 0x01e5f050, 373 0x01e5f050,
386 0x00008f7e, 374 0x8f7effb2,
375 0x010f0000,
387 0x0003147e, 376 0x0003147e,
388 0x85050498, 377 0x501da88e,
389 0x98504000, 378 0xb201e5f0,
390 0x64b60406, 379 0x008f7eff,
391 0x0056bb0f, 380 0x8eff0f00,
392/* 0x04e0: tpc_strand_init_tpc_loop */ 381 0xf0501d98,
393 0x05705eb8, 382 0xffb201e5,
394 0x00657e00,
395 0xbdf6b200,
396/* 0x04ed: tpc_strand_init_idx_loop */
397 0x605eb874,
398 0x7fb20005,
399 0x00008f7e,
400 0x05885eb8,
401 0x082f9500,
402 0x00008f7e,
403 0x058c5eb8,
404 0x082f9500,
405 0x00008f7e, 383 0x00008f7e,
406 0x05905eb8, 384 0xa88e020f,
407 0x00657e00,
408 0x06f5b600,
409 0xb601f0b6,
410 0x2fbb08f4,
411 0x003fbb00,
412 0xb60170b6,
413 0x1bf40162,
414 0x0050b7bf,
415 0x0142b608,
416 0x0fa81bf4,
417 0x8effb23f,
418 0xf0501d60,
419 0x8f7e01e5,
420 0x0d0f0000,
421 0xa88effb2,
422 0xe5f0501d, 385 0xe5f0501d,
423 0x008f7e01, 386 0x7effb201,
424 0x03147e00, 387 0x7e00008f,
425 0x01008000, 388 0x98000314,
426 0x0003f602, 389 0x00850504,
427 0x24bd04bd, 390 0x06985040,
428 0x801f29f0, 391 0x0f64b604,
429 0xf6023000, 392/* 0x04e3: tpc_strand_init_tpc_loop */
430 0x04bd0002, 393 0xb80056bb,
431/* 0x0574: main */ 394 0x0005705e,
432 0xf40031f4, 395 0x0000657e,
433 0x240d0028, 396 0x74bdf6b2,
434 0x0000377e, 397/* 0x04f0: tpc_strand_init_idx_loop */
435 0xb0f401f4, 398 0x05605eb8,
436 0x18f404e4, 399 0x7e7fb200,
437 0x0181fe1d, 400 0xb800008f,
438 0x20bd0602, 401 0x0005885e,
439 0xb60412fd, 402 0x7e082f95,
440 0x1efd01e4, 403 0xb800008f,
441 0x0018fe05, 404 0x00058c5e,
442 0x0006477e, 405 0x7e082f95,
443/* 0x05a3: main_not_ctx_xfer */ 406 0xb800008f,
444 0x94d40ef4, 407 0x0005905e,
445 0xf5f010ef, 408 0x0000657e,
446 0x02f87e01, 409 0xb606f5b6,
447 0xc70ef400, 410 0xf4b601f0,
448/* 0x05b0: ih */ 411 0x002fbb08,
449 0x88fe80f9, 412 0xb6003fbb,
450 0xf980f901, 413 0x62b60170,
451 0xf9a0f990, 414 0xbf1bf401,
452 0xf9d0f9b0, 415 0x080050b7,
453 0xbdf0f9e0, 416 0xf40142b6,
454 0x02004a04, 417 0x3f0fa81b,
455 0xc400aacf, 418 0x501d608e,
456 0x0bf404ab, 419 0xb201e5f0,
457 0x4e240d1f, 420 0x008f7eff,
458 0xeecf1a00, 421 0x8e0d0f00,
459 0x19004f00, 422 0xf0501da8,
460 0x7e00ffcf, 423 0xffb201e5,
461 0x0e000004, 424 0x00008f7e,
462 0x1d004001, 425 0x0003147e,
463 0xbd000ef6, 426 0x02010080,
464/* 0x05ed: ih_no_fifo */ 427 0xbd0003f6,
465 0x01004004, 428 0xf024bd04,
466 0xbd000af6, 429 0x00801f29,
467 0xfcf0fc04, 430 0x02f60230,
468 0xfcd0fce0, 431/* 0x0577: main */
469 0xfca0fcb0, 432 0xf404bd00,
470 0xfe80fc90, 433 0x28f40031,
471 0x80fc0088, 434 0x7e240d00,
472 0xf80032f4, 435 0xf4000037,
473/* 0x060d: hub_barrier_done */ 436 0xe4b0f401,
474 0x98010f01, 437 0x1d18f404,
475 0xfebb040e, 438 0x020181fe,
476 0x8effb204, 439 0xfd20bd06,
477 0x7e409418, 440 0xe4b60412,
478 0xf800008f, 441 0x051efd01,
479/* 0x0621: ctx_redswitch */ 442 0x7e0018fe,
480 0x80200f00, 443 0xf400064a,
444/* 0x05a6: main_not_ctx_xfer */
445 0xef94d40e,
446 0x01f5f010,
447 0x0002f87e,
448/* 0x05b3: ih */
449 0xf9c70ef4,
450 0x0188fe80,
451 0x90f980f9,
452 0xb0f9a0f9,
453 0xe0f9d0f9,
454 0x04bdf0f9,
455 0xcf02004a,
456 0xabc400aa,
457 0x1f0bf404,
458 0x004e240d,
459 0x00eecf1a,
460 0xcf19004f,
461 0x047e00ff,
462 0x010e0000,
463 0xf61d0040,
464 0x04bd000e,
465/* 0x05f0: ih_no_fifo */
466 0xf6010040,
467 0x04bd000a,
468 0xe0fcf0fc,
469 0xb0fcd0fc,
470 0x90fca0fc,
471 0x88fe80fc,
472 0xf480fc00,
473 0x01f80032,
474/* 0x0610: hub_barrier_done */
475 0x0e98010f,
476 0x04febb04,
477 0x188effb2,
478 0x8f7e4094,
479 0x00f80000,
480/* 0x0624: ctx_redswitch */
481 0x0080200f,
482 0x0ff60185,
483 0x0e04bd00,
484/* 0x0631: ctx_redswitch_delay */
485 0x01e2b608,
486 0xf1fd1bf4,
487 0xf10800f5,
488 0x800200f5,
481 0xf6018500, 489 0xf6018500,
482 0x04bd000f, 490 0x04bd000f,
483/* 0x062e: ctx_redswitch_delay */ 491/* 0x064a: ctx_xfer */
484 0xe2b6080e, 492 0x008000f8,
485 0xfd1bf401, 493 0x0ff60281,
486 0x0800f5f1, 494 0x8e04bd00,
487 0x0200f5f1, 495 0xf0501dc4,
488 0x01850080, 496 0xffb201e5,
489 0xbd000ff6, 497 0x00008f7e,
490/* 0x0647: ctx_xfer */ 498 0x7e0711f4,
491 0x8000f804, 499/* 0x0667: ctx_xfer_not_load */
492 0xf6028100, 500 0x7e000624,
493 0x04bd000f, 501 0xbd000216,
494 0xc48effb2, 502 0x47fc8024,
495 0xe5f0501d,
496 0x008f7e01,
497 0x0711f400,
498 0x0006217e,
499/* 0x0664: ctx_xfer_not_load */
500 0x0002167e,
501 0xfc8024bd,
502 0x02f60247,
503 0xf004bd00,
504 0x20b6012c,
505 0x4afc8003,
506 0x0002f602, 503 0x0002f602,
507 0x0c0f04bd, 504 0x2cf004bd,
508 0xa88effb2, 505 0x0320b601,
509 0xe5f0501d, 506 0x024afc80,
510 0x008f7e01, 507 0xbd0002f6,
511 0x03147e00, 508 0x8e0c0f04,
512 0xb23f0f00, 509 0xf0501da8,
513 0x1d608eff, 510 0xffb201e5,
514 0x01e5f050,
515 0x00008f7e, 511 0x00008f7e,
516 0xffb2000f, 512 0x0003147e,
517 0x501d9c8e, 513 0x608e3f0f,
518 0x7e01e5f0, 514 0xe5f0501d,
515 0x7effb201,
519 0x0f00008f, 516 0x0f00008f,
520 0x03147e01, 517 0x1d9c8e00,
521 0x01fcf000,
522 0xb203f0b6,
523 0x1da88eff,
524 0x01e5f050, 518 0x01e5f050,
525 0x00008f7e, 519 0x8f7effb2,
526 0xf001acf0, 520 0x010f0000,
527 0x008b02a5, 521 0x0003147e,
528 0x0c985000, 522 0xb601fcf0,
529 0x0fc4b604, 523 0xa88e03f0,
530 0x9800bcbb, 524 0xe5f0501d,
531 0x0d98000c, 525 0x7effb201,
532 0x7e000e01, 526 0xf000008f,
533 0xf000013d,
534 0x008b01ac,
535 0x0c985040,
536 0x0fc4b604,
537 0x9800bcbb,
538 0x0d98010c,
539 0x060f9802,
540 0x7e08004e,
541 0xf000013d,
542 0xa5f001ac, 527 0xa5f001ac,
543 0x30008b04, 528 0x00008b02,
544 0x040c9850, 529 0x040c9850,
545 0xbb0fc4b6, 530 0xbb0fc4b6,
546 0x0c9800bc, 531 0x0c9800bc,
547 0x030d9802, 532 0x010d9800,
548 0x4e080f98, 533 0x3d7e000e,
549 0x3d7e0200, 534 0xacf00001,
550 0x0a7e0001, 535 0x40008b01,
551 0x147e0002, 536 0x040c9850,
552 0x01f40003, 537 0xbb0fc4b6,
553 0x1a12f406, 538 0x0c9800bc,
554/* 0x073c: ctx_xfer_post */ 539 0x020d9801,
555 0x0002277e, 540 0x4e060f98,
556 0xffb20d0f, 541 0x3d7e0800,
557 0x501da88e, 542 0xacf00001,
558 0x7e01e5f0, 543 0x04a5f001,
559 0x7e00008f, 544 0x5030008b,
560/* 0x0753: ctx_xfer_done */ 545 0xb6040c98,
561 0x7e000314, 546 0xbcbb0fc4,
562 0xf800060d, 547 0x020c9800,
563 0x00000000, 548 0x98030d98,
549 0x004e080f,
550 0x013d7e02,
551 0x020a7e00,
552 0x03147e00,
553 0x0601f400,
554/* 0x073f: ctx_xfer_post */
555 0x7e1a12f4,
556 0x0f000227,
557 0x1da88e0d,
558 0x01e5f050,
559 0x8f7effb2,
560 0x147e0000,
561/* 0x0756: ctx_xfer_done */
562 0x107e0003,
563 0x00f80006,
564 0x00000000, 564 0x00000000,
565 0x00000000, 565 0x00000000,
566 0x00000000, 566 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index dda7a7d224c9..9f5dfc85147a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -143,7 +143,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
143static int 143static int
144gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) 144gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
145{ 145{
146 struct gf100_gr *gr = (void *)object->engine; 146 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
147 union { 147 union {
148 struct fermi_a_zbc_color_v0 v0; 148 struct fermi_a_zbc_color_v0 v0;
149 } *args = data; 149 } *args = data;
@@ -189,7 +189,7 @@ gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
189static int 189static int
190gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) 190gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
191{ 191{
192 struct gf100_gr *gr = (void *)object->engine; 192 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
193 union { 193 union {
194 struct fermi_a_zbc_depth_v0 v0; 194 struct fermi_a_zbc_depth_v0 v0;
195 } *args = data; 195 } *args = data;
@@ -1530,6 +1530,8 @@ gf100_gr_oneinit(struct nvkm_gr *base)
1530 gr->ppc_nr[i] = gr->func->ppc_nr; 1530 gr->ppc_nr[i] = gr->func->ppc_nr;
1531 for (j = 0; j < gr->ppc_nr[i]; j++) { 1531 for (j = 0; j < gr->ppc_nr[i]; j++) {
1532 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); 1532 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
1533 if (mask)
1534 gr->ppc_mask[i] |= (1 << j);
1533 gr->ppc_tpc_nr[i][j] = hweight8(mask); 1535 gr->ppc_tpc_nr[i][j] = hweight8(mask);
1534 } 1536 }
1535 } 1537 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
index 4611961b1187..02e78b8d93f6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -97,6 +97,7 @@ struct gf100_gr {
97 u8 tpc_nr[GPC_MAX]; 97 u8 tpc_nr[GPC_MAX];
98 u8 tpc_total; 98 u8 tpc_total;
99 u8 ppc_nr[GPC_MAX]; 99 u8 ppc_nr[GPC_MAX];
100 u8 ppc_mask[GPC_MAX];
100 u8 ppc_tpc_nr[GPC_MAX][4]; 101 u8 ppc_tpc_nr[GPC_MAX][4];
101 102
102 struct nvkm_memory *unk4188b4; 103 struct nvkm_memory *unk4188b4;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
index 895ba74057d4..1d7dd38292b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
@@ -97,7 +97,9 @@ static void *
97nvkm_instobj_dtor(struct nvkm_memory *memory) 97nvkm_instobj_dtor(struct nvkm_memory *memory)
98{ 98{
99 struct nvkm_instobj *iobj = nvkm_instobj(memory); 99 struct nvkm_instobj *iobj = nvkm_instobj(memory);
100 spin_lock(&iobj->imem->lock);
100 list_del(&iobj->head); 101 list_del(&iobj->head);
102 spin_unlock(&iobj->imem->lock);
101 nvkm_memory_del(&iobj->parent); 103 nvkm_memory_del(&iobj->parent);
102 return iobj; 104 return iobj;
103} 105}
@@ -190,7 +192,9 @@ nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero,
190 nvkm_memory_ctor(&nvkm_instobj_func_slow, &iobj->memory); 192 nvkm_memory_ctor(&nvkm_instobj_func_slow, &iobj->memory);
191 iobj->parent = memory; 193 iobj->parent = memory;
192 iobj->imem = imem; 194 iobj->imem = imem;
195 spin_lock(&iobj->imem->lock);
193 list_add_tail(&iobj->head, &imem->list); 196 list_add_tail(&iobj->head, &imem->list);
197 spin_unlock(&iobj->imem->lock);
194 memory = &iobj->memory; 198 memory = &iobj->memory;
195 } 199 }
196 200
@@ -309,5 +313,6 @@ nvkm_instmem_ctor(const struct nvkm_instmem_func *func,
309{ 313{
310 nvkm_subdev_ctor(&nvkm_instmem, device, index, 0, &imem->subdev); 314 nvkm_subdev_ctor(&nvkm_instmem, device, index, 0, &imem->subdev);
311 imem->func = func; 315 imem->func = func;
316 spin_lock_init(&imem->lock);
312 INIT_LIST_HEAD(&imem->list); 317 INIT_LIST_HEAD(&imem->list);
313} 318}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
index b61509e26ec9..b735173a18ff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c
@@ -59,7 +59,7 @@ gk104_volt_set(struct nvkm_volt *base, u32 uv)
59 duty = (uv - bios->base) * div / bios->pwm_range; 59 duty = (uv - bios->base) * div / bios->pwm_range;
60 60
61 nvkm_wr32(device, 0x20340, div); 61 nvkm_wr32(device, 0x20340, div);
62 nvkm_wr32(device, 0x20344, 0x8000000 | duty); 62 nvkm_wr32(device, 0x20344, 0x80000000 | duty);
63 63
64 return 0; 64 return 0;
65} 65}
diff --git a/drivers/gpu/drm/radeon/rv730_dpm.c b/drivers/gpu/drm/radeon/rv730_dpm.c
index 3f5e1cf138ba..d37ba2cb886e 100644
--- a/drivers/gpu/drm/radeon/rv730_dpm.c
+++ b/drivers/gpu/drm/radeon/rv730_dpm.c
@@ -464,7 +464,7 @@ void rv730_stop_dpm(struct radeon_device *rdev)
464 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled); 464 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
465 465
466 if (result != PPSMC_Result_OK) 466 if (result != PPSMC_Result_OK)
467 DRM_ERROR("Could not force DPM to low\n"); 467 DRM_DEBUG("Could not force DPM to low\n");
468 468
469 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 469 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
470 470
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index b9c770745a7a..e830c8935db0 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -193,7 +193,7 @@ void rv770_stop_dpm(struct radeon_device *rdev)
193 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled); 193 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
194 194
195 if (result != PPSMC_Result_OK) 195 if (result != PPSMC_Result_OK)
196 DRM_ERROR("Could not force DPM to low.\n"); 196 DRM_DEBUG("Could not force DPM to low.\n");
197 197
198 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 198 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
199 199
@@ -1418,7 +1418,7 @@ int rv770_resume_smc(struct radeon_device *rdev)
1418int rv770_set_sw_state(struct radeon_device *rdev) 1418int rv770_set_sw_state(struct radeon_device *rdev)
1419{ 1419{
1420 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK) 1420 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
1421 return -EINVAL; 1421 DRM_DEBUG("rv770_set_sw_state failed\n");
1422 return 0; 1422 return 0;
1423} 1423}
1424 1424