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authorDavid S. Miller <davem@davemloft.net>2018-08-05 20:08:27 -0400
committerDavid S. Miller <davem@davemloft.net>2018-08-05 20:08:27 -0400
commitc595be94c7b93ffdd2ed635b115dd2e6e8472f4c (patch)
treed77a39d7b0563edf6a7e24a4f3ca9242ca3070ae
parent074fb8801667add0b63083af90a3af6edca9532c (diff)
parentaabfc016e9a6db2a8c2da815fc84bfd5a2e8d221 (diff)
Merge branch 'bnxt_en-Updates-for-net-next'
Michael Chan says: ==================== bnxt_en: Updates for net-next. This series includes the usual firmware spec update. The driver has added external phy loopback test and phy setup retry logic that is needed during hotplug. In the SRIOV space, the driver has added a new VF resource allocation mode that requires the VF driver to reserve resources during IFUP. IF state changes are now propagated to firmware so that firmware can release some resources during IFDOWN. ethtool method to get firmware core dump and hwmon temperature reading have been added. DSCP to user priority support has been added to the driver's DCBNL interface, and the CoS queue logic has been refined to make sure that the special RDMA Congestion Notification hardware CoS queue will not be used for networking traffic. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/broadcom/Kconfig8
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt.c216
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt.h30
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.h66
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c89
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h10
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c8
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c378
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h37
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h1227
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c25
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c4
12 files changed, 1716 insertions, 382 deletions
diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig
index b7aa8ad96dfb..c1d3ee9baf7e 100644
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig
@@ -230,4 +230,12 @@ config BNXT_DCB
230 230
231 If unsure, say N. 231 If unsure, say N.
232 232
233config BNXT_HWMON
234 bool "Broadcom NetXtreme-C/E HWMON support"
235 default y
236 depends on BNXT && HWMON && !(BNXT=y && HWMON=m)
237 ---help---
238 Say Y if you want to expose the thermal sensor data on NetXtreme-C/E
239 devices, via the hwmon sysfs interface.
240
233endif # NET_VENDOR_BROADCOM 241endif # NET_VENDOR_BROADCOM
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
index c612d74451a7..d7f51ab85b45 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c
@@ -51,6 +51,8 @@
51#include <linux/cpu_rmap.h> 51#include <linux/cpu_rmap.h>
52#include <linux/cpumask.h> 52#include <linux/cpumask.h>
53#include <net/pkt_cls.h> 53#include <net/pkt_cls.h>
54#include <linux/hwmon.h>
55#include <linux/hwmon-sysfs.h>
54 56
55#include "bnxt_hsi.h" 57#include "bnxt_hsi.h"
56#include "bnxt.h" 58#include "bnxt.h"
@@ -1115,7 +1117,7 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1115 tpa_info->hash_type = PKT_HASH_TYPE_L4; 1117 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1116 tpa_info->gso_type = SKB_GSO_TCPV4; 1118 tpa_info->gso_type = SKB_GSO_TCPV4;
1117 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ 1119 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1118 if (hash_type == 3) 1120 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1119 tpa_info->gso_type = SKB_GSO_TCPV6; 1121 tpa_info->gso_type = SKB_GSO_TCPV6;
1120 tpa_info->rss_hash = 1122 tpa_info->rss_hash =
1121 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); 1123 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
@@ -3445,7 +3447,7 @@ static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3445 cp_ring_id = le16_to_cpu(req->cmpl_ring); 3447 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3446 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; 3448 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3447 3449
3448 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 3450 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
3449 void *short_cmd_req = bp->hwrm_short_cmd_req_addr; 3451 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3450 3452
3451 memcpy(short_cmd_req, req, msg_len); 3453 memcpy(short_cmd_req, req, msg_len);
@@ -3638,7 +3640,9 @@ int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3638 3640
3639static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) 3641static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3640{ 3642{
3643 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3641 struct hwrm_func_drv_rgtr_input req = {0}; 3644 struct hwrm_func_drv_rgtr_input req = {0};
3645 int rc;
3642 3646
3643 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); 3647 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3644 3648
@@ -3676,7 +3680,15 @@ static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3676 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); 3680 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3677 } 3681 }
3678 3682
3679 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 3683 mutex_lock(&bp->hwrm_cmd_lock);
3684 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3685 if (rc)
3686 rc = -EIO;
3687 else if (resp->flags &
3688 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3689 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3690 mutex_unlock(&bp->hwrm_cmd_lock);
3691 return rc;
3680} 3692}
3681 3693
3682static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) 3694static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
@@ -3981,6 +3993,7 @@ static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3981 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); 3993 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3982 if (set_rss) { 3994 if (set_rss) {
3983 req.hash_type = cpu_to_le32(bp->rss_hash_cfg); 3995 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3996 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
3984 if (vnic->flags & BNXT_VNIC_RSS_FLAG) { 3997 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3985 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 3998 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3986 max_rings = bp->rx_nr_rings - 1; 3999 max_rings = bp->rx_nr_rings - 1;
@@ -4578,7 +4591,7 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp)
4578 } 4591 }
4579 4592
4580 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings); 4593 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4581 if (bp->flags & BNXT_FLAG_NEW_RM) { 4594 if (BNXT_NEW_RM(bp)) {
4582 u16 cp, stats; 4595 u16 cp, stats;
4583 4596
4584 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings); 4597 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
@@ -4624,7 +4637,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4624 req->fid = cpu_to_le16(0xffff); 4637 req->fid = cpu_to_le16(0xffff);
4625 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0; 4638 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4626 req->num_tx_rings = cpu_to_le16(tx_rings); 4639 req->num_tx_rings = cpu_to_le16(tx_rings);
4627 if (bp->flags & BNXT_FLAG_NEW_RM) { 4640 if (BNXT_NEW_RM(bp)) {
4628 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0; 4641 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4629 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS | 4642 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4630 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0; 4643 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
@@ -4697,7 +4710,7 @@ bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4697 struct hwrm_func_vf_cfg_input req = {0}; 4710 struct hwrm_func_vf_cfg_input req = {0};
4698 int rc; 4711 int rc;
4699 4712
4700 if (!(bp->flags & BNXT_FLAG_NEW_RM)) { 4713 if (!BNXT_NEW_RM(bp)) {
4701 bp->hw_resc.resv_tx_rings = tx_rings; 4714 bp->hw_resc.resv_tx_rings = tx_rings;
4702 return 0; 4715 return 0;
4703 } 4716 }
@@ -4757,7 +4770,7 @@ static bool bnxt_need_reserve_rings(struct bnxt *bp)
4757 vnic = rx + 1; 4770 vnic = rx + 1;
4758 if (bp->flags & BNXT_FLAG_AGG_RINGS) 4771 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4759 rx <<= 1; 4772 rx <<= 1;
4760 if ((bp->flags & BNXT_FLAG_NEW_RM) && 4773 if (BNXT_NEW_RM(bp) &&
4761 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp || 4774 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4762 hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic)) 4775 hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4763 return true; 4776 return true;
@@ -4793,7 +4806,7 @@ static int __bnxt_reserve_rings(struct bnxt *bp)
4793 return rc; 4806 return rc;
4794 4807
4795 tx = hw_resc->resv_tx_rings; 4808 tx = hw_resc->resv_tx_rings;
4796 if (bp->flags & BNXT_FLAG_NEW_RM) { 4809 if (BNXT_NEW_RM(bp)) {
4797 rx = hw_resc->resv_rx_rings; 4810 rx = hw_resc->resv_rx_rings;
4798 cp = hw_resc->resv_cp_rings; 4811 cp = hw_resc->resv_cp_rings;
4799 grp = hw_resc->resv_hw_ring_grps; 4812 grp = hw_resc->resv_hw_ring_grps;
@@ -4837,7 +4850,7 @@ static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4837 u32 flags; 4850 u32 flags;
4838 int rc; 4851 int rc;
4839 4852
4840 if (!(bp->flags & BNXT_FLAG_NEW_RM)) 4853 if (!BNXT_NEW_RM(bp))
4841 return 0; 4854 return 0;
4842 4855
4843 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4856 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
@@ -4866,7 +4879,7 @@ static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4866 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps, 4879 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4867 cp_rings, vnics); 4880 cp_rings, vnics);
4868 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST; 4881 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4869 if (bp->flags & BNXT_FLAG_NEW_RM) 4882 if (BNXT_NEW_RM(bp))
4870 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST | 4883 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4871 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST | 4884 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4872 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST | 4885 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
@@ -5088,9 +5101,9 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5088 flags = le16_to_cpu(resp->flags); 5101 flags = le16_to_cpu(resp->flags);
5089 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED | 5102 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5090 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) { 5103 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5091 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT; 5104 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5092 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED) 5105 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5093 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT; 5106 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5094 } 5107 }
5095 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) 5108 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5096 bp->flags |= BNXT_FLAG_MULTI_HOST; 5109 bp->flags |= BNXT_FLAG_MULTI_HOST;
@@ -5162,7 +5175,7 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5162 5175
5163 pf->vf_resv_strategy = 5176 pf->vf_resv_strategy =
5164 le16_to_cpu(resp->vf_reservation_strategy); 5177 le16_to_cpu(resp->vf_reservation_strategy);
5165 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL) 5178 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
5166 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL; 5179 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5167 } 5180 }
5168hwrm_func_resc_qcaps_exit: 5181hwrm_func_resc_qcaps_exit:
@@ -5248,7 +5261,7 @@ static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5248 if (bp->hwrm_spec_code >= 0x10803) { 5261 if (bp->hwrm_spec_code >= 0x10803) {
5249 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 5262 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5250 if (!rc) 5263 if (!rc)
5251 bp->flags |= BNXT_FLAG_NEW_RM; 5264 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
5252 } 5265 }
5253 return 0; 5266 return 0;
5254} 5267}
@@ -5268,7 +5281,8 @@ static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5268 int rc = 0; 5281 int rc = 0;
5269 struct hwrm_queue_qportcfg_input req = {0}; 5282 struct hwrm_queue_qportcfg_input req = {0};
5270 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; 5283 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5271 u8 i, *qptr; 5284 u8 i, j, *qptr;
5285 bool no_rdma;
5272 5286
5273 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); 5287 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5274 5288
@@ -5286,19 +5300,24 @@ static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5286 if (bp->max_tc > BNXT_MAX_QUEUE) 5300 if (bp->max_tc > BNXT_MAX_QUEUE)
5287 bp->max_tc = BNXT_MAX_QUEUE; 5301 bp->max_tc = BNXT_MAX_QUEUE;
5288 5302
5303 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5304 qptr = &resp->queue_id0;
5305 for (i = 0, j = 0; i < bp->max_tc; i++) {
5306 bp->q_info[j].queue_id = *qptr++;
5307 bp->q_info[j].queue_profile = *qptr++;
5308 bp->tc_to_qidx[j] = j;
5309 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
5310 (no_rdma && BNXT_PF(bp)))
5311 j++;
5312 }
5313 bp->max_tc = max_t(u8, j, 1);
5314
5289 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG) 5315 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5290 bp->max_tc = 1; 5316 bp->max_tc = 1;
5291 5317
5292 if (bp->max_lltc > bp->max_tc) 5318 if (bp->max_lltc > bp->max_tc)
5293 bp->max_lltc = bp->max_tc; 5319 bp->max_lltc = bp->max_tc;
5294 5320
5295 qptr = &resp->queue_id0;
5296 for (i = 0; i < bp->max_tc; i++) {
5297 bp->q_info[i].queue_id = *qptr++;
5298 bp->q_info[i].queue_profile = *qptr++;
5299 bp->tc_to_qidx[i] = i;
5300 }
5301
5302qportcfg_exit: 5321qportcfg_exit:
5303 mutex_unlock(&bp->hwrm_cmd_lock); 5322 mutex_unlock(&bp->hwrm_cmd_lock);
5304 return rc; 5323 return rc;
@@ -5351,7 +5370,7 @@ static int bnxt_hwrm_ver_get(struct bnxt *bp)
5351 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg); 5370 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5352 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) && 5371 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5353 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) 5372 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5354 bp->flags |= BNXT_FLAG_SHORT_CMD; 5373 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
5355 5374
5356hwrm_ver_get_exit: 5375hwrm_ver_get_exit:
5357 mutex_unlock(&bp->hwrm_cmd_lock); 5376 mutex_unlock(&bp->hwrm_cmd_lock);
@@ -5920,7 +5939,7 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num)
5920 5939
5921 max_idx = min_t(int, bp->total_irqs, max_cp); 5940 max_idx = min_t(int, bp->total_irqs, max_cp);
5922 avail_msix = max_idx - bp->cp_nr_rings; 5941 avail_msix = max_idx - bp->cp_nr_rings;
5923 if (!(bp->flags & BNXT_FLAG_NEW_RM) || avail_msix >= num) 5942 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
5924 return avail_msix; 5943 return avail_msix;
5925 5944
5926 if (max_irq < total_req) { 5945 if (max_irq < total_req) {
@@ -5933,7 +5952,7 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num)
5933 5952
5934static int bnxt_get_num_msix(struct bnxt *bp) 5953static int bnxt_get_num_msix(struct bnxt *bp)
5935{ 5954{
5936 if (!(bp->flags & BNXT_FLAG_NEW_RM)) 5955 if (!BNXT_NEW_RM(bp))
5937 return bnxt_get_max_func_irqs(bp); 5956 return bnxt_get_max_func_irqs(bp);
5938 5957
5939 return bnxt_cp_rings_in_use(bp); 5958 return bnxt_cp_rings_in_use(bp);
@@ -6056,8 +6075,7 @@ int bnxt_reserve_rings(struct bnxt *bp)
6056 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc); 6075 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
6057 return rc; 6076 return rc;
6058 } 6077 }
6059 if ((bp->flags & BNXT_FLAG_NEW_RM) && 6078 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6060 (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6061 bnxt_ulp_irq_stop(bp); 6079 bnxt_ulp_irq_stop(bp);
6062 bnxt_clear_int_mode(bp); 6080 bnxt_clear_int_mode(bp);
6063 rc = bnxt_init_int_mode(bp); 6081 rc = bnxt_init_int_mode(bp);
@@ -6337,6 +6355,10 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6337 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) & 6355 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6338 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK; 6356 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6339 } 6357 }
6358 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
6359 if (bp->test_info)
6360 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
6361 }
6340 if (resp->supported_speeds_auto_mode) 6362 if (resp->supported_speeds_auto_mode)
6341 link_info->support_auto_speeds = 6363 link_info->support_auto_speeds =
6342 le16_to_cpu(resp->supported_speeds_auto_mode); 6364 le16_to_cpu(resp->supported_speeds_auto_mode);
@@ -6633,6 +6655,39 @@ static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6633 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6655 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6634} 6656}
6635 6657
6658static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6659{
6660 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6661 struct hwrm_func_drv_if_change_input req = {0};
6662 bool resc_reinit = false;
6663 int rc;
6664
6665 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
6666 return 0;
6667
6668 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
6669 if (up)
6670 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6671 mutex_lock(&bp->hwrm_cmd_lock);
6672 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6673 if (!rc && (resp->flags &
6674 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
6675 resc_reinit = true;
6676 mutex_unlock(&bp->hwrm_cmd_lock);
6677
6678 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
6679 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6680
6681 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6682 hw_resc->resv_cp_rings = 0;
6683 hw_resc->resv_tx_rings = 0;
6684 hw_resc->resv_rx_rings = 0;
6685 hw_resc->resv_hw_ring_grps = 0;
6686 hw_resc->resv_vnics = 0;
6687 }
6688 return rc;
6689}
6690
6636static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp) 6691static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6637{ 6692{
6638 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr; 6693 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
@@ -6742,6 +6797,62 @@ static void bnxt_get_wol_settings(struct bnxt *bp)
6742 } while (handle && handle != 0xffff); 6797 } while (handle && handle != 0xffff);
6743} 6798}
6744 6799
6800#ifdef CONFIG_BNXT_HWMON
6801static ssize_t bnxt_show_temp(struct device *dev,
6802 struct device_attribute *devattr, char *buf)
6803{
6804 struct hwrm_temp_monitor_query_input req = {0};
6805 struct hwrm_temp_monitor_query_output *resp;
6806 struct bnxt *bp = dev_get_drvdata(dev);
6807 u32 temp = 0;
6808
6809 resp = bp->hwrm_cmd_resp_addr;
6810 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
6811 mutex_lock(&bp->hwrm_cmd_lock);
6812 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
6813 temp = resp->temp * 1000; /* display millidegree */
6814 mutex_unlock(&bp->hwrm_cmd_lock);
6815
6816 return sprintf(buf, "%u\n", temp);
6817}
6818static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
6819
6820static struct attribute *bnxt_attrs[] = {
6821 &sensor_dev_attr_temp1_input.dev_attr.attr,
6822 NULL
6823};
6824ATTRIBUTE_GROUPS(bnxt);
6825
6826static void bnxt_hwmon_close(struct bnxt *bp)
6827{
6828 if (bp->hwmon_dev) {
6829 hwmon_device_unregister(bp->hwmon_dev);
6830 bp->hwmon_dev = NULL;
6831 }
6832}
6833
6834static void bnxt_hwmon_open(struct bnxt *bp)
6835{
6836 struct pci_dev *pdev = bp->pdev;
6837
6838 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
6839 DRV_MODULE_NAME, bp,
6840 bnxt_groups);
6841 if (IS_ERR(bp->hwmon_dev)) {
6842 bp->hwmon_dev = NULL;
6843 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
6844 }
6845}
6846#else
6847static void bnxt_hwmon_close(struct bnxt *bp)
6848{
6849}
6850
6851static void bnxt_hwmon_open(struct bnxt *bp)
6852{
6853}
6854#endif
6855
6745static bool bnxt_eee_config_ok(struct bnxt *bp) 6856static bool bnxt_eee_config_ok(struct bnxt *bp)
6746{ 6857{
6747 struct ethtool_eee *eee = &bp->eee; 6858 struct ethtool_eee *eee = &bp->eee;
@@ -6894,8 +7005,14 @@ static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6894 mutex_lock(&bp->link_lock); 7005 mutex_lock(&bp->link_lock);
6895 rc = bnxt_update_phy_setting(bp); 7006 rc = bnxt_update_phy_setting(bp);
6896 mutex_unlock(&bp->link_lock); 7007 mutex_unlock(&bp->link_lock);
6897 if (rc) 7008 if (rc) {
6898 netdev_warn(bp->dev, "failed to update phy settings\n"); 7009 netdev_warn(bp->dev, "failed to update phy settings\n");
7010 if (BNXT_SINGLE_PF(bp)) {
7011 bp->link_info.phy_retry = true;
7012 bp->link_info.phy_retry_expires =
7013 jiffies + 5 * HZ;
7014 }
7015 }
6899 } 7016 }
6900 7017
6901 if (irq_re_init) 7018 if (irq_re_init)
@@ -6981,8 +7098,16 @@ void bnxt_half_close_nic(struct bnxt *bp)
6981static int bnxt_open(struct net_device *dev) 7098static int bnxt_open(struct net_device *dev)
6982{ 7099{
6983 struct bnxt *bp = netdev_priv(dev); 7100 struct bnxt *bp = netdev_priv(dev);
7101 int rc;
7102
7103 bnxt_hwrm_if_change(bp, true);
7104 rc = __bnxt_open_nic(bp, true, true);
7105 if (rc)
7106 bnxt_hwrm_if_change(bp, false);
7107
7108 bnxt_hwmon_open(bp);
6984 7109
6985 return __bnxt_open_nic(bp, true, true); 7110 return rc;
6986} 7111}
6987 7112
6988static bool bnxt_drv_busy(struct bnxt *bp) 7113static bool bnxt_drv_busy(struct bnxt *bp)
@@ -7044,8 +7169,10 @@ static int bnxt_close(struct net_device *dev)
7044{ 7169{
7045 struct bnxt *bp = netdev_priv(dev); 7170 struct bnxt *bp = netdev_priv(dev);
7046 7171
7172 bnxt_hwmon_close(bp);
7047 bnxt_close_nic(bp, true, true); 7173 bnxt_close_nic(bp, true, true);
7048 bnxt_hwrm_shutdown_link(bp); 7174 bnxt_hwrm_shutdown_link(bp);
7175 bnxt_hwrm_if_change(bp, false);
7049 return 0; 7176 return 0;
7050} 7177}
7051 7178
@@ -7295,7 +7422,7 @@ skip_uc:
7295static bool bnxt_can_reserve_rings(struct bnxt *bp) 7422static bool bnxt_can_reserve_rings(struct bnxt *bp)
7296{ 7423{
7297#ifdef CONFIG_BNXT_SRIOV 7424#ifdef CONFIG_BNXT_SRIOV
7298 if ((bp->flags & BNXT_FLAG_NEW_RM) && BNXT_VF(bp)) { 7425 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
7299 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 7426 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7300 7427
7301 /* No minimum rings were provisioned by the PF. Don't 7428 /* No minimum rings were provisioned by the PF. Don't
@@ -7345,7 +7472,7 @@ static bool bnxt_rfs_capable(struct bnxt *bp)
7345 return false; 7472 return false;
7346 } 7473 }
7347 7474
7348 if (!(bp->flags & BNXT_FLAG_NEW_RM)) 7475 if (!BNXT_NEW_RM(bp))
7349 return true; 7476 return true;
7350 7477
7351 if (vnics == bp->hw_resc.resv_vnics) 7478 if (vnics == bp->hw_resc.resv_vnics)
@@ -7579,6 +7706,16 @@ static void bnxt_timer(struct timer_list *t)
7579 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event); 7706 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7580 bnxt_queue_sp_work(bp); 7707 bnxt_queue_sp_work(bp);
7581 } 7708 }
7709
7710 if (bp->link_info.phy_retry) {
7711 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
7712 bp->link_info.phy_retry = 0;
7713 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
7714 } else {
7715 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
7716 bnxt_queue_sp_work(bp);
7717 }
7718 }
7582bnxt_restart_timer: 7719bnxt_restart_timer:
7583 mod_timer(&bp->timer, jiffies + bp->current_interval); 7720 mod_timer(&bp->timer, jiffies + bp->current_interval);
7584} 7721}
@@ -7666,6 +7803,19 @@ static void bnxt_sp_task(struct work_struct *work)
7666 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", 7803 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7667 rc); 7804 rc);
7668 } 7805 }
7806 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
7807 int rc;
7808
7809 mutex_lock(&bp->link_lock);
7810 rc = bnxt_update_phy_setting(bp);
7811 mutex_unlock(&bp->link_lock);
7812 if (rc) {
7813 netdev_warn(bp->dev, "update phy settings retry failed\n");
7814 } else {
7815 bp->link_info.phy_retry = false;
7816 netdev_info(bp->dev, "update phy settings retry succeeded\n");
7817 }
7818 }
7669 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) { 7819 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7670 mutex_lock(&bp->link_lock); 7820 mutex_lock(&bp->link_lock);
7671 bnxt_get_port_module_status(bp); 7821 bnxt_get_port_module_status(bp);
@@ -7718,7 +7868,7 @@ int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7718 if (bp->flags & BNXT_FLAG_AGG_RINGS) 7868 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7719 rx_rings <<= 1; 7869 rx_rings <<= 1;
7720 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx; 7870 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7721 if (bp->flags & BNXT_FLAG_NEW_RM) 7871 if (BNXT_NEW_RM(bp))
7722 cp += bnxt_get_ulp_msix_num(bp); 7872 cp += bnxt_get_ulp_msix_num(bp);
7723 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp, 7873 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7724 vnics); 7874 vnics);
@@ -8727,7 +8877,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8727 if (rc) 8877 if (rc)
8728 goto init_err_pci_clean; 8878 goto init_err_pci_clean;
8729 8879
8730 if (bp->flags & BNXT_FLAG_SHORT_CMD) { 8880 if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
8731 rc = bnxt_alloc_hwrm_short_cmd_req(bp); 8881 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8732 if (rc) 8882 if (rc)
8733 goto init_err_pci_clean; 8883 goto init_err_pci_clean;
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
index 934aa11c82eb..fefa011320e0 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h
@@ -12,11 +12,11 @@
12#define BNXT_H 12#define BNXT_H
13 13
14#define DRV_MODULE_NAME "bnxt_en" 14#define DRV_MODULE_NAME "bnxt_en"
15#define DRV_MODULE_VERSION "1.9.1" 15#define DRV_MODULE_VERSION "1.9.2"
16 16
17#define DRV_VER_MAJ 1 17#define DRV_VER_MAJ 1
18#define DRV_VER_MIN 9 18#define DRV_VER_MIN 9
19#define DRV_VER_UPD 1 19#define DRV_VER_UPD 2
20 20
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/rhashtable.h> 22#include <linux/rhashtable.h>
@@ -326,6 +326,10 @@ struct rx_tpa_start_cmp_ext {
326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
328 328
329#define TPA_START_IS_IPV6(rx_tpa_start) \
330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
332
329struct rx_tpa_end_cmp { 333struct rx_tpa_end_cmp {
330 __le32 rx_tpa_end_cmp_len_flags_type; 334 __le32 rx_tpa_end_cmp_len_flags_type;
331 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 335 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
@@ -862,6 +866,7 @@ struct bnxt_pf_info {
862 u8 vf_resv_strategy; 866 u8 vf_resv_strategy;
863#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 867#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
864#define BNXT_VF_RESV_STRATEGY_MINIMAL 1 868#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
869#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
865 void *hwrm_cmd_req_addr[4]; 870 void *hwrm_cmd_req_addr[4];
866 dma_addr_t hwrm_cmd_req_dma_addr[4]; 871 dma_addr_t hwrm_cmd_req_dma_addr[4];
867 struct bnxt_vf_info *vf; 872 struct bnxt_vf_info *vf;
@@ -959,6 +964,9 @@ struct bnxt_link_info {
959 u16 advertising; /* user adv setting */ 964 u16 advertising; /* user adv setting */
960 bool force_link_chng; 965 bool force_link_chng;
961 966
967 bool phy_retry;
968 unsigned long phy_retry_expires;
969
962 /* a copy of phy_qcfg output used to report link 970 /* a copy of phy_qcfg output used to report link
963 * info to VF 971 * info to VF
964 */ 972 */
@@ -990,6 +998,8 @@ struct bnxt_led_info {
990 998
991struct bnxt_test_info { 999struct bnxt_test_info {
992 u8 offline_mask; 1000 u8 offline_mask;
1001 u8 flags;
1002#define BNXT_TEST_FL_EXT_LPBK 0x1
993 u16 timeout; 1003 u16 timeout;
994 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 1004 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
995}; 1005};
@@ -1134,7 +1144,6 @@ struct bnxt {
1134 atomic_t intr_sem; 1144 atomic_t intr_sem;
1135 1145
1136 u32 flags; 1146 u32 flags;
1137 #define BNXT_FLAG_DCB_ENABLED 0x1
1138 #define BNXT_FLAG_VF 0x2 1147 #define BNXT_FLAG_VF 0x2
1139 #define BNXT_FLAG_LRO 0x4 1148 #define BNXT_FLAG_LRO 0x4
1140#ifdef CONFIG_INET 1149#ifdef CONFIG_INET
@@ -1163,15 +1172,11 @@ struct bnxt {
1163 BNXT_FLAG_ROCEV2_CAP) 1172 BNXT_FLAG_ROCEV2_CAP)
1164 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1173 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1165 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1174 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1166 #define BNXT_FLAG_FW_LLDP_AGENT 0x80000
1167 #define BNXT_FLAG_MULTI_HOST 0x100000 1175 #define BNXT_FLAG_MULTI_HOST 0x100000
1168 #define BNXT_FLAG_SHORT_CMD 0x200000
1169 #define BNXT_FLAG_DOUBLE_DB 0x400000 1176 #define BNXT_FLAG_DOUBLE_DB 0x400000
1170 #define BNXT_FLAG_FW_DCBX_AGENT 0x800000
1171 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1177 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1172 #define BNXT_FLAG_DIM 0x2000000 1178 #define BNXT_FLAG_DIM 0x2000000
1173 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1179 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1174 #define BNXT_FLAG_NEW_RM 0x8000000
1175 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1180 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1176 1181
1177 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1182 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
@@ -1276,10 +1281,19 @@ struct bnxt {
1276 struct ieee_ets *ieee_ets; 1281 struct ieee_ets *ieee_ets;
1277 u8 dcbx_cap; 1282 u8 dcbx_cap;
1278 u8 default_pri; 1283 u8 default_pri;
1284 u8 max_dscp_value;
1279#endif /* CONFIG_BNXT_DCB */ 1285#endif /* CONFIG_BNXT_DCB */
1280 1286
1281 u32 msg_enable; 1287 u32 msg_enable;
1282 1288
1289 u32 fw_cap;
1290 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1291 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1292 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1293 #define BNXT_FW_CAP_NEW_RM 0x00000008
1294 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1295
1296#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1283 u32 hwrm_spec_code; 1297 u32 hwrm_spec_code;
1284 u16 hwrm_cmd_seq; 1298 u16 hwrm_cmd_seq;
1285 u32 hwrm_intr_seq_id; 1299 u32 hwrm_intr_seq_id;
@@ -1342,6 +1356,7 @@ struct bnxt {
1342#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1356#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1343#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1357#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1344#define BNXT_FLOW_STATS_SP_EVENT 15 1358#define BNXT_FLOW_STATS_SP_EVENT 15
1359#define BNXT_UPDATE_PHY_SP_EVENT 16
1345 1360
1346 struct bnxt_hw_resc hw_resc; 1361 struct bnxt_hw_resc hw_resc;
1347 struct bnxt_pf_info pf; 1362 struct bnxt_pf_info pf;
@@ -1397,6 +1412,7 @@ struct bnxt {
1397 struct bnxt_tc_info *tc_info; 1412 struct bnxt_tc_info *tc_info;
1398 struct dentry *debugfs_pdev; 1413 struct dentry *debugfs_pdev;
1399 struct dentry *debugfs_dim; 1414 struct dentry *debugfs_dim;
1415 struct device *hwmon_dev;
1400}; 1416};
1401 1417
1402#define BNXT_RX_STATS_OFFSET(counter) \ 1418#define BNXT_RX_STATS_OFFSET(counter) \
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.h
new file mode 100644
index 000000000000..09c22f8fe399
--- /dev/null
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_coredump.h
@@ -0,0 +1,66 @@
1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2018 Broadcom Inc
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10#ifndef BNXT_COREDUMP_H
11#define BNXT_COREDUMP_H
12
13struct bnxt_coredump_segment_hdr {
14 __u8 signature[4];
15 __le32 component_id;
16 __le32 segment_id;
17 __le32 flags;
18 __u8 low_version;
19 __u8 high_version;
20 __le16 function_id;
21 __le32 offset;
22 __le32 length;
23 __le32 status;
24 __le32 duration;
25 __le32 data_offset;
26 __le32 instance;
27 __le32 rsvd[5];
28};
29
30struct bnxt_coredump_record {
31 __u8 signature[4];
32 __le32 flags;
33 __u8 low_version;
34 __u8 high_version;
35 __u8 asic_state;
36 __u8 rsvd0[5];
37 char system_name[32];
38 __le16 year;
39 __le16 month;
40 __le16 day;
41 __le16 hour;
42 __le16 minute;
43 __le16 second;
44 __le16 utc_bias;
45 __le16 rsvd1;
46 char commandline[256];
47 __le32 total_segments;
48 __le32 os_ver_major;
49 __le32 os_ver_minor;
50 __le32 rsvd2;
51 char os_name[32];
52 __le16 end_year;
53 __le16 end_month;
54 __le16 end_day;
55 __le16 end_hour;
56 __le16 end_minute;
57 __le16 end_second;
58 __le16 end_utc_bias;
59 __le32 asic_id1;
60 __le32 asic_id2;
61 __le32 coredump_status;
62 __u8 ioctl_low_version;
63 __u8 ioctl_high_version;
64 __le16 rsvd3[313];
65};
66#endif
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c
index d5bc72cecde3..ddc98c359488 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c
@@ -385,6 +385,61 @@ set_app_exit:
385 return rc; 385 return rc;
386} 386}
387 387
388static int bnxt_hwrm_queue_dscp_qcaps(struct bnxt *bp)
389{
390 struct hwrm_queue_dscp_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
391 struct hwrm_queue_dscp_qcaps_input req = {0};
392 int rc;
393
394 if (bp->hwrm_spec_code < 0x10800 || BNXT_VF(bp))
395 return 0;
396
397 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_DSCP_QCAPS, -1, -1);
398 mutex_lock(&bp->hwrm_cmd_lock);
399 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
400 if (!rc) {
401 bp->max_dscp_value = (1 << resp->num_dscp_bits) - 1;
402 if (bp->max_dscp_value < 0x3f)
403 bp->max_dscp_value = 0;
404 }
405
406 mutex_unlock(&bp->hwrm_cmd_lock);
407 return rc;
408}
409
410static int bnxt_hwrm_queue_dscp2pri_cfg(struct bnxt *bp, struct dcb_app *app,
411 bool add)
412{
413 struct hwrm_queue_dscp2pri_cfg_input req = {0};
414 struct bnxt_dscp2pri_entry *dscp2pri;
415 dma_addr_t mapping;
416 int rc;
417
418 if (bp->hwrm_spec_code < 0x10800)
419 return 0;
420
421 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_DSCP2PRI_CFG, -1, -1);
422 dscp2pri = dma_alloc_coherent(&bp->pdev->dev, sizeof(*dscp2pri),
423 &mapping, GFP_KERNEL);
424 if (!dscp2pri)
425 return -ENOMEM;
426
427 req.src_data_addr = cpu_to_le64(mapping);
428 dscp2pri->dscp = app->protocol;
429 if (add)
430 dscp2pri->mask = 0x3f;
431 else
432 dscp2pri->mask = 0;
433 dscp2pri->pri = app->priority;
434 req.entry_cnt = cpu_to_le16(1);
435 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
436 if (rc)
437 rc = -EIO;
438 dma_free_coherent(&bp->pdev->dev, sizeof(*dscp2pri), dscp2pri,
439 mapping);
440 return rc;
441}
442
388static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc) 443static int bnxt_ets_validate(struct bnxt *bp, struct ieee_ets *ets, u8 *tc)
389{ 444{
390 int total_ets_bw = 0; 445 int total_ets_bw = 0;
@@ -551,15 +606,30 @@ static int bnxt_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)
551 return rc; 606 return rc;
552} 607}
553 608
609static int bnxt_dcbnl_ieee_dscp_app_prep(struct bnxt *bp, struct dcb_app *app)
610{
611 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP) {
612 if (!bp->max_dscp_value)
613 return -ENOTSUPP;
614 if (app->protocol > bp->max_dscp_value)
615 return -EINVAL;
616 }
617 return 0;
618}
619
554static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app) 620static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
555{ 621{
556 struct bnxt *bp = netdev_priv(dev); 622 struct bnxt *bp = netdev_priv(dev);
557 int rc = -EINVAL; 623 int rc;
558 624
559 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) || 625 if (!(bp->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
560 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 626 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
561 return -EINVAL; 627 return -EINVAL;
562 628
629 rc = bnxt_dcbnl_ieee_dscp_app_prep(bp, app);
630 if (rc)
631 return rc;
632
563 rc = dcb_ieee_setapp(dev, app); 633 rc = dcb_ieee_setapp(dev, app);
564 if (rc) 634 if (rc)
565 return rc; 635 return rc;
@@ -570,6 +640,9 @@ static int bnxt_dcbnl_ieee_setapp(struct net_device *dev, struct dcb_app *app)
570 app->protocol == ROCE_V2_UDP_DPORT)) 640 app->protocol == ROCE_V2_UDP_DPORT))
571 rc = bnxt_hwrm_set_dcbx_app(bp, app, true); 641 rc = bnxt_hwrm_set_dcbx_app(bp, app, true);
572 642
643 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP)
644 rc = bnxt_hwrm_queue_dscp2pri_cfg(bp, app, true);
645
573 return rc; 646 return rc;
574} 647}
575 648
@@ -582,6 +655,10 @@ static int bnxt_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
582 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST)) 655 !(bp->dcbx_cap & DCB_CAP_DCBX_HOST))
583 return -EINVAL; 656 return -EINVAL;
584 657
658 rc = bnxt_dcbnl_ieee_dscp_app_prep(bp, app);
659 if (rc)
660 return rc;
661
585 rc = dcb_ieee_delapp(dev, app); 662 rc = dcb_ieee_delapp(dev, app);
586 if (rc) 663 if (rc)
587 return rc; 664 return rc;
@@ -591,6 +668,9 @@ static int bnxt_dcbnl_ieee_delapp(struct net_device *dev, struct dcb_app *app)
591 app->protocol == ROCE_V2_UDP_DPORT)) 668 app->protocol == ROCE_V2_UDP_DPORT))
592 rc = bnxt_hwrm_set_dcbx_app(bp, app, false); 669 rc = bnxt_hwrm_set_dcbx_app(bp, app, false);
593 670
671 if (app->selector == IEEE_8021QAZ_APP_SEL_DSCP)
672 rc = bnxt_hwrm_queue_dscp2pri_cfg(bp, app, false);
673
594 return rc; 674 return rc;
595} 675}
596 676
@@ -610,7 +690,7 @@ static u8 bnxt_dcbnl_setdcbx(struct net_device *dev, u8 mode)
610 return 1; 690 return 1;
611 691
612 if (mode & DCB_CAP_DCBX_HOST) { 692 if (mode & DCB_CAP_DCBX_HOST) {
613 if (BNXT_VF(bp) || (bp->flags & BNXT_FLAG_FW_LLDP_AGENT)) 693 if (BNXT_VF(bp) || (bp->fw_cap & BNXT_FW_CAP_LLDP_AGENT))
614 return 1; 694 return 1;
615 695
616 /* only support IEEE */ 696 /* only support IEEE */
@@ -642,10 +722,11 @@ void bnxt_dcb_init(struct bnxt *bp)
642 if (bp->hwrm_spec_code < 0x10501) 722 if (bp->hwrm_spec_code < 0x10501)
643 return; 723 return;
644 724
725 bnxt_hwrm_queue_dscp_qcaps(bp);
645 bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE; 726 bp->dcbx_cap = DCB_CAP_DCBX_VER_IEEE;
646 if (BNXT_PF(bp) && !(bp->flags & BNXT_FLAG_FW_LLDP_AGENT)) 727 if (BNXT_PF(bp) && !(bp->fw_cap & BNXT_FW_CAP_LLDP_AGENT))
647 bp->dcbx_cap |= DCB_CAP_DCBX_HOST; 728 bp->dcbx_cap |= DCB_CAP_DCBX_HOST;
648 else if (bp->flags & BNXT_FLAG_FW_DCBX_AGENT) 729 else if (bp->fw_cap & BNXT_FW_CAP_DCBX_AGENT)
649 bp->dcbx_cap |= DCB_CAP_DCBX_LLD_MANAGED; 730 bp->dcbx_cap |= DCB_CAP_DCBX_LLD_MANAGED;
650 bp->dev->dcbnl_ops = &dcbnl_ops; 731 bp->dev->dcbnl_ops = &dcbnl_ops;
651} 732}
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h
index 69efde785f23..6eed231de565 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h
@@ -33,10 +33,20 @@ struct bnxt_cos2bw_cfg {
33 u8 unused; 33 u8 unused;
34}; 34};
35 35
36struct bnxt_dscp2pri_entry {
37 u8 dscp;
38 u8 mask;
39 u8 pri;
40};
41
36#define BNXT_LLQ(q_profile) \ 42#define BNXT_LLQ(q_profile) \
37 ((q_profile) == \ 43 ((q_profile) == \
38 QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE) 44 QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE)
39 45
46#define BNXT_CNPQ(q_profile) \
47 ((q_profile) == \
48 QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP)
49
40#define HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL 0x0300 50#define HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL 0x0300
41 51
42void bnxt_dcb_init(struct bnxt *bp); 52void bnxt_dcb_init(struct bnxt *bp);
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c
index 7bd96ab4f7c5..f3b9fbcc705b 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c
@@ -29,7 +29,7 @@ static const struct bnxt_dl_nvm_param nvm_params[] = {
29static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg, 29static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg,
30 int msg_len, union devlink_param_value *val) 30 int msg_len, union devlink_param_value *val)
31{ 31{
32 struct hwrm_nvm_variable_input *req = msg; 32 struct hwrm_nvm_get_variable_input *req = msg;
33 void *data_addr = NULL, *buf = NULL; 33 void *data_addr = NULL, *buf = NULL;
34 struct bnxt_dl_nvm_param nvm_param; 34 struct bnxt_dl_nvm_param nvm_param;
35 int bytesize, idx = 0, rc, i; 35 int bytesize, idx = 0, rc, i;
@@ -60,18 +60,18 @@ static int bnxt_hwrm_nvm_req(struct bnxt *bp, u32 param_id, void *msg,
60 if (!data_addr) 60 if (!data_addr)
61 return -ENOMEM; 61 return -ENOMEM;
62 62
63 req->data_addr = cpu_to_le64(data_dma_addr); 63 req->dest_data_addr = cpu_to_le64(data_dma_addr);
64 req->data_len = cpu_to_le16(nvm_param.num_bits); 64 req->data_len = cpu_to_le16(nvm_param.num_bits);
65 req->option_num = cpu_to_le16(nvm_param.offset); 65 req->option_num = cpu_to_le16(nvm_param.offset);
66 req->index_0 = cpu_to_le16(idx); 66 req->index_0 = cpu_to_le16(idx);
67 if (idx) 67 if (idx)
68 req->dimensions = cpu_to_le16(1); 68 req->dimensions = cpu_to_le16(1);
69 69
70 if (req->req_type == HWRM_NVM_SET_VARIABLE) 70 if (req->req_type == cpu_to_le16(HWRM_NVM_SET_VARIABLE))
71 memcpy(data_addr, buf, bytesize); 71 memcpy(data_addr, buf, bytesize);
72 72
73 rc = hwrm_send_message(bp, msg, msg_len, HWRM_CMD_TIMEOUT); 73 rc = hwrm_send_message(bp, msg, msg_len, HWRM_CMD_TIMEOUT);
74 if (!rc && req->req_type == HWRM_NVM_GET_VARIABLE) 74 if (!rc && req->req_type == cpu_to_le16(HWRM_NVM_GET_VARIABLE))
75 memcpy(buf, data_addr, bytesize); 75 memcpy(buf, data_addr, bytesize);
76 76
77 dma_free_coherent(&bp->pdev->dev, bytesize, data_addr, data_dma_addr); 77 dma_free_coherent(&bp->pdev->dev, bytesize, data_addr, data_dma_addr);
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
index 7270c8b0cef3..b6dbc3f6d309 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c
@@ -16,12 +16,15 @@
16#include <linux/etherdevice.h> 16#include <linux/etherdevice.h>
17#include <linux/crc32.h> 17#include <linux/crc32.h>
18#include <linux/firmware.h> 18#include <linux/firmware.h>
19#include <linux/utsname.h>
20#include <linux/time.h>
19#include "bnxt_hsi.h" 21#include "bnxt_hsi.h"
20#include "bnxt.h" 22#include "bnxt.h"
21#include "bnxt_xdp.h" 23#include "bnxt_xdp.h"
22#include "bnxt_ethtool.h" 24#include "bnxt_ethtool.h"
23#include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 25#include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
24#include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 26#include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
27#include "bnxt_coredump.h"
25#define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100) 28#define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
26#define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 29#define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
27#define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200) 30#define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
@@ -112,6 +115,11 @@ static int bnxt_set_coalesce(struct net_device *dev,
112 BNXT_MAX_STATS_COAL_TICKS); 115 BNXT_MAX_STATS_COAL_TICKS);
113 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
114 bp->stats_coal_ticks = stats_ticks; 117 bp->stats_coal_ticks = stats_ticks;
118 if (bp->stats_coal_ticks)
119 bp->current_interval =
120 bp->stats_coal_ticks * HZ / 1000000;
121 else
122 bp->current_interval = BNXT_TIMER_INTERVAL;
115 update_stats = true; 123 update_stats = true;
116 } 124 }
117 125
@@ -162,7 +170,7 @@ static const struct {
162 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 170 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
163 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 171 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
164 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 172 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
165 BNXT_RX_STATS_ENTRY(rx_1024b_1518_frames), 173 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
166 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 174 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
167 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 175 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
168 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 176 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
@@ -205,9 +213,9 @@ static const struct {
205 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 213 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
206 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 214 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
207 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 215 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
208 BNXT_TX_STATS_ENTRY(tx_1024b_1518_frames), 216 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
209 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 217 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
210 BNXT_TX_STATS_ENTRY(tx_1519b_2047_frames), 218 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
211 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 219 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
212 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 220 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
213 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 221 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
@@ -463,7 +471,7 @@ static void bnxt_get_channels(struct net_device *dev,
463 int max_tx_sch_inputs; 471 int max_tx_sch_inputs;
464 472
465 /* Get the most up-to-date max_tx_sch_inputs. */ 473 /* Get the most up-to-date max_tx_sch_inputs. */
466 if (bp->flags & BNXT_FLAG_NEW_RM) 474 if (BNXT_NEW_RM(bp))
467 bnxt_hwrm_func_resc_qcaps(bp, false); 475 bnxt_hwrm_func_resc_qcaps(bp, false);
468 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 476 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
469 477
@@ -2392,7 +2400,7 @@ static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
2392 return rc; 2400 return rc;
2393} 2401}
2394 2402
2395static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable) 2403static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
2396{ 2404{
2397 struct hwrm_port_phy_cfg_input req = {0}; 2405 struct hwrm_port_phy_cfg_input req = {0};
2398 2406
@@ -2400,7 +2408,10 @@ static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable)
2400 2408
2401 if (enable) { 2409 if (enable) {
2402 bnxt_disable_an_for_lpbk(bp, &req); 2410 bnxt_disable_an_for_lpbk(bp, &req);
2403 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 2411 if (ext)
2412 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
2413 else
2414 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
2404 } else { 2415 } else {
2405 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 2416 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
2406 } 2417 }
@@ -2533,15 +2544,17 @@ static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
2533 return rc; 2544 return rc;
2534} 2545}
2535 2546
2536#define BNXT_DRV_TESTS 3 2547#define BNXT_DRV_TESTS 4
2537#define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 2548#define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
2538#define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 2549#define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
2539#define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 2550#define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
2551#define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
2540 2552
2541static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 2553static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
2542 u64 *buf) 2554 u64 *buf)
2543{ 2555{
2544 struct bnxt *bp = netdev_priv(dev); 2556 struct bnxt *bp = netdev_priv(dev);
2557 bool do_ext_lpbk = false;
2545 bool offline = false; 2558 bool offline = false;
2546 u8 test_results = 0; 2559 u8 test_results = 0;
2547 u8 test_mask = 0; 2560 u8 test_mask = 0;
@@ -2555,6 +2568,10 @@ static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
2555 return; 2568 return;
2556 } 2569 }
2557 2570
2571 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
2572 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK))
2573 do_ext_lpbk = true;
2574
2558 if (etest->flags & ETH_TEST_FL_OFFLINE) { 2575 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2559 if (bp->pf.active_vfs) { 2576 if (bp->pf.active_vfs) {
2560 etest->flags |= ETH_TEST_FL_FAILED; 2577 etest->flags |= ETH_TEST_FL_FAILED;
@@ -2595,13 +2612,22 @@ static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
2595 buf[BNXT_MACLPBK_TEST_IDX] = 0; 2612 buf[BNXT_MACLPBK_TEST_IDX] = 0;
2596 2613
2597 bnxt_hwrm_mac_loopback(bp, false); 2614 bnxt_hwrm_mac_loopback(bp, false);
2598 bnxt_hwrm_phy_loopback(bp, true); 2615 bnxt_hwrm_phy_loopback(bp, true, false);
2599 msleep(1000); 2616 msleep(1000);
2600 if (bnxt_run_loopback(bp)) { 2617 if (bnxt_run_loopback(bp)) {
2601 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 2618 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
2602 etest->flags |= ETH_TEST_FL_FAILED; 2619 etest->flags |= ETH_TEST_FL_FAILED;
2603 } 2620 }
2604 bnxt_hwrm_phy_loopback(bp, false); 2621 if (do_ext_lpbk) {
2622 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2623 bnxt_hwrm_phy_loopback(bp, true, true);
2624 msleep(1000);
2625 if (bnxt_run_loopback(bp)) {
2626 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
2627 etest->flags |= ETH_TEST_FL_FAILED;
2628 }
2629 }
2630 bnxt_hwrm_phy_loopback(bp, false, false);
2605 bnxt_half_close_nic(bp); 2631 bnxt_half_close_nic(bp);
2606 bnxt_open_nic(bp, false, true); 2632 bnxt_open_nic(bp, false, true);
2607 } 2633 }
@@ -2662,6 +2688,334 @@ static int bnxt_reset(struct net_device *dev, u32 *flags)
2662 return rc; 2688 return rc;
2663} 2689}
2664 2690
2691static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
2692 struct bnxt_hwrm_dbg_dma_info *info)
2693{
2694 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
2695 struct hwrm_dbg_cmn_input *cmn_req = msg;
2696 __le16 *seq_ptr = msg + info->seq_off;
2697 u16 seq = 0, len, segs_off;
2698 void *resp = cmn_resp;
2699 dma_addr_t dma_handle;
2700 int rc, off = 0;
2701 void *dma_buf;
2702
2703 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
2704 GFP_KERNEL);
2705 if (!dma_buf)
2706 return -ENOMEM;
2707
2708 segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
2709 total_segments);
2710 cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
2711 cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
2712 mutex_lock(&bp->hwrm_cmd_lock);
2713 while (1) {
2714 *seq_ptr = cpu_to_le16(seq);
2715 rc = _hwrm_send_message(bp, msg, msg_len, HWRM_CMD_TIMEOUT);
2716 if (rc)
2717 break;
2718
2719 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
2720 if (!seq &&
2721 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
2722 info->segs = le16_to_cpu(*((__le16 *)(resp +
2723 segs_off)));
2724 if (!info->segs) {
2725 rc = -EIO;
2726 break;
2727 }
2728
2729 info->dest_buf_size = info->segs *
2730 sizeof(struct coredump_segment_record);
2731 info->dest_buf = kmalloc(info->dest_buf_size,
2732 GFP_KERNEL);
2733 if (!info->dest_buf) {
2734 rc = -ENOMEM;
2735 break;
2736 }
2737 }
2738
2739 if (info->dest_buf)
2740 memcpy(info->dest_buf + off, dma_buf, len);
2741
2742 if (cmn_req->req_type ==
2743 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
2744 info->dest_buf_size += len;
2745
2746 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
2747 break;
2748
2749 seq++;
2750 off += len;
2751 }
2752 mutex_unlock(&bp->hwrm_cmd_lock);
2753 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
2754 return rc;
2755}
2756
2757static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
2758 struct bnxt_coredump *coredump)
2759{
2760 struct hwrm_dbg_coredump_list_input req = {0};
2761 struct bnxt_hwrm_dbg_dma_info info = {NULL};
2762 int rc;
2763
2764 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
2765
2766 info.dma_len = COREDUMP_LIST_BUF_LEN;
2767 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
2768 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
2769 data_len);
2770
2771 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
2772 if (!rc) {
2773 coredump->data = info.dest_buf;
2774 coredump->data_size = info.dest_buf_size;
2775 coredump->total_segs = info.segs;
2776 }
2777 return rc;
2778}
2779
2780static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
2781 u16 segment_id)
2782{
2783 struct hwrm_dbg_coredump_initiate_input req = {0};
2784
2785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
2786 req.component_id = cpu_to_le16(component_id);
2787 req.segment_id = cpu_to_le16(segment_id);
2788
2789 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2790}
2791
2792static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
2793 u16 segment_id, u32 *seg_len,
2794 void *buf, u32 offset)
2795{
2796 struct hwrm_dbg_coredump_retrieve_input req = {0};
2797 struct bnxt_hwrm_dbg_dma_info info = {NULL};
2798 int rc;
2799
2800 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
2801 req.component_id = cpu_to_le16(component_id);
2802 req.segment_id = cpu_to_le16(segment_id);
2803
2804 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
2805 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
2806 seq_no);
2807 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
2808 data_len);
2809 if (buf)
2810 info.dest_buf = buf + offset;
2811
2812 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
2813 if (!rc)
2814 *seg_len = info.dest_buf_size;
2815
2816 return rc;
2817}
2818
2819static void
2820bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
2821 struct bnxt_coredump_segment_hdr *seg_hdr,
2822 struct coredump_segment_record *seg_rec, u32 seg_len,
2823 int status, u32 duration, u32 instance)
2824{
2825 memset(seg_hdr, 0, sizeof(*seg_hdr));
2826 strcpy(seg_hdr->signature, "sEgM");
2827 if (seg_rec) {
2828 seg_hdr->component_id = (__force __le32)seg_rec->component_id;
2829 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
2830 seg_hdr->low_version = seg_rec->version_low;
2831 seg_hdr->high_version = seg_rec->version_hi;
2832 } else {
2833 /* For hwrm_ver_get response Component id = 2
2834 * and Segment id = 0
2835 */
2836 seg_hdr->component_id = cpu_to_le32(2);
2837 seg_hdr->segment_id = 0;
2838 }
2839 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
2840 seg_hdr->length = cpu_to_le32(seg_len);
2841 seg_hdr->status = cpu_to_le32(status);
2842 seg_hdr->duration = cpu_to_le32(duration);
2843 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
2844 seg_hdr->instance = cpu_to_le32(instance);
2845}
2846
2847static void
2848bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
2849 time64_t start, s16 start_utc, u16 total_segs,
2850 int status)
2851{
2852 time64_t end = ktime_get_real_seconds();
2853 u32 os_ver_major = 0, os_ver_minor = 0;
2854 struct tm tm;
2855
2856 time64_to_tm(start, 0, &tm);
2857 memset(record, 0, sizeof(*record));
2858 strcpy(record->signature, "cOrE");
2859 record->flags = 0;
2860 record->low_version = 0;
2861 record->high_version = 1;
2862 record->asic_state = 0;
2863 strncpy(record->system_name, utsname()->nodename,
2864 strlen(utsname()->nodename));
2865 record->year = cpu_to_le16(tm.tm_year);
2866 record->month = cpu_to_le16(tm.tm_mon);
2867 record->day = cpu_to_le16(tm.tm_mday);
2868 record->hour = cpu_to_le16(tm.tm_hour);
2869 record->minute = cpu_to_le16(tm.tm_min);
2870 record->second = cpu_to_le16(tm.tm_sec);
2871 record->utc_bias = cpu_to_le16(start_utc);
2872 strcpy(record->commandline, "ethtool -w");
2873 record->total_segments = cpu_to_le32(total_segs);
2874
2875 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
2876 record->os_ver_major = cpu_to_le32(os_ver_major);
2877 record->os_ver_minor = cpu_to_le32(os_ver_minor);
2878
2879 strcpy(record->os_name, utsname()->sysname);
2880 time64_to_tm(end, 0, &tm);
2881 record->end_year = cpu_to_le16(tm.tm_year + 1900);
2882 record->end_month = cpu_to_le16(tm.tm_mon + 1);
2883 record->end_day = cpu_to_le16(tm.tm_mday);
2884 record->end_hour = cpu_to_le16(tm.tm_hour);
2885 record->end_minute = cpu_to_le16(tm.tm_min);
2886 record->end_second = cpu_to_le16(tm.tm_sec);
2887 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
2888 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
2889 bp->ver_resp.chip_rev << 8 |
2890 bp->ver_resp.chip_metal);
2891 record->asic_id2 = 0;
2892 record->coredump_status = cpu_to_le32(status);
2893 record->ioctl_low_version = 0;
2894 record->ioctl_high_version = 0;
2895}
2896
2897static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
2898{
2899 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
2900 struct coredump_segment_record *seg_record = NULL;
2901 u32 offset = 0, seg_hdr_len, seg_record_len;
2902 struct bnxt_coredump_segment_hdr seg_hdr;
2903 struct bnxt_coredump_record coredump_rec;
2904 struct bnxt_coredump coredump = {NULL};
2905 time64_t start_time;
2906 u16 start_utc;
2907 int rc = 0, i;
2908
2909 start_time = ktime_get_real_seconds();
2910 start_utc = sys_tz.tz_minuteswest * 60;
2911 seg_hdr_len = sizeof(seg_hdr);
2912
2913 /* First segment should be hwrm_ver_get response */
2914 *dump_len = seg_hdr_len + ver_get_resp_len;
2915 if (buf) {
2916 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
2917 0, 0, 0);
2918 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
2919 offset += seg_hdr_len;
2920 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
2921 offset += ver_get_resp_len;
2922 }
2923
2924 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
2925 if (rc) {
2926 netdev_err(bp->dev, "Failed to get coredump segment list\n");
2927 goto err;
2928 }
2929
2930 *dump_len += seg_hdr_len * coredump.total_segs;
2931
2932 seg_record = (struct coredump_segment_record *)coredump.data;
2933 seg_record_len = sizeof(*seg_record);
2934
2935 for (i = 0; i < coredump.total_segs; i++) {
2936 u16 comp_id = le16_to_cpu(seg_record->component_id);
2937 u16 seg_id = le16_to_cpu(seg_record->segment_id);
2938 u32 duration = 0, seg_len = 0;
2939 unsigned long start, end;
2940
2941 start = jiffies;
2942
2943 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
2944 if (rc) {
2945 netdev_err(bp->dev,
2946 "Failed to initiate coredump for seg = %d\n",
2947 seg_record->segment_id);
2948 goto next_seg;
2949 }
2950
2951 /* Write segment data into the buffer */
2952 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
2953 &seg_len, buf,
2954 offset + seg_hdr_len);
2955 if (rc)
2956 netdev_err(bp->dev,
2957 "Failed to retrieve coredump for seg = %d\n",
2958 seg_record->segment_id);
2959
2960next_seg:
2961 end = jiffies;
2962 duration = jiffies_to_msecs(end - start);
2963 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
2964 rc, duration, 0);
2965
2966 if (buf) {
2967 /* Write segment header into the buffer */
2968 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
2969 offset += seg_hdr_len + seg_len;
2970 }
2971
2972 *dump_len += seg_len;
2973 seg_record =
2974 (struct coredump_segment_record *)((u8 *)seg_record +
2975 seg_record_len);
2976 }
2977
2978err:
2979 if (buf) {
2980 bnxt_fill_coredump_record(bp, &coredump_rec, start_time,
2981 start_utc, coredump.total_segs + 1,
2982 rc);
2983 memcpy(buf + offset, &coredump_rec, sizeof(coredump_rec));
2984 }
2985 kfree(coredump.data);
2986 *dump_len += sizeof(coredump_rec);
2987
2988 return rc;
2989}
2990
2991static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
2992{
2993 struct bnxt *bp = netdev_priv(dev);
2994
2995 if (bp->hwrm_spec_code < 0x10801)
2996 return -EOPNOTSUPP;
2997
2998 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
2999 bp->ver_resp.hwrm_fw_min_8b << 16 |
3000 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3001 bp->ver_resp.hwrm_fw_rsvd_8b;
3002
3003 return bnxt_get_coredump(bp, NULL, &dump->len);
3004}
3005
3006static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3007 void *buf)
3008{
3009 struct bnxt *bp = netdev_priv(dev);
3010
3011 if (bp->hwrm_spec_code < 0x10801)
3012 return -EOPNOTSUPP;
3013
3014 memset(buf, 0, dump->len);
3015
3016 return bnxt_get_coredump(bp, buf, &dump->len);
3017}
3018
2665void bnxt_ethtool_init(struct bnxt *bp) 3019void bnxt_ethtool_init(struct bnxt *bp)
2666{ 3020{
2667 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr; 3021 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
@@ -2702,6 +3056,8 @@ void bnxt_ethtool_init(struct bnxt *bp)
2702 strcpy(str, "Mac loopback test (offline)"); 3056 strcpy(str, "Mac loopback test (offline)");
2703 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 3057 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
2704 strcpy(str, "Phy loopback test (offline)"); 3058 strcpy(str, "Phy loopback test (offline)");
3059 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3060 strcpy(str, "Ext loopback test (offline)");
2705 } else if (i == BNXT_IRQ_TEST_IDX) { 3061 } else if (i == BNXT_IRQ_TEST_IDX) {
2706 strcpy(str, "Interrupt_test (offline)"); 3062 strcpy(str, "Interrupt_test (offline)");
2707 } else { 3063 } else {
@@ -2763,4 +3119,6 @@ const struct ethtool_ops bnxt_ethtool_ops = {
2763 .set_phys_id = bnxt_set_phys_id, 3119 .set_phys_id = bnxt_set_phys_id,
2764 .self_test = bnxt_self_test, 3120 .self_test = bnxt_self_test,
2765 .reset = bnxt_reset, 3121 .reset = bnxt_reset,
3122 .get_dump_flag = bnxt_get_dump_flag,
3123 .get_dump_data = bnxt_get_dump_data,
2766}; 3124};
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h
index 836ef682f24c..b5b65b3f8534 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.h
@@ -22,6 +22,43 @@ struct bnxt_led_cfg {
22 u8 rsvd; 22 u8 rsvd;
23}; 23};
24 24
25#define COREDUMP_LIST_BUF_LEN 2048
26#define COREDUMP_RETRIEVE_BUF_LEN 4096
27
28struct bnxt_coredump {
29 void *data;
30 int data_size;
31 u16 total_segs;
32};
33
34struct bnxt_hwrm_dbg_dma_info {
35 void *dest_buf;
36 int dest_buf_size;
37 u16 dma_len;
38 u16 seq_off;
39 u16 data_len_off;
40 u16 segs;
41};
42
43struct hwrm_dbg_cmn_input {
44 __le16 req_type;
45 __le16 cmpl_ring;
46 __le16 seq_id;
47 __le16 target_id;
48 __le64 resp_addr;
49 __le64 host_dest_addr;
50 __le32 host_buf_len;
51};
52
53struct hwrm_dbg_cmn_output {
54 __le16 error_code;
55 __le16 req_type;
56 __le16 seq_id;
57 __le16 resp_len;
58 u8 flags;
59 #define HWRM_DBG_CMN_FLAGS_MORE 1
60};
61
25#define BNXT_LED_DFLT_ENA \ 62#define BNXT_LED_DFLT_ENA \
26 (PORT_LED_CFG_REQ_ENABLES_LED0_ID | \ 63 (PORT_LED_CFG_REQ_ENABLES_LED0_ID | \
27 PORT_LED_CFG_REQ_ENABLES_LED0_STATE | \ 64 PORT_LED_CFG_REQ_ENABLES_LED0_STATE | \
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
index c75d7fa6dab6..971ace5d0d4a 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
@@ -96,6 +96,7 @@ struct hwrm_short_input {
96struct cmd_nums { 96struct cmd_nums {
97 __le16 req_type; 97 __le16 req_type;
98 #define HWRM_VER_GET 0x0UL 98 #define HWRM_VER_GET 0x0UL
99 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
99 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 100 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
100 #define HWRM_FUNC_VF_CFG 0xfUL 101 #define HWRM_FUNC_VF_CFG 0xfUL
101 #define HWRM_RESERVED1 0x10UL 102 #define HWRM_RESERVED1 0x10UL
@@ -159,6 +160,7 @@ struct cmd_nums {
159 #define HWRM_RING_FREE 0x51UL 160 #define HWRM_RING_FREE 0x51UL
160 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 161 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
161 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 162 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
163 #define HWRM_RING_AGGINT_QCAPS 0x54UL
162 #define HWRM_RING_RESET 0x5eUL 164 #define HWRM_RING_RESET 0x5eUL
163 #define HWRM_RING_GRP_ALLOC 0x60UL 165 #define HWRM_RING_GRP_ALLOC 0x60UL
164 #define HWRM_RING_GRP_FREE 0x61UL 166 #define HWRM_RING_GRP_FREE 0x61UL
@@ -191,6 +193,8 @@ struct cmd_nums {
191 #define HWRM_PORT_QSTATS_EXT 0xb4UL 193 #define HWRM_PORT_QSTATS_EXT 0xb4UL
192 #define HWRM_FW_RESET 0xc0UL 194 #define HWRM_FW_RESET 0xc0UL
193 #define HWRM_FW_QSTATUS 0xc1UL 195 #define HWRM_FW_QSTATUS 0xc1UL
196 #define HWRM_FW_HEALTH_CHECK 0xc2UL
197 #define HWRM_FW_SYNC 0xc3UL
194 #define HWRM_FW_SET_TIME 0xc8UL 198 #define HWRM_FW_SET_TIME 0xc8UL
195 #define HWRM_FW_GET_TIME 0xc9UL 199 #define HWRM_FW_GET_TIME 0xc9UL
196 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 200 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
@@ -269,6 +273,11 @@ struct cmd_nums {
269 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 273 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
270 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 274 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
271 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 275 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
276 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
277 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
278 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
279 #define HWRM_FUNC_VF_BW_CFG 0x195UL
280 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
272 #define HWRM_SELFTEST_QLIST 0x200UL 281 #define HWRM_SELFTEST_QLIST 0x200UL
273 #define HWRM_SELFTEST_EXEC 0x201UL 282 #define HWRM_SELFTEST_EXEC 0x201UL
274 #define HWRM_SELFTEST_IRQ 0x202UL 283 #define HWRM_SELFTEST_IRQ 0x202UL
@@ -284,6 +293,8 @@ struct cmd_nums {
284 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 293 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
285 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 294 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
286 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 295 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
296 #define HWRM_DBG_FW_CLI 0xff1aUL
297 #define HWRM_DBG_I2C_CMD 0xff1bUL
287 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 298 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
288 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 299 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
289 #define HWRM_NVM_FLUSH 0xfff0UL 300 #define HWRM_NVM_FLUSH 0xfff0UL
@@ -318,6 +329,7 @@ struct ret_codes {
318 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 329 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
319 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 330 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
320 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 331 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
332 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
321 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 333 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
322 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 334 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
323 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 335 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
@@ -344,9 +356,9 @@ struct hwrm_err_output {
344#define HWRM_RESP_VALID_KEY 1 356#define HWRM_RESP_VALID_KEY 1
345#define HWRM_VERSION_MAJOR 1 357#define HWRM_VERSION_MAJOR 1
346#define HWRM_VERSION_MINOR 9 358#define HWRM_VERSION_MINOR 9
347#define HWRM_VERSION_UPDATE 1 359#define HWRM_VERSION_UPDATE 2
348#define HWRM_VERSION_RSVD 15 360#define HWRM_VERSION_RSVD 25
349#define HWRM_VERSION_STR "1.9.1.15" 361#define HWRM_VERSION_STR "1.9.2.25"
350 362
351/* hwrm_ver_get_input (size:192b/24B) */ 363/* hwrm_ver_get_input (size:192b/24B) */
352struct hwrm_ver_get_input { 364struct hwrm_ver_get_input {
@@ -526,6 +538,7 @@ struct hwrm_async_event_cmpl {
526 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 538 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
527 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 539 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
528 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 540 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
541 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
529 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 542 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
530 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 543 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
531 __le32 event_data2; 544 __le32 event_data2;
@@ -564,6 +577,8 @@ struct hwrm_async_event_cmpl_link_status_change {
564 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 577 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
565 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 578 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
566 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 579 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
580 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
581 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
567}; 582};
568 583
569/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 584/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
@@ -817,23 +832,26 @@ struct hwrm_func_qcaps_output {
817 __le16 fid; 832 __le16 fid;
818 __le16 port_id; 833 __le16 port_id;
819 __le32 flags; 834 __le32 flags;
820 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 835 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
821 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 836 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
822 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 837 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
823 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 838 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
824 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 839 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
825 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 840 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
826 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 841 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
827 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 842 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
828 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 843 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
829 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 844 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
830 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 845 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
831 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 846 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
832 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 847 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
833 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 848 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
834 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 849 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
835 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 850 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
836 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 851 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
852 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
853 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
854 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
837 u8 mac_address[6]; 855 u8 mac_address[6];
838 __le16 max_rsscos_ctx; 856 __le16 max_rsscos_ctx;
839 __le16 max_cmpl_rings; 857 __le16 max_cmpl_rings;
@@ -947,58 +965,26 @@ struct hwrm_func_qcfg_output {
947 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 965 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
948 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 966 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
949 u8 options; 967 u8 options;
950 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 968 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
951 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 969 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
952 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 970 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
953 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 971 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
954 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 972 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
955 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xfcUL 973 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
956 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 2 974 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
975 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
976 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
977 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
978 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
979 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
980 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
957 __le16 alloc_vfs; 981 __le16 alloc_vfs;
958 __le32 alloc_mcast_filters; 982 __le32 alloc_mcast_filters;
959 __le32 alloc_hw_ring_grps; 983 __le32 alloc_hw_ring_grps;
960 __le16 alloc_sp_tx_rings; 984 __le16 alloc_sp_tx_rings;
961 __le16 alloc_stat_ctx; 985 __le16 alloc_stat_ctx;
962 u8 unused_2[7]; 986 __le16 alloc_msix;
963 u8 valid; 987 u8 unused_2[5];
964};
965
966/* hwrm_func_vlan_cfg_input (size:384b/48B) */
967struct hwrm_func_vlan_cfg_input {
968 __le16 req_type;
969 __le16 cmpl_ring;
970 __le16 seq_id;
971 __le16 target_id;
972 __le64 resp_addr;
973 __le16 fid;
974 u8 unused_0[2];
975 __le32 enables;
976 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL
977 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL
978 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL
979 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL
980 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL
981 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL
982 __le16 stag_vid;
983 u8 stag_pcp;
984 u8 unused_1;
985 __be16 stag_tpid;
986 __le16 ctag_vid;
987 u8 ctag_pcp;
988 u8 unused_2;
989 __be16 ctag_tpid;
990 __le32 rsvd1;
991 __le32 rsvd2;
992 u8 unused_3[4];
993};
994
995/* hwrm_func_vlan_cfg_output (size:128b/16B) */
996struct hwrm_func_vlan_cfg_output {
997 __le16 error_code;
998 __le16 req_type;
999 __le16 seq_id;
1000 __le16 resp_len;
1001 u8 unused_0[7];
1002 u8 valid; 988 u8 valid;
1003}; 989};
1004 990
@@ -1010,7 +996,7 @@ struct hwrm_func_cfg_input {
1010 __le16 target_id; 996 __le16 target_id;
1011 __le64 resp_addr; 997 __le64 resp_addr;
1012 __le16 fid; 998 __le16 fid;
1013 u8 unused_0[2]; 999 __le16 num_msix;
1014 __le32 flags; 1000 __le32 flags;
1015 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1001 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1016 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1002 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
@@ -1050,6 +1036,8 @@ struct hwrm_func_cfg_input {
1050 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1036 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1051 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1037 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1052 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1038 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1039 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1040 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1053 __le16 mtu; 1041 __le16 mtu;
1054 __le16 mru; 1042 __le16 mru;
1055 __le16 num_rsscos_ctxs; 1043 __le16 num_rsscos_ctxs;
@@ -1109,13 +1097,19 @@ struct hwrm_func_cfg_input {
1109 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1097 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1110 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1098 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1111 u8 options; 1099 u8 options;
1112 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1100 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1113 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1101 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1114 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1102 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1115 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1103 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1116 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1104 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1117 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xfcUL 1105 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1118 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 2 1106 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1107 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1108 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1109 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1110 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1111 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1112 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1119 __le16 num_mcast_filters; 1113 __le16 num_mcast_filters;
1120}; 1114};
1121 1115
@@ -1212,30 +1206,6 @@ struct hwrm_func_vf_resc_free_output {
1212 u8 valid; 1206 u8 valid;
1213}; 1207};
1214 1208
1215/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
1216struct hwrm_func_vf_vnic_ids_query_input {
1217 __le16 req_type;
1218 __le16 cmpl_ring;
1219 __le16 seq_id;
1220 __le16 target_id;
1221 __le64 resp_addr;
1222 __le16 vf_id;
1223 u8 unused_0[2];
1224 __le32 max_vnic_id_cnt;
1225 __le64 vnic_id_tbl_addr;
1226};
1227
1228/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
1229struct hwrm_func_vf_vnic_ids_query_output {
1230 __le16 error_code;
1231 __le16 req_type;
1232 __le16 seq_id;
1233 __le16 resp_len;
1234 __le32 vnic_id_cnt;
1235 u8 unused_0[3];
1236 u8 valid;
1237};
1238
1239/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1209/* hwrm_func_drv_rgtr_input (size:896b/112B) */
1240struct hwrm_func_drv_rgtr_input { 1210struct hwrm_func_drv_rgtr_input {
1241 __le16 req_type; 1211 __le16 req_type;
@@ -1286,7 +1256,9 @@ struct hwrm_func_drv_rgtr_output {
1286 __le16 req_type; 1256 __le16 req_type;
1287 __le16 seq_id; 1257 __le16 seq_id;
1288 __le16 resp_len; 1258 __le16 resp_len;
1289 u8 unused_0[7]; 1259 __le32 flags;
1260 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1261 u8 unused_0[3];
1290 u8 valid; 1262 u8 valid;
1291}; 1263};
1292 1264
@@ -1372,7 +1344,7 @@ struct hwrm_func_drv_qver_input {
1372 u8 unused_0[2]; 1344 u8 unused_0[2];
1373}; 1345};
1374 1346
1375/* hwrm_func_drv_qver_output (size:192b/24B) */ 1347/* hwrm_func_drv_qver_output (size:256b/32B) */
1376struct hwrm_func_drv_qver_output { 1348struct hwrm_func_drv_qver_output {
1377 __le16 error_code; 1349 __le16 error_code;
1378 __le16 req_type; 1350 __le16 req_type;
@@ -1394,12 +1366,13 @@ struct hwrm_func_drv_qver_output {
1394 u8 ver_maj_8b; 1366 u8 ver_maj_8b;
1395 u8 ver_min_8b; 1367 u8 ver_min_8b;
1396 u8 ver_upd_8b; 1368 u8 ver_upd_8b;
1397 u8 unused_0[2]; 1369 u8 unused_0[3];
1398 u8 valid;
1399 __le16 ver_maj; 1370 __le16 ver_maj;
1400 __le16 ver_min; 1371 __le16 ver_min;
1401 __le16 ver_upd; 1372 __le16 ver_upd;
1402 __le16 ver_patch; 1373 __le16 ver_patch;
1374 u8 unused_1[7];
1375 u8 valid;
1403}; 1376};
1404 1377
1405/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1378/* hwrm_func_resource_qcaps_input (size:192b/24B) */
@@ -1493,6 +1466,410 @@ struct hwrm_func_vf_resource_cfg_output {
1493 u8 valid; 1466 u8 valid;
1494}; 1467};
1495 1468
1469/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1470struct hwrm_func_backing_store_qcaps_input {
1471 __le16 req_type;
1472 __le16 cmpl_ring;
1473 __le16 seq_id;
1474 __le16 target_id;
1475 __le64 resp_addr;
1476};
1477
1478/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
1479struct hwrm_func_backing_store_qcaps_output {
1480 __le16 error_code;
1481 __le16 req_type;
1482 __le16 seq_id;
1483 __le16 resp_len;
1484 __le32 qp_max_entries;
1485 __le16 qp_min_qp1_entries;
1486 __le16 qp_max_l2_entries;
1487 __le16 qp_entry_size;
1488 __le16 srq_max_l2_entries;
1489 __le32 srq_max_entries;
1490 __le16 srq_entry_size;
1491 __le16 cq_max_l2_entries;
1492 __le32 cq_max_entries;
1493 __le16 cq_entry_size;
1494 __le16 vnic_max_vnic_entries;
1495 __le16 vnic_max_ring_table_entries;
1496 __le16 vnic_entry_size;
1497 __le32 stat_max_entries;
1498 __le16 stat_entry_size;
1499 __le16 tqm_entry_size;
1500 __le32 tqm_min_entries_per_ring;
1501 __le32 tqm_max_entries_per_ring;
1502 __le32 mrav_max_entries;
1503 __le16 mrav_entry_size;
1504 __le16 tim_entry_size;
1505 __le32 tim_max_entries;
1506 u8 unused_0[3];
1507 u8 valid;
1508};
1509
1510/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
1511struct hwrm_func_backing_store_cfg_input {
1512 __le16 req_type;
1513 __le16 cmpl_ring;
1514 __le16 seq_id;
1515 __le16 target_id;
1516 __le64 resp_addr;
1517 __le32 flags;
1518 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
1519 __le32 enables;
1520 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
1521 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
1522 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
1523 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
1524 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
1525 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
1526 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
1527 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
1528 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
1529 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
1530 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
1531 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
1532 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
1533 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
1534 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
1535 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
1536 u8 qpc_pg_size_qpc_lvl;
1537 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
1538 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
1539 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
1540 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
1541 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
1542 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
1543 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
1544 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
1545 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
1546 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
1547 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
1548 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
1549 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
1550 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
1551 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
1552 u8 srq_pg_size_srq_lvl;
1553 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
1554 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
1555 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
1556 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
1557 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
1558 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
1559 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
1560 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
1561 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
1562 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
1563 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
1564 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
1565 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
1566 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
1567 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
1568 u8 cq_pg_size_cq_lvl;
1569 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
1570 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
1571 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
1572 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
1573 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
1574 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
1575 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
1576 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
1577 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
1578 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
1579 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
1580 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
1581 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
1582 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
1583 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
1584 u8 vnic_pg_size_vnic_lvl;
1585 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
1586 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
1587 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
1588 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
1589 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
1590 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
1591 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
1592 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
1593 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
1594 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
1595 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
1596 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
1597 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
1598 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
1599 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
1600 u8 stat_pg_size_stat_lvl;
1601 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
1602 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
1603 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
1604 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
1605 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
1606 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
1607 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
1608 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
1609 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
1610 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
1611 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
1612 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
1613 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
1614 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
1615 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
1616 u8 tqm_sp_pg_size_tqm_sp_lvl;
1617 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
1618 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
1619 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
1620 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
1621 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
1622 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
1623 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
1624 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
1625 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
1626 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
1627 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
1628 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
1629 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
1630 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
1631 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
1632 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
1633 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
1634 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
1635 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
1636 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
1637 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
1638 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
1639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
1640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
1641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
1642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
1643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
1644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
1645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
1646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
1647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
1648 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
1649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
1650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
1651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
1652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
1653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
1654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
1655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
1656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
1657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
1658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
1659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
1660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
1661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
1662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
1663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
1664 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
1665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
1666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
1667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
1668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
1669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
1670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
1671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
1672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
1673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
1674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
1675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
1676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
1677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
1678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
1679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
1680 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
1681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
1682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
1683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
1684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
1685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
1686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
1687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
1688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
1689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
1690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
1691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
1692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
1693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
1694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
1695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
1696 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
1697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
1698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
1699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
1700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
1701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
1702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
1703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
1704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
1705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
1706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
1707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
1708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
1709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
1710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
1711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
1712 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
1713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
1714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
1715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
1716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
1717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
1718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
1719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
1720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
1721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
1722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
1723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
1724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
1725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
1726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
1727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
1728 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
1729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
1730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
1731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
1732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
1733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
1734 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
1735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
1736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
1737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
1738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
1739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
1740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
1741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
1742 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
1743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
1744 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
1745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
1746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
1747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
1748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
1749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
1750 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
1751 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
1752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
1753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
1754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
1755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
1756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
1757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
1758 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
1759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
1760 u8 mrav_pg_size_mrav_lvl;
1761 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
1762 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
1763 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
1764 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
1765 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
1766 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
1767 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
1768 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
1769 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
1770 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
1771 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
1772 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
1773 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
1774 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
1775 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
1776 u8 tim_pg_size_tim_lvl;
1777 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
1778 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
1779 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
1780 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
1781 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
1782 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
1783 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
1784 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
1785 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
1786 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
1787 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
1788 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
1789 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
1790 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
1791 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
1792 __le64 qpc_page_dir;
1793 __le64 srq_page_dir;
1794 __le64 cq_page_dir;
1795 __le64 vnic_page_dir;
1796 __le64 stat_page_dir;
1797 __le64 tqm_sp_page_dir;
1798 __le64 tqm_ring0_page_dir;
1799 __le64 tqm_ring1_page_dir;
1800 __le64 tqm_ring2_page_dir;
1801 __le64 tqm_ring3_page_dir;
1802 __le64 tqm_ring4_page_dir;
1803 __le64 tqm_ring5_page_dir;
1804 __le64 tqm_ring6_page_dir;
1805 __le64 tqm_ring7_page_dir;
1806 __le64 mrav_page_dir;
1807 __le64 tim_page_dir;
1808 __le32 qp_num_entries;
1809 __le32 srq_num_entries;
1810 __le32 cq_num_entries;
1811 __le32 stat_num_entries;
1812 __le32 tqm_sp_num_entries;
1813 __le32 tqm_ring0_num_entries;
1814 __le32 tqm_ring1_num_entries;
1815 __le32 tqm_ring2_num_entries;
1816 __le32 tqm_ring3_num_entries;
1817 __le32 tqm_ring4_num_entries;
1818 __le32 tqm_ring5_num_entries;
1819 __le32 tqm_ring6_num_entries;
1820 __le32 tqm_ring7_num_entries;
1821 __le32 mrav_num_entries;
1822 __le32 tim_num_entries;
1823 __le16 qp_num_qp1_entries;
1824 __le16 qp_num_l2_entries;
1825 __le16 qp_entry_size;
1826 __le16 srq_num_l2_entries;
1827 __le16 srq_entry_size;
1828 __le16 cq_num_l2_entries;
1829 __le16 cq_entry_size;
1830 __le16 vnic_num_vnic_entries;
1831 __le16 vnic_num_ring_table_entries;
1832 __le16 vnic_entry_size;
1833 __le16 stat_entry_size;
1834 __le16 tqm_entry_size;
1835 __le16 mrav_entry_size;
1836 __le16 tim_entry_size;
1837};
1838
1839/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
1840struct hwrm_func_backing_store_cfg_output {
1841 __le16 error_code;
1842 __le16 req_type;
1843 __le16 seq_id;
1844 __le16 resp_len;
1845 u8 unused_0[7];
1846 u8 valid;
1847};
1848
1849/* hwrm_func_drv_if_change_input (size:192b/24B) */
1850struct hwrm_func_drv_if_change_input {
1851 __le16 req_type;
1852 __le16 cmpl_ring;
1853 __le16 seq_id;
1854 __le16 target_id;
1855 __le64 resp_addr;
1856 __le32 flags;
1857 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
1858 __le32 unused;
1859};
1860
1861/* hwrm_func_drv_if_change_output (size:128b/16B) */
1862struct hwrm_func_drv_if_change_output {
1863 __le16 error_code;
1864 __le16 req_type;
1865 __le16 seq_id;
1866 __le16 resp_len;
1867 __le32 flags;
1868 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
1869 u8 unused_0[3];
1870 u8 valid;
1871};
1872
1496/* hwrm_port_phy_cfg_input (size:448b/56B) */ 1873/* hwrm_port_phy_cfg_input (size:448b/56B) */
1497struct hwrm_port_phy_cfg_input { 1874struct hwrm_port_phy_cfg_input {
1498 __le16 req_type; 1875 __le16 req_type;
@@ -1592,10 +1969,11 @@ struct hwrm_port_phy_cfg_input {
1592 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1969 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
1593 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 1970 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
1594 u8 lpbk; 1971 u8 lpbk;
1595 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1972 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
1596 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1973 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
1597 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1974 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
1598 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_REMOTE 1975 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
1976 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
1599 u8 force_pause; 1977 u8 force_pause;
1600 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1978 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1601 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1979 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
@@ -1751,10 +2129,11 @@ struct hwrm_port_phy_qcfg_output {
1751 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2129 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
1752 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2130 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
1753 u8 lpbk; 2131 u8 lpbk;
1754 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2132 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
1755 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2133 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
1756 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2134 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
1757 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_REMOTE 2135 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2136 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
1758 u8 force_pause; 2137 u8 force_pause;
1759 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2138 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1760 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2139 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
@@ -2014,6 +2393,131 @@ struct hwrm_port_mac_ptp_qcfg_output {
2014 u8 valid; 2393 u8 valid;
2015}; 2394};
2016 2395
2396/* tx_port_stats (size:3264b/408B) */
2397struct tx_port_stats {
2398 __le64 tx_64b_frames;
2399 __le64 tx_65b_127b_frames;
2400 __le64 tx_128b_255b_frames;
2401 __le64 tx_256b_511b_frames;
2402 __le64 tx_512b_1023b_frames;
2403 __le64 tx_1024b_1518b_frames;
2404 __le64 tx_good_vlan_frames;
2405 __le64 tx_1519b_2047b_frames;
2406 __le64 tx_2048b_4095b_frames;
2407 __le64 tx_4096b_9216b_frames;
2408 __le64 tx_9217b_16383b_frames;
2409 __le64 tx_good_frames;
2410 __le64 tx_total_frames;
2411 __le64 tx_ucast_frames;
2412 __le64 tx_mcast_frames;
2413 __le64 tx_bcast_frames;
2414 __le64 tx_pause_frames;
2415 __le64 tx_pfc_frames;
2416 __le64 tx_jabber_frames;
2417 __le64 tx_fcs_err_frames;
2418 __le64 tx_control_frames;
2419 __le64 tx_oversz_frames;
2420 __le64 tx_single_dfrl_frames;
2421 __le64 tx_multi_dfrl_frames;
2422 __le64 tx_single_coll_frames;
2423 __le64 tx_multi_coll_frames;
2424 __le64 tx_late_coll_frames;
2425 __le64 tx_excessive_coll_frames;
2426 __le64 tx_frag_frames;
2427 __le64 tx_err;
2428 __le64 tx_tagged_frames;
2429 __le64 tx_dbl_tagged_frames;
2430 __le64 tx_runt_frames;
2431 __le64 tx_fifo_underruns;
2432 __le64 tx_pfc_ena_frames_pri0;
2433 __le64 tx_pfc_ena_frames_pri1;
2434 __le64 tx_pfc_ena_frames_pri2;
2435 __le64 tx_pfc_ena_frames_pri3;
2436 __le64 tx_pfc_ena_frames_pri4;
2437 __le64 tx_pfc_ena_frames_pri5;
2438 __le64 tx_pfc_ena_frames_pri6;
2439 __le64 tx_pfc_ena_frames_pri7;
2440 __le64 tx_eee_lpi_events;
2441 __le64 tx_eee_lpi_duration;
2442 __le64 tx_llfc_logical_msgs;
2443 __le64 tx_hcfc_msgs;
2444 __le64 tx_total_collisions;
2445 __le64 tx_bytes;
2446 __le64 tx_xthol_frames;
2447 __le64 tx_stat_discard;
2448 __le64 tx_stat_error;
2449};
2450
2451/* rx_port_stats (size:4224b/528B) */
2452struct rx_port_stats {
2453 __le64 rx_64b_frames;
2454 __le64 rx_65b_127b_frames;
2455 __le64 rx_128b_255b_frames;
2456 __le64 rx_256b_511b_frames;
2457 __le64 rx_512b_1023b_frames;
2458 __le64 rx_1024b_1518b_frames;
2459 __le64 rx_good_vlan_frames;
2460 __le64 rx_1519b_2047b_frames;
2461 __le64 rx_2048b_4095b_frames;
2462 __le64 rx_4096b_9216b_frames;
2463 __le64 rx_9217b_16383b_frames;
2464 __le64 rx_total_frames;
2465 __le64 rx_ucast_frames;
2466 __le64 rx_mcast_frames;
2467 __le64 rx_bcast_frames;
2468 __le64 rx_fcs_err_frames;
2469 __le64 rx_ctrl_frames;
2470 __le64 rx_pause_frames;
2471 __le64 rx_pfc_frames;
2472 __le64 rx_unsupported_opcode_frames;
2473 __le64 rx_unsupported_da_pausepfc_frames;
2474 __le64 rx_wrong_sa_frames;
2475 __le64 rx_align_err_frames;
2476 __le64 rx_oor_len_frames;
2477 __le64 rx_code_err_frames;
2478 __le64 rx_false_carrier_frames;
2479 __le64 rx_ovrsz_frames;
2480 __le64 rx_jbr_frames;
2481 __le64 rx_mtu_err_frames;
2482 __le64 rx_match_crc_frames;
2483 __le64 rx_promiscuous_frames;
2484 __le64 rx_tagged_frames;
2485 __le64 rx_double_tagged_frames;
2486 __le64 rx_trunc_frames;
2487 __le64 rx_good_frames;
2488 __le64 rx_pfc_xon2xoff_frames_pri0;
2489 __le64 rx_pfc_xon2xoff_frames_pri1;
2490 __le64 rx_pfc_xon2xoff_frames_pri2;
2491 __le64 rx_pfc_xon2xoff_frames_pri3;
2492 __le64 rx_pfc_xon2xoff_frames_pri4;
2493 __le64 rx_pfc_xon2xoff_frames_pri5;
2494 __le64 rx_pfc_xon2xoff_frames_pri6;
2495 __le64 rx_pfc_xon2xoff_frames_pri7;
2496 __le64 rx_pfc_ena_frames_pri0;
2497 __le64 rx_pfc_ena_frames_pri1;
2498 __le64 rx_pfc_ena_frames_pri2;
2499 __le64 rx_pfc_ena_frames_pri3;
2500 __le64 rx_pfc_ena_frames_pri4;
2501 __le64 rx_pfc_ena_frames_pri5;
2502 __le64 rx_pfc_ena_frames_pri6;
2503 __le64 rx_pfc_ena_frames_pri7;
2504 __le64 rx_sch_crc_err_frames;
2505 __le64 rx_undrsz_frames;
2506 __le64 rx_frag_frames;
2507 __le64 rx_eee_lpi_events;
2508 __le64 rx_eee_lpi_duration;
2509 __le64 rx_llfc_physical_msgs;
2510 __le64 rx_llfc_logical_msgs;
2511 __le64 rx_llfc_msgs_with_crc_err;
2512 __le64 rx_hcfc_msgs;
2513 __le64 rx_hcfc_msgs_with_crc_err;
2514 __le64 rx_bytes;
2515 __le64 rx_runt_bytes;
2516 __le64 rx_runt_frames;
2517 __le64 rx_stat_discard;
2518 __le64 rx_stat_err;
2519};
2520
2017/* hwrm_port_qstats_input (size:320b/40B) */ 2521/* hwrm_port_qstats_input (size:320b/40B) */
2018struct hwrm_port_qstats_input { 2522struct hwrm_port_qstats_input {
2019 __le16 req_type; 2523 __le16 req_type;
@@ -2039,6 +2543,83 @@ struct hwrm_port_qstats_output {
2039 u8 valid; 2543 u8 valid;
2040}; 2544};
2041 2545
2546/* tx_port_stats_ext (size:2048b/256B) */
2547struct tx_port_stats_ext {
2548 __le64 tx_bytes_cos0;
2549 __le64 tx_bytes_cos1;
2550 __le64 tx_bytes_cos2;
2551 __le64 tx_bytes_cos3;
2552 __le64 tx_bytes_cos4;
2553 __le64 tx_bytes_cos5;
2554 __le64 tx_bytes_cos6;
2555 __le64 tx_bytes_cos7;
2556 __le64 tx_packets_cos0;
2557 __le64 tx_packets_cos1;
2558 __le64 tx_packets_cos2;
2559 __le64 tx_packets_cos3;
2560 __le64 tx_packets_cos4;
2561 __le64 tx_packets_cos5;
2562 __le64 tx_packets_cos6;
2563 __le64 tx_packets_cos7;
2564 __le64 pfc_pri0_tx_duration_us;
2565 __le64 pfc_pri0_tx_transitions;
2566 __le64 pfc_pri1_tx_duration_us;
2567 __le64 pfc_pri1_tx_transitions;
2568 __le64 pfc_pri2_tx_duration_us;
2569 __le64 pfc_pri2_tx_transitions;
2570 __le64 pfc_pri3_tx_duration_us;
2571 __le64 pfc_pri3_tx_transitions;
2572 __le64 pfc_pri4_tx_duration_us;
2573 __le64 pfc_pri4_tx_transitions;
2574 __le64 pfc_pri5_tx_duration_us;
2575 __le64 pfc_pri5_tx_transitions;
2576 __le64 pfc_pri6_tx_duration_us;
2577 __le64 pfc_pri6_tx_transitions;
2578 __le64 pfc_pri7_tx_duration_us;
2579 __le64 pfc_pri7_tx_transitions;
2580};
2581
2582/* rx_port_stats_ext (size:2368b/296B) */
2583struct rx_port_stats_ext {
2584 __le64 link_down_events;
2585 __le64 continuous_pause_events;
2586 __le64 resume_pause_events;
2587 __le64 continuous_roce_pause_events;
2588 __le64 resume_roce_pause_events;
2589 __le64 rx_bytes_cos0;
2590 __le64 rx_bytes_cos1;
2591 __le64 rx_bytes_cos2;
2592 __le64 rx_bytes_cos3;
2593 __le64 rx_bytes_cos4;
2594 __le64 rx_bytes_cos5;
2595 __le64 rx_bytes_cos6;
2596 __le64 rx_bytes_cos7;
2597 __le64 rx_packets_cos0;
2598 __le64 rx_packets_cos1;
2599 __le64 rx_packets_cos2;
2600 __le64 rx_packets_cos3;
2601 __le64 rx_packets_cos4;
2602 __le64 rx_packets_cos5;
2603 __le64 rx_packets_cos6;
2604 __le64 rx_packets_cos7;
2605 __le64 pfc_pri0_rx_duration_us;
2606 __le64 pfc_pri0_rx_transitions;
2607 __le64 pfc_pri1_rx_duration_us;
2608 __le64 pfc_pri1_rx_transitions;
2609 __le64 pfc_pri2_rx_duration_us;
2610 __le64 pfc_pri2_rx_transitions;
2611 __le64 pfc_pri3_rx_duration_us;
2612 __le64 pfc_pri3_rx_transitions;
2613 __le64 pfc_pri4_rx_duration_us;
2614 __le64 pfc_pri4_rx_transitions;
2615 __le64 pfc_pri5_rx_duration_us;
2616 __le64 pfc_pri5_rx_transitions;
2617 __le64 pfc_pri6_rx_duration_us;
2618 __le64 pfc_pri6_rx_transitions;
2619 __le64 pfc_pri7_rx_duration_us;
2620 __le64 pfc_pri7_rx_transitions;
2621};
2622
2042/* hwrm_port_qstats_ext_input (size:320b/40B) */ 2623/* hwrm_port_qstats_ext_input (size:320b/40B) */
2043struct hwrm_port_qstats_ext_input { 2624struct hwrm_port_qstats_ext_input {
2044 __le16 req_type; 2625 __le16 req_type;
@@ -2062,7 +2643,8 @@ struct hwrm_port_qstats_ext_output {
2062 __le16 resp_len; 2643 __le16 resp_len;
2063 __le16 tx_stat_size; 2644 __le16 tx_stat_size;
2064 __le16 rx_stat_size; 2645 __le16 rx_stat_size;
2065 u8 unused_0[3]; 2646 __le16 total_active_cos_queues;
2647 u8 unused_0;
2066 u8 valid; 2648 u8 valid;
2067}; 2649};
2068 2650
@@ -2153,9 +2735,10 @@ struct hwrm_port_phy_qcaps_output {
2153 __le16 seq_id; 2735 __le16 seq_id;
2154 __le16 resp_len; 2736 __le16 resp_len;
2155 u8 flags; 2737 u8 flags;
2156 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2738 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
2157 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 2739 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
2158 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 2740 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL
2741 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2
2159 u8 port_cnt; 2742 u8 port_cnt;
2160 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2743 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
2161 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2744 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
@@ -2612,6 +3195,7 @@ struct hwrm_queue_qportcfg_output {
2612 u8 queue_id0; 3195 u8 queue_id0;
2613 u8 queue_id0_service_profile; 3196 u8 queue_id0_service_profile;
2614 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3197 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
3198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
2615 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3199 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2616 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3200 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2617 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3201 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2620,6 +3204,7 @@ struct hwrm_queue_qportcfg_output {
2620 u8 queue_id1; 3204 u8 queue_id1;
2621 u8 queue_id1_service_profile; 3205 u8 queue_id1_service_profile;
2622 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3206 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
3207 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
2623 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2624 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2625 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2628,6 +3213,7 @@ struct hwrm_queue_qportcfg_output {
2628 u8 queue_id2; 3213 u8 queue_id2;
2629 u8 queue_id2_service_profile; 3214 u8 queue_id2_service_profile;
2630 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
3216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
2631 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2632 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2633 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2636,6 +3222,7 @@ struct hwrm_queue_qportcfg_output {
2636 u8 queue_id3; 3222 u8 queue_id3;
2637 u8 queue_id3_service_profile; 3223 u8 queue_id3_service_profile;
2638 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
3225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
2639 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3226 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2640 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3227 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2641 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2644,6 +3231,7 @@ struct hwrm_queue_qportcfg_output {
2644 u8 queue_id4; 3231 u8 queue_id4;
2645 u8 queue_id4_service_profile; 3232 u8 queue_id4_service_profile;
2646 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
3234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
2647 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2648 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3236 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2649 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2652,6 +3240,7 @@ struct hwrm_queue_qportcfg_output {
2652 u8 queue_id5; 3240 u8 queue_id5;
2653 u8 queue_id5_service_profile; 3241 u8 queue_id5_service_profile;
2654 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
3243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
2655 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2656 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2657 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2660,6 +3249,7 @@ struct hwrm_queue_qportcfg_output {
2660 u8 queue_id6; 3249 u8 queue_id6;
2661 u8 queue_id6_service_profile; 3250 u8 queue_id6_service_profile;
2662 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3251 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
3252 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
2663 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2664 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2665 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -2668,6 +3258,7 @@ struct hwrm_queue_qportcfg_output {
2668 u8 queue_id7; 3258 u8 queue_id7;
2669 u8 queue_id7_service_profile; 3259 u8 queue_id7_service_profile;
2670 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3260 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
3261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
2671 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
2672 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3263 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
2673 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
@@ -3689,18 +4280,21 @@ struct hwrm_vnic_cfg_input {
3689 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4280 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
3690 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4281 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
3691 __le32 enables; 4282 __le32 enables;
3692 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4283 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
3693 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4284 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
3694 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4285 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
3695 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4286 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
3696 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4287 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
4288 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
4289 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
3697 __le16 vnic_id; 4290 __le16 vnic_id;
3698 __le16 dflt_ring_grp; 4291 __le16 dflt_ring_grp;
3699 __le16 rss_rule; 4292 __le16 rss_rule;
3700 __le16 cos_rule; 4293 __le16 cos_rule;
3701 __le16 lb_rule; 4294 __le16 lb_rule;
3702 __le16 mru; 4295 __le16 mru;
3703 u8 unused_0[4]; 4296 __le16 default_rx_ring_id;
4297 __le16 default_cmpl_ring_id;
3704}; 4298};
3705 4299
3706/* hwrm_vnic_cfg_output (size:128b/16B) */ 4300/* hwrm_vnic_cfg_output (size:128b/16B) */
@@ -3740,6 +4334,7 @@ struct hwrm_vnic_qcaps_output {
3740 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4334 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
3741 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4335 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
3742 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4336 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
4337 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
3743 u8 unused_1[7]; 4338 u8 unused_1[7];
3744 u8 valid; 4339 u8 valid;
3745}; 4340};
@@ -3857,7 +4452,14 @@ struct hwrm_vnic_rss_cfg_input {
3857 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4452 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
3858 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4453 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
3859 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4454 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
3860 u8 unused_0[4]; 4455 __le16 vnic_id;
4456 u8 ring_table_pair_index;
4457 u8 hash_mode_flags;
4458 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
4459 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
4460 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
4461 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
4462 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
3861 __le64 ring_grp_tbl_addr; 4463 __le64 ring_grp_tbl_addr;
3862 __le64 hash_key_tbl_addr; 4464 __le64 hash_key_tbl_addr;
3863 __le16 rss_ctx_idx; 4465 __le16 rss_ctx_idx;
@@ -3950,7 +4552,7 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output {
3950 u8 valid; 4552 u8 valid;
3951}; 4553};
3952 4554
3953/* hwrm_ring_alloc_input (size:640b/80B) */ 4555/* hwrm_ring_alloc_input (size:704b/88B) */
3954struct hwrm_ring_alloc_input { 4556struct hwrm_ring_alloc_input {
3955 __le16 req_type; 4557 __le16 req_type;
3956 __le16 cmpl_ring; 4558 __le16 cmpl_ring;
@@ -3961,12 +4563,17 @@ struct hwrm_ring_alloc_input {
3961 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 4563 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
3962 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 4564 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
3963 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 4565 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
4566 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
4567 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
4568 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
3964 u8 ring_type; 4569 u8 ring_type;
3965 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 4570 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
3966 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 4571 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
3967 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 4572 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
3968 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4573 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
3969 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 4574 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
4575 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
4576 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
3970 u8 unused_0[3]; 4577 u8 unused_0[3];
3971 __le64 page_tbl_addr; 4578 __le64 page_tbl_addr;
3972 __le32 fbo; 4579 __le32 fbo;
@@ -3977,8 +4584,9 @@ struct hwrm_ring_alloc_input {
3977 __le16 logical_id; 4584 __le16 logical_id;
3978 __le16 cmpl_ring_id; 4585 __le16 cmpl_ring_id;
3979 __le16 queue_id; 4586 __le16 queue_id;
3980 u8 unused_2[2]; 4587 __le16 rx_buf_size;
3981 __le32 reserved1; 4588 __le16 rx_ring_id;
4589 __le16 nq_ring_id;
3982 __le16 ring_arb_cfg; 4590 __le16 ring_arb_cfg;
3983 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 4591 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
3984 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 4592 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
@@ -4016,6 +4624,7 @@ struct hwrm_ring_alloc_input {
4016 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 4624 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
4017 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 4625 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
4018 u8 unused_4[3]; 4626 u8 unused_4[3];
4627 __le64 cq_handle;
4019}; 4628};
4020 4629
4021/* hwrm_ring_alloc_output (size:128b/16B) */ 4630/* hwrm_ring_alloc_output (size:128b/16B) */
@@ -4042,7 +4651,9 @@ struct hwrm_ring_free_input {
4042 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 4651 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
4043 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 4652 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
4044 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4653 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4045 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_ROCE_CMPL 4654 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
4655 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
4656 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
4046 u8 unused_0; 4657 u8 unused_0;
4047 __le16 ring_id; 4658 __le16 ring_id;
4048 u8 unused_1[4]; 4659 u8 unused_1[4];
@@ -4058,6 +4669,52 @@ struct hwrm_ring_free_output {
4058 u8 valid; 4669 u8 valid;
4059}; 4670};
4060 4671
4672/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
4673struct hwrm_ring_aggint_qcaps_input {
4674 __le16 req_type;
4675 __le16 cmpl_ring;
4676 __le16 seq_id;
4677 __le16 target_id;
4678 __le64 resp_addr;
4679};
4680
4681/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
4682struct hwrm_ring_aggint_qcaps_output {
4683 __le16 error_code;
4684 __le16 req_type;
4685 __le16 seq_id;
4686 __le16 resp_len;
4687 __le32 cmpl_params;
4688 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
4689 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
4690 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
4691 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
4692 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
4693 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
4694 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
4695 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
4696 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
4697 __le32 nq_params;
4698 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
4699 __le16 num_cmpl_dma_aggr_min;
4700 __le16 num_cmpl_dma_aggr_max;
4701 __le16 num_cmpl_dma_aggr_during_int_min;
4702 __le16 num_cmpl_dma_aggr_during_int_max;
4703 __le16 cmpl_aggr_dma_tmr_min;
4704 __le16 cmpl_aggr_dma_tmr_max;
4705 __le16 cmpl_aggr_dma_tmr_during_int_min;
4706 __le16 cmpl_aggr_dma_tmr_during_int_max;
4707 __le16 int_lat_tmr_min_min;
4708 __le16 int_lat_tmr_min_max;
4709 __le16 int_lat_tmr_max_min;
4710 __le16 int_lat_tmr_max_max;
4711 __le16 num_cmpl_aggr_int_min;
4712 __le16 num_cmpl_aggr_int_max;
4713 __le16 timer_units;
4714 u8 unused_0[1];
4715 u8 valid;
4716};
4717
4061/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 4718/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
4062struct hwrm_ring_cmpl_ring_qaggint_params_input { 4719struct hwrm_ring_cmpl_ring_qaggint_params_input {
4063 __le16 req_type; 4720 __le16 req_type;
@@ -4100,6 +4757,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
4100 __le16 flags; 4757 __le16 flags;
4101 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 4758 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
4102 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 4759 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
4760 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
4103 __le16 num_cmpl_dma_aggr; 4761 __le16 num_cmpl_dma_aggr;
4104 __le16 num_cmpl_dma_aggr_during_int; 4762 __le16 num_cmpl_dma_aggr_during_int;
4105 __le16 cmpl_aggr_dma_tmr; 4763 __le16 cmpl_aggr_dma_tmr;
@@ -4107,7 +4765,14 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
4107 __le16 int_lat_tmr_min; 4765 __le16 int_lat_tmr_min;
4108 __le16 int_lat_tmr_max; 4766 __le16 int_lat_tmr_max;
4109 __le16 num_cmpl_aggr_int; 4767 __le16 num_cmpl_aggr_int;
4110 u8 unused_0[6]; 4768 __le16 enables;
4769 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
4770 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
4771 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
4772 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
4773 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
4774 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
4775 u8 unused_0[4];
4111}; 4776};
4112 4777
4113/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 4778/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
@@ -4120,34 +4785,6 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
4120 u8 valid; 4785 u8 valid;
4121}; 4786};
4122 4787
4123/* hwrm_ring_reset_input (size:192b/24B) */
4124struct hwrm_ring_reset_input {
4125 __le16 req_type;
4126 __le16 cmpl_ring;
4127 __le16 seq_id;
4128 __le16 target_id;
4129 __le64 resp_addr;
4130 u8 ring_type;
4131 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
4132 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
4133 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
4134 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
4135 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL
4136 u8 unused_0;
4137 __le16 ring_id;
4138 u8 unused_1[4];
4139};
4140
4141/* hwrm_ring_reset_output (size:128b/16B) */
4142struct hwrm_ring_reset_output {
4143 __le16 error_code;
4144 __le16 req_type;
4145 __le16 seq_id;
4146 __le16 resp_len;
4147 u8 unused_0[7];
4148 u8 valid;
4149};
4150
4151/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 4788/* hwrm_ring_grp_alloc_input (size:192b/24B) */
4152struct hwrm_ring_grp_alloc_input { 4789struct hwrm_ring_grp_alloc_input {
4153 __le16 req_type; 4790 __le16 req_type;
@@ -5032,7 +5669,8 @@ struct hwrm_tunnel_dst_port_query_input {
5032 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5669 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5033 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5670 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5034 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5671 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5035 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 5672 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5673 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1
5036 u8 unused_0[7]; 5674 u8 unused_0[7];
5037}; 5675};
5038 5676
@@ -5059,7 +5697,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
5059 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5697 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5060 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5698 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5061 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5699 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5062 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 5700 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5701 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1
5063 u8 unused_0; 5702 u8 unused_0;
5064 __be16 tunnel_dst_port_val; 5703 __be16 tunnel_dst_port_val;
5065 u8 unused_1[4]; 5704 u8 unused_1[4];
@@ -5087,7 +5726,8 @@ struct hwrm_tunnel_dst_port_free_input {
5087 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5726 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5088 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5727 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5089 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5728 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5090 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 5729 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5730 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1
5091 u8 unused_0; 5731 u8 unused_0;
5092 __le16 tunnel_dst_port_id; 5732 __le16 tunnel_dst_port_id;
5093 u8 unused_1[4]; 5733 u8 unused_1[4];
@@ -5259,140 +5899,6 @@ struct hwrm_pcie_qstats_output {
5259 u8 valid; 5899 u8 valid;
5260}; 5900};
5261 5901
5262/* tx_port_stats (size:3264b/408B) */
5263struct tx_port_stats {
5264 __le64 tx_64b_frames;
5265 __le64 tx_65b_127b_frames;
5266 __le64 tx_128b_255b_frames;
5267 __le64 tx_256b_511b_frames;
5268 __le64 tx_512b_1023b_frames;
5269 __le64 tx_1024b_1518_frames;
5270 __le64 tx_good_vlan_frames;
5271 __le64 tx_1519b_2047_frames;
5272 __le64 tx_2048b_4095b_frames;
5273 __le64 tx_4096b_9216b_frames;
5274 __le64 tx_9217b_16383b_frames;
5275 __le64 tx_good_frames;
5276 __le64 tx_total_frames;
5277 __le64 tx_ucast_frames;
5278 __le64 tx_mcast_frames;
5279 __le64 tx_bcast_frames;
5280 __le64 tx_pause_frames;
5281 __le64 tx_pfc_frames;
5282 __le64 tx_jabber_frames;
5283 __le64 tx_fcs_err_frames;
5284 __le64 tx_control_frames;
5285 __le64 tx_oversz_frames;
5286 __le64 tx_single_dfrl_frames;
5287 __le64 tx_multi_dfrl_frames;
5288 __le64 tx_single_coll_frames;
5289 __le64 tx_multi_coll_frames;
5290 __le64 tx_late_coll_frames;
5291 __le64 tx_excessive_coll_frames;
5292 __le64 tx_frag_frames;
5293 __le64 tx_err;
5294 __le64 tx_tagged_frames;
5295 __le64 tx_dbl_tagged_frames;
5296 __le64 tx_runt_frames;
5297 __le64 tx_fifo_underruns;
5298 __le64 tx_pfc_ena_frames_pri0;
5299 __le64 tx_pfc_ena_frames_pri1;
5300 __le64 tx_pfc_ena_frames_pri2;
5301 __le64 tx_pfc_ena_frames_pri3;
5302 __le64 tx_pfc_ena_frames_pri4;
5303 __le64 tx_pfc_ena_frames_pri5;
5304 __le64 tx_pfc_ena_frames_pri6;
5305 __le64 tx_pfc_ena_frames_pri7;
5306 __le64 tx_eee_lpi_events;
5307 __le64 tx_eee_lpi_duration;
5308 __le64 tx_llfc_logical_msgs;
5309 __le64 tx_hcfc_msgs;
5310 __le64 tx_total_collisions;
5311 __le64 tx_bytes;
5312 __le64 tx_xthol_frames;
5313 __le64 tx_stat_discard;
5314 __le64 tx_stat_error;
5315};
5316
5317/* rx_port_stats (size:4224b/528B) */
5318struct rx_port_stats {
5319 __le64 rx_64b_frames;
5320 __le64 rx_65b_127b_frames;
5321 __le64 rx_128b_255b_frames;
5322 __le64 rx_256b_511b_frames;
5323 __le64 rx_512b_1023b_frames;
5324 __le64 rx_1024b_1518_frames;
5325 __le64 rx_good_vlan_frames;
5326 __le64 rx_1519b_2047b_frames;
5327 __le64 rx_2048b_4095b_frames;
5328 __le64 rx_4096b_9216b_frames;
5329 __le64 rx_9217b_16383b_frames;
5330 __le64 rx_total_frames;
5331 __le64 rx_ucast_frames;
5332 __le64 rx_mcast_frames;
5333 __le64 rx_bcast_frames;
5334 __le64 rx_fcs_err_frames;
5335 __le64 rx_ctrl_frames;
5336 __le64 rx_pause_frames;
5337 __le64 rx_pfc_frames;
5338 __le64 rx_unsupported_opcode_frames;
5339 __le64 rx_unsupported_da_pausepfc_frames;
5340 __le64 rx_wrong_sa_frames;
5341 __le64 rx_align_err_frames;
5342 __le64 rx_oor_len_frames;
5343 __le64 rx_code_err_frames;
5344 __le64 rx_false_carrier_frames;
5345 __le64 rx_ovrsz_frames;
5346 __le64 rx_jbr_frames;
5347 __le64 rx_mtu_err_frames;
5348 __le64 rx_match_crc_frames;
5349 __le64 rx_promiscuous_frames;
5350 __le64 rx_tagged_frames;
5351 __le64 rx_double_tagged_frames;
5352 __le64 rx_trunc_frames;
5353 __le64 rx_good_frames;
5354 __le64 rx_pfc_xon2xoff_frames_pri0;
5355 __le64 rx_pfc_xon2xoff_frames_pri1;
5356 __le64 rx_pfc_xon2xoff_frames_pri2;
5357 __le64 rx_pfc_xon2xoff_frames_pri3;
5358 __le64 rx_pfc_xon2xoff_frames_pri4;
5359 __le64 rx_pfc_xon2xoff_frames_pri5;
5360 __le64 rx_pfc_xon2xoff_frames_pri6;
5361 __le64 rx_pfc_xon2xoff_frames_pri7;
5362 __le64 rx_pfc_ena_frames_pri0;
5363 __le64 rx_pfc_ena_frames_pri1;
5364 __le64 rx_pfc_ena_frames_pri2;
5365 __le64 rx_pfc_ena_frames_pri3;
5366 __le64 rx_pfc_ena_frames_pri4;
5367 __le64 rx_pfc_ena_frames_pri5;
5368 __le64 rx_pfc_ena_frames_pri6;
5369 __le64 rx_pfc_ena_frames_pri7;
5370 __le64 rx_sch_crc_err_frames;
5371 __le64 rx_undrsz_frames;
5372 __le64 rx_frag_frames;
5373 __le64 rx_eee_lpi_events;
5374 __le64 rx_eee_lpi_duration;
5375 __le64 rx_llfc_physical_msgs;
5376 __le64 rx_llfc_logical_msgs;
5377 __le64 rx_llfc_msgs_with_crc_err;
5378 __le64 rx_hcfc_msgs;
5379 __le64 rx_hcfc_msgs_with_crc_err;
5380 __le64 rx_bytes;
5381 __le64 rx_runt_bytes;
5382 __le64 rx_runt_frames;
5383 __le64 rx_stat_discard;
5384 __le64 rx_stat_err;
5385};
5386
5387/* rx_port_stats_ext (size:320b/40B) */
5388struct rx_port_stats_ext {
5389 __le64 link_down_events;
5390 __le64 continuous_pause_events;
5391 __le64 resume_pause_events;
5392 __le64 continuous_roce_pause_events;
5393 __le64 resume_roce_pause_events;
5394};
5395
5396/* pcie_ctx_hw_stats (size:768b/96B) */ 5902/* pcie_ctx_hw_stats (size:768b/96B) */
5397struct pcie_ctx_hw_stats { 5903struct pcie_ctx_hw_stats {
5398 __le64 pcie_pl_signal_integrity; 5904 __le64 pcie_pl_signal_integrity;
@@ -5884,6 +6390,114 @@ struct hwrm_wol_reason_qcfg_output {
5884 u8 valid; 6390 u8 valid;
5885}; 6391};
5886 6392
6393/* coredump_segment_record (size:128b/16B) */
6394struct coredump_segment_record {
6395 __le16 component_id;
6396 __le16 segment_id;
6397 __le16 max_instances;
6398 u8 version_hi;
6399 u8 version_low;
6400 u8 seg_flags;
6401 u8 unused_0[7];
6402};
6403
6404/* hwrm_dbg_coredump_list_input (size:256b/32B) */
6405struct hwrm_dbg_coredump_list_input {
6406 __le16 req_type;
6407 __le16 cmpl_ring;
6408 __le16 seq_id;
6409 __le16 target_id;
6410 __le64 resp_addr;
6411 __le64 host_dest_addr;
6412 __le32 host_buf_len;
6413 __le16 seq_no;
6414 u8 unused_0[2];
6415};
6416
6417/* hwrm_dbg_coredump_list_output (size:128b/16B) */
6418struct hwrm_dbg_coredump_list_output {
6419 __le16 error_code;
6420 __le16 req_type;
6421 __le16 seq_id;
6422 __le16 resp_len;
6423 u8 flags;
6424 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
6425 u8 unused_0;
6426 __le16 total_segments;
6427 __le16 data_len;
6428 u8 unused_1;
6429 u8 valid;
6430};
6431
6432/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
6433struct hwrm_dbg_coredump_initiate_input {
6434 __le16 req_type;
6435 __le16 cmpl_ring;
6436 __le16 seq_id;
6437 __le16 target_id;
6438 __le64 resp_addr;
6439 __le16 component_id;
6440 __le16 segment_id;
6441 __le16 instance;
6442 __le16 unused_0;
6443 u8 seg_flags;
6444 u8 unused_1[7];
6445};
6446
6447/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
6448struct hwrm_dbg_coredump_initiate_output {
6449 __le16 error_code;
6450 __le16 req_type;
6451 __le16 seq_id;
6452 __le16 resp_len;
6453 u8 unused_0[7];
6454 u8 valid;
6455};
6456
6457/* coredump_data_hdr (size:128b/16B) */
6458struct coredump_data_hdr {
6459 __le32 address;
6460 __le32 flags_length;
6461 __le32 instance;
6462 __le32 next_offset;
6463};
6464
6465/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
6466struct hwrm_dbg_coredump_retrieve_input {
6467 __le16 req_type;
6468 __le16 cmpl_ring;
6469 __le16 seq_id;
6470 __le16 target_id;
6471 __le64 resp_addr;
6472 __le64 host_dest_addr;
6473 __le32 host_buf_len;
6474 __le32 unused_0;
6475 __le16 component_id;
6476 __le16 segment_id;
6477 __le16 instance;
6478 __le16 unused_1;
6479 u8 seg_flags;
6480 u8 unused_2;
6481 __le16 unused_3;
6482 __le32 unused_4;
6483 __le32 seq_no;
6484 __le32 unused_5;
6485};
6486
6487/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
6488struct hwrm_dbg_coredump_retrieve_output {
6489 __le16 error_code;
6490 __le16 req_type;
6491 __le16 seq_id;
6492 __le16 resp_len;
6493 u8 flags;
6494 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
6495 u8 unused_0;
6496 __le16 data_len;
6497 u8 unused_1[3];
6498 u8 valid;
6499};
6500
5887/* hwrm_nvm_read_input (size:320b/40B) */ 6501/* hwrm_nvm_read_input (size:320b/40B) */
5888struct hwrm_nvm_read_input { 6502struct hwrm_nvm_read_input {
5889 __le16 req_type; 6503 __le16 req_type;
@@ -6201,19 +6815,6 @@ struct hwrm_nvm_install_update_cmd_err {
6201 u8 unused_0[7]; 6815 u8 unused_0[7];
6202}; 6816};
6203 6817
6204struct hwrm_nvm_variable_input {
6205 __le16 req_type;
6206 __le16 cmpl_ring;
6207 __le16 seq_id;
6208 __le16 target_id;
6209 __le64 resp_addr;
6210 __le64 data_addr;
6211 __le16 data_len;
6212 __le16 option_num;
6213 __le16 dimensions;
6214 __le16 index_0;
6215};
6216
6217/* hwrm_nvm_get_variable_input (size:320b/40B) */ 6818/* hwrm_nvm_get_variable_input (size:320b/40B) */
6218struct hwrm_nvm_get_variable_input { 6819struct hwrm_nvm_get_variable_input {
6219 __le16 req_type; 6820 __le16 req_type;
@@ -6282,12 +6883,14 @@ struct hwrm_nvm_set_variable_input {
6282 __le16 index_2; 6883 __le16 index_2;
6283 __le16 index_3; 6884 __le16 index_3;
6284 u8 flags; 6885 u8 flags;
6285 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 6886 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
6286 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 6887 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
6287 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 6888 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
6288 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 6889 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
6289 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 6890 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
6290 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 6891 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
6892 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
6893 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
6291 u8 unused_0; 6894 u8 unused_0;
6292}; 6895};
6293 6896
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
index f560845c5a9d..6d583bcd2a81 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
@@ -447,7 +447,7 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs)
447 u16 vf_tx_rings, vf_rx_rings, vf_cp_rings; 447 u16 vf_tx_rings, vf_rx_rings, vf_cp_rings;
448 u16 vf_stat_ctx, vf_vnics, vf_ring_grps; 448 u16 vf_stat_ctx, vf_vnics, vf_ring_grps;
449 struct bnxt_pf_info *pf = &bp->pf; 449 struct bnxt_pf_info *pf = &bp->pf;
450 int i, rc = 0; 450 int i, rc = 0, min = 1;
451 451
452 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_RESOURCE_CFG, -1, -1); 452 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_RESOURCE_CFG, -1, -1);
453 453
@@ -464,14 +464,19 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs)
464 464
465 req.min_rsscos_ctx = cpu_to_le16(BNXT_VF_MIN_RSS_CTX); 465 req.min_rsscos_ctx = cpu_to_le16(BNXT_VF_MIN_RSS_CTX);
466 req.max_rsscos_ctx = cpu_to_le16(BNXT_VF_MAX_RSS_CTX); 466 req.max_rsscos_ctx = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
467 if (pf->vf_resv_strategy == BNXT_VF_RESV_STRATEGY_MINIMAL) { 467 if (pf->vf_resv_strategy == BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
468 req.min_cmpl_rings = cpu_to_le16(1); 468 min = 0;
469 req.min_tx_rings = cpu_to_le16(1); 469 req.min_rsscos_ctx = cpu_to_le16(min);
470 req.min_rx_rings = cpu_to_le16(1); 470 }
471 req.min_l2_ctxs = cpu_to_le16(BNXT_VF_MIN_L2_CTX); 471 if (pf->vf_resv_strategy == BNXT_VF_RESV_STRATEGY_MINIMAL ||
472 req.min_vnics = cpu_to_le16(1); 472 pf->vf_resv_strategy == BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
473 req.min_stat_ctx = cpu_to_le16(1); 473 req.min_cmpl_rings = cpu_to_le16(min);
474 req.min_hw_ring_grps = cpu_to_le16(1); 474 req.min_tx_rings = cpu_to_le16(min);
475 req.min_rx_rings = cpu_to_le16(min);
476 req.min_l2_ctxs = cpu_to_le16(min);
477 req.min_vnics = cpu_to_le16(min);
478 req.min_stat_ctx = cpu_to_le16(min);
479 req.min_hw_ring_grps = cpu_to_le16(min);
475 } else { 480 } else {
476 vf_cp_rings /= num_vfs; 481 vf_cp_rings /= num_vfs;
477 vf_tx_rings /= num_vfs; 482 vf_tx_rings /= num_vfs;
@@ -618,7 +623,7 @@ static int bnxt_hwrm_func_cfg(struct bnxt *bp, int num_vfs)
618 623
619static int bnxt_func_cfg(struct bnxt *bp, int num_vfs) 624static int bnxt_func_cfg(struct bnxt *bp, int num_vfs)
620{ 625{
621 if (bp->flags & BNXT_FLAG_NEW_RM) 626 if (BNXT_NEW_RM(bp))
622 return bnxt_hwrm_func_vf_resc_cfg(bp, num_vfs); 627 return bnxt_hwrm_func_vf_resc_cfg(bp, num_vfs);
623 else 628 else
624 return bnxt_hwrm_func_cfg(bp, num_vfs); 629 return bnxt_hwrm_func_cfg(bp, num_vfs);
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
index 840f6e505f73..c37b2842f972 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
@@ -141,7 +141,7 @@ static int bnxt_req_msix_vecs(struct bnxt_en_dev *edev, int ulp_id,
141 if (avail_msix > num_msix) 141 if (avail_msix > num_msix)
142 avail_msix = num_msix; 142 avail_msix = num_msix;
143 143
144 if (bp->flags & BNXT_FLAG_NEW_RM) { 144 if (BNXT_NEW_RM(bp)) {
145 idx = bp->cp_nr_rings; 145 idx = bp->cp_nr_rings;
146 } else { 146 } else {
147 max_idx = min_t(int, bp->total_irqs, max_cp_rings); 147 max_idx = min_t(int, bp->total_irqs, max_cp_rings);
@@ -162,7 +162,7 @@ static int bnxt_req_msix_vecs(struct bnxt_en_dev *edev, int ulp_id,
162 return -EAGAIN; 162 return -EAGAIN;
163 } 163 }
164 164
165 if (bp->flags & BNXT_FLAG_NEW_RM) { 165 if (BNXT_NEW_RM(bp)) {
166 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 166 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
167 167
168 avail_msix = hw_resc->resv_cp_rings - bp->cp_nr_rings; 168 avail_msix = hw_resc->resv_cp_rings - bp->cp_nr_rings;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 19:51:07 -0400