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authorThierry Reding <treding@nvidia.com>2016-11-21 04:25:36 -0500
committerThierry Reding <treding@nvidia.com>2017-01-25 03:23:56 -0500
commitc58f5f88483974adebc49996b3cbfd89e944222f (patch)
tree996959752bec7a410fc4fb67fdde0f77596bfd27
parent5edcebb96b2f6815f94d7030408cbe08c0dd4b80 (diff)
arm64: tegra: Use symbolic clock identifiers
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi41
1 files changed, 21 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index e3ef2f1b97f4..910315f579c4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,3 +1,4 @@
1#include <dt-bindings/clock/tegra186-clock.h>
1#include <dt-bindings/gpio/tegra186-gpio.h> 2#include <dt-bindings/gpio/tegra186-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include <dt-bindings/mailbox/tegra186-hsp.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h>
@@ -30,7 +31,7 @@
30 reg = <0x0 0x03100000 0x0 0x40>; 31 reg = <0x0 0x03100000 0x0 0x40>;
31 reg-shift = <2>; 32 reg-shift = <2>;
32 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 33 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&bpmp 55>; 34 clocks = <&bpmp TEGRA186_CLK_UARTA>;
34 clock-names = "serial"; 35 clock-names = "serial";
35 resets = <&bpmp 47>; 36 resets = <&bpmp 47>;
36 reset-names = "serial"; 37 reset-names = "serial";
@@ -42,7 +43,7 @@
42 reg = <0x0 0x03110000 0x0 0x40>; 43 reg = <0x0 0x03110000 0x0 0x40>;
43 reg-shift = <2>; 44 reg-shift = <2>;
44 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 45 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&bpmp 56>; 46 clocks = <&bpmp TEGRA186_CLK_UARTB>;
46 clock-names = "serial"; 47 clock-names = "serial";
47 resets = <&bpmp 48>; 48 resets = <&bpmp 48>;
48 reset-names = "serial"; 49 reset-names = "serial";
@@ -54,7 +55,7 @@
54 reg = <0x0 0x03130000 0x0 0x40>; 55 reg = <0x0 0x03130000 0x0 0x40>;
55 reg-shift = <2>; 56 reg-shift = <2>;
56 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 57 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&bpmp 77>; 58 clocks = <&bpmp TEGRA186_CLK_UARTD>;
58 clock-names = "serial"; 59 clock-names = "serial";
59 resets = <&bpmp 50>; 60 resets = <&bpmp 50>;
60 reset-names = "serial"; 61 reset-names = "serial";
@@ -66,7 +67,7 @@
66 reg = <0x0 0x03140000 0x0 0x40>; 67 reg = <0x0 0x03140000 0x0 0x40>;
67 reg-shift = <2>; 68 reg-shift = <2>;
68 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 69 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&bpmp 194>; 70 clocks = <&bpmp TEGRA186_CLK_UARTE>;
70 clock-names = "serial"; 71 clock-names = "serial";
71 resets = <&bpmp 132>; 72 resets = <&bpmp 132>;
72 reset-names = "serial"; 73 reset-names = "serial";
@@ -78,7 +79,7 @@
78 reg = <0x0 0x03150000 0x0 0x40>; 79 reg = <0x0 0x03150000 0x0 0x40>;
79 reg-shift = <2>; 80 reg-shift = <2>;
80 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 81 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&bpmp 195>; 82 clocks = <&bpmp TEGRA186_CLK_UARTF>;
82 clock-names = "serial"; 83 clock-names = "serial";
83 resets = <&bpmp 111>; 84 resets = <&bpmp 111>;
84 reset-names = "serial"; 85 reset-names = "serial";
@@ -91,7 +92,7 @@
91 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 92 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
92 #address-cells = <1>; 93 #address-cells = <1>;
93 #size-cells = <0>; 94 #size-cells = <0>;
94 clocks = <&bpmp 47>; 95 clocks = <&bpmp TEGRA186_CLK_I2C1>;
95 clock-names = "div-clk"; 96 clock-names = "div-clk";
96 resets = <&bpmp 19>; 97 resets = <&bpmp 19>;
97 reset-names = "i2c"; 98 reset-names = "i2c";
@@ -104,7 +105,7 @@
104 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 105 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
105 #address-cells = <1>; 106 #address-cells = <1>;
106 #size-cells = <0>; 107 #size-cells = <0>;
107 clocks = <&bpmp 75>; 108 clocks = <&bpmp TEGRA186_CLK_I2C3>;
108 clock-names = "div-clk"; 109 clock-names = "div-clk";
109 resets = <&bpmp 21>; 110 resets = <&bpmp 21>;
110 reset-names = "i2c"; 111 reset-names = "i2c";
@@ -118,7 +119,7 @@
118 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
119 #address-cells = <1>; 120 #address-cells = <1>;
120 #size-cells = <0>; 121 #size-cells = <0>;
121 clocks = <&bpmp 86>; 122 clocks = <&bpmp TEGRA186_CLK_I2C4>;
122 clock-names = "div-clk"; 123 clock-names = "div-clk";
123 resets = <&bpmp 22>; 124 resets = <&bpmp 22>;
124 reset-names = "i2c"; 125 reset-names = "i2c";
@@ -132,7 +133,7 @@
132 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 133 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
133 #address-cells = <1>; 134 #address-cells = <1>;
134 #size-cells = <0>; 135 #size-cells = <0>;
135 clocks = <&bpmp 48>; 136 clocks = <&bpmp TEGRA186_CLK_I2C5>;
136 clock-names = "div-clk"; 137 clock-names = "div-clk";
137 resets = <&bpmp 23>; 138 resets = <&bpmp 23>;
138 reset-names = "i2c"; 139 reset-names = "i2c";
@@ -146,7 +147,7 @@
146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 147 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147 #address-cells = <1>; 148 #address-cells = <1>;
148 #size-cells = <0>; 149 #size-cells = <0>;
149 clocks = <&bpmp 125>; 150 clocks = <&bpmp TEGRA186_CLK_I2C6>;
150 clock-names = "div-clk"; 151 clock-names = "div-clk";
151 resets = <&bpmp 24>; 152 resets = <&bpmp 24>;
152 reset-names = "i2c"; 153 reset-names = "i2c";
@@ -159,7 +160,7 @@
159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 160 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
160 #address-cells = <1>; 161 #address-cells = <1>;
161 #size-cells = <0>; 162 #size-cells = <0>;
162 clocks = <&bpmp 182>; 163 clocks = <&bpmp TEGRA186_CLK_I2C7>;
163 clock-names = "div-clk"; 164 clock-names = "div-clk";
164 resets = <&bpmp 81>; 165 resets = <&bpmp 81>;
165 reset-names = "i2c"; 166 reset-names = "i2c";
@@ -172,7 +173,7 @@
172 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>; 174 #address-cells = <1>;
174 #size-cells = <0>; 175 #size-cells = <0>;
175 clocks = <&bpmp 183>; 176 clocks = <&bpmp TEGRA186_CLK_I2C9>;
176 clock-names = "div-clk"; 177 clock-names = "div-clk";
177 resets = <&bpmp 83>; 178 resets = <&bpmp 83>;
178 reset-names = "i2c"; 179 reset-names = "i2c";
@@ -183,7 +184,7 @@
183 compatible = "nvidia,tegra186-sdhci"; 184 compatible = "nvidia,tegra186-sdhci";
184 reg = <0x0 0x03400000 0x0 0x10000>; 185 reg = <0x0 0x03400000 0x0 0x10000>;
185 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&bpmp 52>; 187 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
187 clock-names = "sdhci"; 188 clock-names = "sdhci";
188 resets = <&bpmp 33>; 189 resets = <&bpmp 33>;
189 reset-names = "sdhci"; 190 reset-names = "sdhci";
@@ -194,7 +195,7 @@
194 compatible = "nvidia,tegra186-sdhci"; 195 compatible = "nvidia,tegra186-sdhci";
195 reg = <0x0 0x03420000 0x0 0x10000>; 196 reg = <0x0 0x03420000 0x0 0x10000>;
196 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 197 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&bpmp 53>; 198 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
198 clock-names = "sdhci"; 199 clock-names = "sdhci";
199 resets = <&bpmp 34>; 200 resets = <&bpmp 34>;
200 reset-names = "sdhci"; 201 reset-names = "sdhci";
@@ -205,7 +206,7 @@
205 compatible = "nvidia,tegra186-sdhci"; 206 compatible = "nvidia,tegra186-sdhci";
206 reg = <0x0 0x03440000 0x0 0x10000>; 207 reg = <0x0 0x03440000 0x0 0x10000>;
207 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&bpmp 76>; 209 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
209 clock-names = "sdhci"; 210 clock-names = "sdhci";
210 resets = <&bpmp 35>; 211 resets = <&bpmp 35>;
211 reset-names = "sdhci"; 212 reset-names = "sdhci";
@@ -216,7 +217,7 @@
216 compatible = "nvidia,tegra186-sdhci"; 217 compatible = "nvidia,tegra186-sdhci";
217 reg = <0x0 0x03460000 0x0 0x10000>; 218 reg = <0x0 0x03460000 0x0 0x10000>;
218 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&bpmp 54>; 220 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
220 clock-names = "sdhci"; 221 clock-names = "sdhci";
221 resets = <&bpmp 36>; 222 resets = <&bpmp 36>;
222 reset-names = "sdhci"; 223 reset-names = "sdhci";
@@ -249,7 +250,7 @@
249 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
250 #address-cells = <1>; 251 #address-cells = <1>;
251 #size-cells = <0>; 252 #size-cells = <0>;
252 clocks = <&bpmp 218>; 253 clocks = <&bpmp TEGRA186_CLK_I2C2>;
253 clock-names = "div-clk"; 254 clock-names = "div-clk";
254 resets = <&bpmp 20>; 255 resets = <&bpmp 20>;
255 reset-names = "i2c"; 256 reset-names = "i2c";
@@ -262,7 +263,7 @@
262 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
263 #address-cells = <1>; 264 #address-cells = <1>;
264 #size-cells = <0>; 265 #size-cells = <0>;
265 clocks = <&bpmp 219>; 266 clocks = <&bpmp TEGRA186_CLK_I2C8>;
266 clock-names = "div-clk"; 267 clock-names = "div-clk";
267 resets = <&bpmp 82>; 268 resets = <&bpmp 82>;
268 reset-names = "i2c"; 269 reset-names = "i2c";
@@ -274,7 +275,7 @@
274 reg = <0x0 0x0c280000 0x0 0x40>; 275 reg = <0x0 0x0c280000 0x0 0x40>;
275 reg-shift = <2>; 276 reg-shift = <2>;
276 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 277 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&bpmp 215>; 278 clocks = <&bpmp TEGRA186_CLK_UARTC>;
278 clock-names = "serial"; 279 clock-names = "serial";
279 resets = <&bpmp 49>; 280 resets = <&bpmp 49>;
280 reset-names = "serial"; 281 reset-names = "serial";
@@ -286,7 +287,7 @@
286 reg = <0x0 0x0c290000 0x0 0x40>; 287 reg = <0x0 0x0c290000 0x0 0x40>;
287 reg-shift = <2>; 288 reg-shift = <2>;
288 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&bpmp 216>; 290 clocks = <&bpmp TEGRA186_CLK_UARTG>;
290 clock-names = "serial"; 291 clock-names = "serial";
291 resets = <&bpmp 112>; 292 resets = <&bpmp 112>;
292 reset-names = "serial"; 293 reset-names = "serial";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 07:27:59 -0400