diff options
author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2016-08-12 17:27:55 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2016-08-15 10:09:09 -0400 |
commit | c49aed77d55b42a1ec5e1d01c2ab788abc82717c (patch) | |
tree | 72e7332ffca6563a86e8e9a7ac419006ebd23ab0 | |
parent | 29b4817d4018df78086157ea3a55c1d9424a7cfc (diff) |
ASoC: rt5640: add internal clock source support
Adding missing definitions and flags to select internal
clock source as system clock, needed for jack detection.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/codecs/rt5640.c | 3 | ||||
-rw-r--r-- | sound/soc/codecs/rt5640.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c index 09e8988bbb2d..b0f6f0712ba1 100644 --- a/sound/soc/codecs/rt5640.c +++ b/sound/soc/codecs/rt5640.c | |||
@@ -1870,6 +1870,9 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai, | |||
1870 | case RT5640_SCLK_S_PLL1: | 1870 | case RT5640_SCLK_S_PLL1: |
1871 | reg_val |= RT5640_SCLK_SRC_PLL1; | 1871 | reg_val |= RT5640_SCLK_SRC_PLL1; |
1872 | break; | 1872 | break; |
1873 | case RT5640_SCLK_S_RCCLK: | ||
1874 | reg_val |= RT5640_SCLK_SRC_RCCLK; | ||
1875 | break; | ||
1873 | default: | 1876 | default: |
1874 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); | 1877 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); |
1875 | return -EINVAL; | 1878 | return -EINVAL; |
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h index 58b664b06c16..90c88711c72a 100644 --- a/sound/soc/codecs/rt5640.h +++ b/sound/soc/codecs/rt5640.h | |||
@@ -984,6 +984,7 @@ | |||
984 | #define RT5640_SCLK_SRC_SFT 14 | 984 | #define RT5640_SCLK_SRC_SFT 14 |
985 | #define RT5640_SCLK_SRC_MCLK (0x0 << 14) | 985 | #define RT5640_SCLK_SRC_MCLK (0x0 << 14) |
986 | #define RT5640_SCLK_SRC_PLL1 (0x1 << 14) | 986 | #define RT5640_SCLK_SRC_PLL1 (0x1 << 14) |
987 | #define RT5640_SCLK_SRC_RCCLK (0x2 << 14) | ||
987 | #define RT5640_PLL1_SRC_MASK (0x3 << 12) | 988 | #define RT5640_PLL1_SRC_MASK (0x3 << 12) |
988 | #define RT5640_PLL1_SRC_SFT 12 | 989 | #define RT5640_PLL1_SRC_SFT 12 |
989 | #define RT5640_PLL1_SRC_MCLK (0x0 << 12) | 990 | #define RT5640_PLL1_SRC_MCLK (0x0 << 12) |