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authorHelen Koike <helen.koike@collabora.com>2019-06-03 10:22:15 -0400
committerHeiko Stuebner <heiko@sntech.de>2019-06-04 09:35:19 -0400
commitc432a29d3fc9ee928caeca2f5cf68b3aebfa6817 (patch)
treeedc41abf7a7fa76efbe47b67d3dc9caaeeb41249
parent0ee198ab08fe1b7cca93a81ad658954534963cb0 (diff)
arm64: dts: rockchip: fix isp iommu clocks and power domain
isp iommu requires wrapper variants of the clocks. noc variants are always on and using the wrapper variants will activate {A,H}CLK_ISP{0,1} due to the hierarchy. Tested using the pending isp patch set (which is not upstream yet). Without this patch, streaming from the isp stalls. Also add the respective power domain and remove the "disabled" status. Refer: RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition Signed-off-by: Helen Koike <helen.koike@collabora.com> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 196ac9b78076..89594a7276f4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1706,11 +1706,11 @@
1706 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1706 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1707 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1707 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1708 interrupt-names = "isp0_mmu"; 1708 interrupt-names = "isp0_mmu";
1709 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; 1709 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1710 clock-names = "aclk", "iface"; 1710 clock-names = "aclk", "iface";
1711 #iommu-cells = <0>; 1711 #iommu-cells = <0>;
1712 power-domains = <&power RK3399_PD_ISP0>;
1712 rockchip,disable-mmu-reset; 1713 rockchip,disable-mmu-reset;
1713 status = "disabled";
1714 }; 1714 };
1715 1715
1716 isp1_mmu: iommu@ff924000 { 1716 isp1_mmu: iommu@ff924000 {
@@ -1718,11 +1718,11 @@
1718 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1718 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1719 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1719 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1720 interrupt-names = "isp1_mmu"; 1720 interrupt-names = "isp1_mmu";
1721 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; 1721 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1722 clock-names = "aclk", "iface"; 1722 clock-names = "aclk", "iface";
1723 #iommu-cells = <0>; 1723 #iommu-cells = <0>;
1724 power-domains = <&power RK3399_PD_ISP1>;
1724 rockchip,disable-mmu-reset; 1725 rockchip,disable-mmu-reset;
1725 status = "disabled";
1726 }; 1726 };
1727 1727
1728 hdmi_sound: hdmi-sound { 1728 hdmi_sound: hdmi-sound {