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authorLinus Torvalds <torvalds@linux-foundation.org>2017-11-24 02:04:56 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-11-24 02:04:56 -0500
commitc353bfc6ebc1073f2f0af72a15f8f18db7193d2e (patch)
tree5f9335398fc199756de6d73a9464407a9d68ead3
parent1d3bc6363a7d14393e7e66f092645e2229b39954 (diff)
parent98ecf1a308977505381b5c360b039a84cf67513c (diff)
Merge tag 'drm-for-v4.15-part2' of git://people.freedesktop.org/~airlied/linux
Pull more drm updates from Dave Airlie: "Fixes/cleanups for rc1, non-desktop flags for VR - remove the MSM dt-bindings file Rob managed to push in the previous pull. - add a property/edid quirk to denote HMD devices, I had these hanging around for a few weeks and Keith had done some work on them, they are fairly self contained and small, and only affect people using HTC Vive VR headsets so far. - amdgpu, tegra, tilcdc, fsl fixes - some imx-drm cleanups I missed, these seemed pretty small, and no reason to hold off. I have one TTM regression fix (fixes bochs-vga in qemu) sitting locally awaiting review I'll probably send that in a separate pull request tomorrow" * tag 'drm-for-v4.15-part2' of git://people.freedesktop.org/~airlied/linux: (33 commits) dt-bindings: remove file that was added accidentally drm/edid: quirk HTC vive headset as non-desktop. [v2] drm/fb: add support for not enabling fbcon on non-desktop displays [v2] drm: add connector info/property for non-desktop displays [v2] drm/amdgpu: fix rmmod KCQ disable failed error drm/amdgpu: fix kernel hang when starting VNC server drm/amdgpu: don't skip attributes when powerplay is enabled drm/amd/pp: fix typecast error in powerplay. drm/tilcdc: Remove obsolete "ti,tilcdc,slave" dts binding support drm/tegra: sor: Reimplement pad clock Revert "drm/radeon: dont switch vt on suspend" drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence drm/amd/powerplay: fix unfreeze level smc message for smu7 drm/amdgpu:fix memleak drm/amdgpu:fix memleak in takedown drm/amd/pp: fix dpm randomly failed on Vega10 drm/amdgpu: set f_mapping on exported DMA-bufs drm/amdgpu: Properly allocate VM invalidate eng v2 drm/fsl-dcu: enable IRQ before drm_atomic_helper_resume() drm/fsl-dcu: avoid disabling pixel clock twice on suspend ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c27
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c15
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c29
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h1
-rw-r--r--drivers/gpu/drm/drm_connector.c17
-rw-r--r--drivers/gpu/drm/drm_edid.c11
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c6
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c3
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c5
-rw-r--r--drivers/gpu/drm/imx/ipuv3-crtc.c2
-rw-r--r--drivers/gpu/drm/imx/parallel-display.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c1
-rw-r--r--drivers/gpu/drm/tegra/sor.c157
-rw-r--r--drivers/gpu/drm/tilcdc/Kconfig11
-rw-r--r--drivers/gpu/drm/tilcdc/Makefile3
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c264
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts72
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h25
-rw-r--r--drivers/gpu/ipu-v3/ipu-dc.c3
-rw-r--r--include/drm/drm_connector.h5
-rw-r--r--include/drm/drm_mode_config.h7
-rw-r--r--include/dt-bindings/msm/msm-bus-ids.h887
39 files changed, 281 insertions, 1399 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index f79854783c2c..5bf77f6dd19d 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -129,7 +129,7 @@ Optional properties:
129 129
130example: 130example:
131 131
132display@di0 { 132disp0 {
133 compatible = "fsl,imx-parallel-display"; 133 compatible = "fsl,imx-parallel-display";
134 edid = [edid-data]; 134 edid = [edid-data];
135 interface-pix-fmt = "rgb24"; 135 interface-pix-fmt = "rgb24";
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index c21adf60a7f2..057e1ecd83ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
59 return false; 59 return false;
60 } 60 }
61 61
62 tmp = bios[0x18] | (bios[0x19] << 8);
63 if (bios[tmp + 0x14] != 0x0) {
64 DRM_INFO("Not an x86 BIOS ROM\n");
65 return false;
66 }
67
68 bios_header_start = bios[0x48] | (bios[0x49] << 8); 62 bios_header_start = bios[0x48] | (bios[0x49] << 8);
69 if (!bios_header_start) { 63 if (!bios_header_start) {
70 DRM_INFO("Can't locate bios header\n"); 64 DRM_INFO("Can't locate bios header\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6c78623e1386..a57cec737c18 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1495,8 +1495,11 @@ out:
1495 memset(wait, 0, sizeof(*wait)); 1495 memset(wait, 0, sizeof(*wait));
1496 wait->out.status = (r > 0); 1496 wait->out.status = (r > 0);
1497 wait->out.first_signaled = first; 1497 wait->out.first_signaled = first;
1498 /* set return value 0 to indicate success */ 1498
1499 r = array[first]->error; 1499 if (first < fence_count && array[first])
1500 r = array[first]->error;
1501 else
1502 r = 0;
1500 1503
1501err_free_fence_array: 1504err_free_fence_array:
1502 for (i = 0; i < fence_count; i++) 1505 for (i = 0; i < fence_count; i++)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2d792cdc094c..2c574374d9b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1837,6 +1837,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1837 adev->ip_blocks[i].status.hw = false; 1837 adev->ip_blocks[i].status.hw = false;
1838 } 1838 }
1839 1839
1840 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
1841 amdgpu_ucode_fini_bo(adev);
1842
1840 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1843 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1841 if (!adev->ip_blocks[i].status.sw) 1844 if (!adev->ip_blocks[i].status.sw)
1842 continue; 1845 continue;
@@ -3261,9 +3264,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3261 pm_pg_lock = (*pos >> 23) & 1; 3264 pm_pg_lock = (*pos >> 23) & 1;
3262 3265
3263 if (*pos & (1ULL << 62)) { 3266 if (*pos & (1ULL << 62)) {
3264 se_bank = (*pos >> 24) & 0x3FF; 3267 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3265 sh_bank = (*pos >> 34) & 0x3FF; 3268 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3266 instance_bank = (*pos >> 44) & 0x3FF; 3269 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3267 3270
3268 if (se_bank == 0x3FF) 3271 if (se_bank == 0x3FF)
3269 se_bank = 0xFFFFFFFF; 3272 se_bank = 0xFFFFFFFF;
@@ -3337,9 +3340,9 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3337 pm_pg_lock = (*pos >> 23) & 1; 3340 pm_pg_lock = (*pos >> 23) & 1;
3338 3341
3339 if (*pos & (1ULL << 62)) { 3342 if (*pos & (1ULL << 62)) {
3340 se_bank = (*pos >> 24) & 0x3FF; 3343 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3341 sh_bank = (*pos >> 34) & 0x3FF; 3344 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3342 instance_bank = (*pos >> 44) & 0x3FF; 3345 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3343 3346
3344 if (se_bank == 0x3FF) 3347 if (se_bank == 0x3FF)
3345 se_bank = 0xFFFFFFFF; 3348 se_bank = 0xFFFFFFFF;
@@ -3687,12 +3690,12 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3687 return -EINVAL; 3690 return -EINVAL;
3688 3691
3689 /* decode offset */ 3692 /* decode offset */
3690 offset = (*pos & 0x7F); 3693 offset = (*pos & GENMASK_ULL(6, 0));
3691 se = ((*pos >> 7) & 0xFF); 3694 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
3692 sh = ((*pos >> 15) & 0xFF); 3695 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
3693 cu = ((*pos >> 23) & 0xFF); 3696 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
3694 wave = ((*pos >> 31) & 0xFF); 3697 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
3695 simd = ((*pos >> 37) & 0xFF); 3698 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3696 3699
3697 /* switch to the specific se/sh/cu */ 3700 /* switch to the specific se/sh/cu */
3698 mutex_lock(&adev->grbm_idx_mutex); 3701 mutex_lock(&adev->grbm_idx_mutex);
@@ -3737,14 +3740,14 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3737 return -EINVAL; 3740 return -EINVAL;
3738 3741
3739 /* decode offset */ 3742 /* decode offset */
3740 offset = (*pos & 0xFFF); /* in dwords */ 3743 offset = *pos & GENMASK_ULL(11, 0);
3741 se = ((*pos >> 12) & 0xFF); 3744 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3742 sh = ((*pos >> 20) & 0xFF); 3745 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3743 cu = ((*pos >> 28) & 0xFF); 3746 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3744 wave = ((*pos >> 36) & 0xFF); 3747 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3745 simd = ((*pos >> 44) & 0xFF); 3748 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3746 thread = ((*pos >> 52) & 0xFF); 3749 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3747 bank = ((*pos >> 60) & 1); 3750 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3748 3751
3749 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); 3752 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3750 if (!data) 3753 if (!data)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a418df1b9422..e87eedcc0da9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -63,6 +63,11 @@ retry:
63 flags, NULL, resv, 0, &bo); 63 flags, NULL, resv, 0, &bo);
64 if (r) { 64 if (r) {
65 if (r != -ERESTARTSYS) { 65 if (r != -ERESTARTSYS) {
66 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
67 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
68 goto retry;
69 }
70
66 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 71 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
67 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 72 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
68 goto retry; 73 goto retry;
@@ -323,7 +328,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
323 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 328 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
324 bo->tbo.ttm->pages); 329 bo->tbo.ttm->pages);
325 if (r) 330 if (r)
326 goto unlock_mmap_sem; 331 goto release_object;
327 332
328 r = amdgpu_bo_reserve(bo, true); 333 r = amdgpu_bo_reserve(bo, true);
329 if (r) 334 if (r)
@@ -348,9 +353,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
348free_pages: 353free_pages:
349 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 354 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
350 355
351unlock_mmap_sem:
352 up_read(&current->mm->mmap_sem);
353
354release_object: 356release_object:
355 drm_gem_object_put_unlocked(gobj); 357 drm_gem_object_put_unlocked(gobj);
356 358
@@ -556,9 +558,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
556 558
557 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 559 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
558 dev_err(&dev->pdev->dev, 560 dev_err(&dev->pdev->dev,
559 "va_address 0x%lX is in reserved area 0x%X\n", 561 "va_address 0x%LX is in reserved area 0x%LX\n",
560 (unsigned long)args->va_address, 562 args->va_address, AMDGPU_VA_RESERVED_SIZE);
561 AMDGPU_VA_RESERVED_SIZE);
562 return -EINVAL; 563 return -EINVAL;
563 } 564 }
564 565
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 33535d347734..00e0ce10862f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -71,12 +71,6 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
71{ 71{
72 struct amdgpu_gtt_mgr *mgr = man->priv; 72 struct amdgpu_gtt_mgr *mgr = man->priv;
73 73
74 spin_lock(&mgr->lock);
75 if (!drm_mm_clean(&mgr->mm)) {
76 spin_unlock(&mgr->lock);
77 return -EBUSY;
78 }
79
80 drm_mm_takedown(&mgr->mm); 74 drm_mm_takedown(&mgr->mm);
81 spin_unlock(&mgr->lock); 75 spin_unlock(&mgr->lock);
82 kfree(mgr); 76 kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d6df5728df7f..6c570d4e4516 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -946,6 +946,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
946 struct amdgpu_device *adev = dev_get_drvdata(dev); 946 struct amdgpu_device *adev = dev_get_drvdata(dev);
947 umode_t effective_mode = attr->mode; 947 umode_t effective_mode = attr->mode;
948 948
949 /* no skipping for powerplay */
950 if (adev->powerplay.cgs_device)
951 return effective_mode;
952
949 /* Skip limit attributes if DPM is not enabled */ 953 /* Skip limit attributes if DPM is not enabled */
950 if (!adev->pm.dpm_enabled && 954 if (!adev->pm.dpm_enabled &&
951 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 955 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5f5aa5fddc16..033fba2def6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle)
164 ret = adev->powerplay.ip_funcs->hw_fini( 164 ret = adev->powerplay.ip_funcs->hw_fini(
165 adev->powerplay.pp_handle); 165 adev->powerplay.pp_handle);
166 166
167 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
168 amdgpu_ucode_fini_bo(adev);
169
170 return ret; 167 return ret;
171} 168}
172 169
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 90af8e82b16a..ae9c106979d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
169 int flags) 169 int flags)
170{ 170{
171 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 171 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
172 struct dma_buf *buf;
172 173
173 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || 174 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
174 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 175 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
175 return ERR_PTR(-EPERM); 176 return ERR_PTR(-EPERM);
176 177
177 return drm_gem_prime_export(dev, gobj, flags); 178 buf = drm_gem_prime_export(dev, gobj, flags);
179 if (!IS_ERR(buf))
180 buf->file->f_mapping = dev->anon_inode->i_mapping;
181 return buf;
178} 182}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 447d446b5015..7714f4a6c8b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -442,8 +442,6 @@ static int psp_hw_fini(void *handle)
442 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 442 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
443 return 0; 443 return 0;
444 444
445 amdgpu_ucode_fini_bo(adev);
446
447 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 445 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
448 446
449 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 447 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index aa914256b4bc..bae77353447b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry;
94#define AMDGPU_MMHUB 1 94#define AMDGPU_MMHUB 1
95 95
96/* hardcode that limit for now */ 96/* hardcode that limit for now */
97#define AMDGPU_VA_RESERVED_SIZE (8 << 20) 97#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
98
98/* max vmids dedicated for process */ 99/* max vmids dedicated for process */
99#define AMDGPU_VM_MAX_RESERVED_VMID 1 100#define AMDGPU_VM_MAX_RESERVED_VMID 1
100 101
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 26e900627971..4acca92f6a52 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man)
68 struct amdgpu_vram_mgr *mgr = man->priv; 68 struct amdgpu_vram_mgr *mgr = man->priv;
69 69
70 spin_lock(&mgr->lock); 70 spin_lock(&mgr->lock);
71 if (!drm_mm_clean(&mgr->mm)) {
72 spin_unlock(&mgr->lock);
73 return -EBUSY;
74 }
75
76 drm_mm_takedown(&mgr->mm); 71 drm_mm_takedown(&mgr->mm);
77 spin_unlock(&mgr->lock); 72 spin_unlock(&mgr->lock);
78 kfree(mgr); 73 kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 00868764a0dd..5c8a7a48a4ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4670,6 +4670,14 @@ static int gfx_v7_0_sw_fini(void *handle)
4670 gfx_v7_0_cp_compute_fini(adev); 4670 gfx_v7_0_cp_compute_fini(adev);
4671 gfx_v7_0_rlc_fini(adev); 4671 gfx_v7_0_rlc_fini(adev);
4672 gfx_v7_0_mec_fini(adev); 4672 gfx_v7_0_mec_fini(adev);
4673 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4674 &adev->gfx.rlc.clear_state_gpu_addr,
4675 (void **)&adev->gfx.rlc.cs_ptr);
4676 if (adev->gfx.rlc.cp_table_size) {
4677 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4678 &adev->gfx.rlc.cp_table_gpu_addr,
4679 (void **)&adev->gfx.rlc.cp_table_ptr);
4680 }
4673 gfx_v7_0_free_microcode(adev); 4681 gfx_v7_0_free_microcode(adev);
4674 4682
4675 return 0; 4683 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b8002ac3e536..9ecdf621a74a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2118,6 +2118,15 @@ static int gfx_v8_0_sw_fini(void *handle)
2118 2118
2119 gfx_v8_0_mec_fini(adev); 2119 gfx_v8_0_mec_fini(adev);
2120 gfx_v8_0_rlc_fini(adev); 2120 gfx_v8_0_rlc_fini(adev);
2121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2122 &adev->gfx.rlc.clear_state_gpu_addr,
2123 (void **)&adev->gfx.rlc.cs_ptr);
2124 if ((adev->asic_type == CHIP_CARRIZO) ||
2125 (adev->asic_type == CHIP_STONEY)) {
2126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2127 &adev->gfx.rlc.cp_table_gpu_addr,
2128 (void **)&adev->gfx.rlc.cp_table_ptr);
2129 }
2121 gfx_v8_0_free_microcode(adev); 2130 gfx_v8_0_free_microcode(adev);
2122 2131
2123 return 0; 2132 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7f15bb2c5233..da43813d67a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] =
207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
208}; 208};
209 209
210static const u32 golden_settings_gc_9_x_common[] =
211{
212 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
213 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
214};
215
210#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 216#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
211#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 217#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
212 218
@@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
242 default: 248 default:
243 break; 249 break;
244 } 250 }
251
252 amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
253 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
245} 254}
246 255
247static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 256static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
@@ -988,12 +997,22 @@ static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
988 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 997 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
989} 998}
990 999
1000static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1001 uint32_t wave, uint32_t thread,
1002 uint32_t start, uint32_t size,
1003 uint32_t *dst)
1004{
1005 wave_read_regs(
1006 adev, simd, wave, thread,
1007 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1008}
991 1009
992static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1010static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
993 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1011 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
994 .select_se_sh = &gfx_v9_0_select_se_sh, 1012 .select_se_sh = &gfx_v9_0_select_se_sh,
995 .read_wave_data = &gfx_v9_0_read_wave_data, 1013 .read_wave_data = &gfx_v9_0_read_wave_data,
996 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1014 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1015 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
997}; 1016};
998 1017
999static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1018static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
@@ -1449,6 +1468,14 @@ static int gfx_v9_0_sw_fini(void *handle)
1449 1468
1450 gfx_v9_0_mec_fini(adev); 1469 gfx_v9_0_mec_fini(adev);
1451 gfx_v9_0_ngg_fini(adev); 1470 gfx_v9_0_ngg_fini(adev);
1471 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1472 &adev->gfx.rlc.clear_state_gpu_addr,
1473 (void **)&adev->gfx.rlc.cs_ptr);
1474 if (adev->asic_type == CHIP_RAVEN) {
1475 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1476 &adev->gfx.rlc.cp_table_gpu_addr,
1477 (void **)&adev->gfx.rlc.cp_table_ptr);
1478 }
1452 gfx_v9_0_free_microcode(adev); 1479 gfx_v9_0_free_microcode(adev);
1453 1480
1454 return 0; 1481 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 621699331e09..c8f1aebeac7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle)
392static int gmc_v9_0_late_init(void *handle) 392static int gmc_v9_0_late_init(void *handle)
393{ 393{
394 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 394 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
395 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 }; 395 /*
396 * The latest engine allocation on gfx9 is:
397 * Engine 0, 1: idle
398 * Engine 2, 3: firmware
399 * Engine 4~13: amdgpu ring, subject to change when ring number changes
400 * Engine 14~15: idle
401 * Engine 16: kfd tlb invalidation
402 * Engine 17: Gart flushes
403 */
404 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
396 unsigned i; 405 unsigned i;
397 406
398 for(i = 0; i < adev->num_rings; ++i) { 407 for(i = 0; i < adev->num_rings; ++i) {
@@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle)
405 ring->funcs->vmhub); 414 ring->funcs->vmhub);
406 } 415 }
407 416
408 /* Engine 17 is used for GART flushes */ 417 /* Engine 16 is used for KFD and 17 for GART flushes */
409 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 418 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
410 BUG_ON(vm_inv_eng[i] > 17); 419 BUG_ON(vm_inv_eng[i] > 16);
411 420
412 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 421 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
413} 422}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index a129bc5b1844..c6febbf0bf69 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
1486 if (vddci_id_buf[i] == virtual_voltage_id) { 1486 if (vddci_id_buf[i] == virtual_voltage_id) {
1487 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1487 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1488 if (efuse_voltage_id <= leakage_bin[j]) { 1488 if (efuse_voltage_id <= leakage_bin[j]) {
1489 *vddci = vddci_buf[j * profile->ucElbVDDC_Num + i]; 1489 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1490 break; 1490 break;
1491 } 1491 }
1492 } 1492 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index d1af1483c69b..a651ebcf44fd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -830,9 +830,9 @@ static int init_over_drive_limits(
830 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table) 830 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
831{ 831{
832 hwmgr->platform_descriptor.overdriveLimit.engineClock = 832 hwmgr->platform_descriptor.overdriveLimit.engineClock =
833 le16_to_cpu(powerplay_table->ulMaxODEngineClock); 833 le32_to_cpu(powerplay_table->ulMaxODEngineClock);
834 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 834 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
835 le16_to_cpu(powerplay_table->ulMaxODMemoryClock); 835 le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
836 836
837 hwmgr->platform_descriptor.minOverdriveVDDC = 0; 837 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
838 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; 838 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4466469cf8ab..e33ec7fc5d09 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3778 "Trying to Unfreeze MCLK DPM when DPM is disabled", 3778 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3779 ); 3779 );
3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3781 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 3781 PPSMC_MSG_MCLKDPM_UnfreezeLevel),
3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3783 return -EINVAL); 3783 return -EINVAL);
3784 } 3784 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 4f79c21f27ed..f8d838c2c8ee 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
753 uint32_t config_telemetry = 0; 753 uint32_t config_telemetry = 0;
754 struct pp_atomfwctrl_voltage_table vol_table; 754 struct pp_atomfwctrl_voltage_table vol_table;
755 struct cgs_system_info sys_info = {0}; 755 struct cgs_system_info sys_info = {0};
756 uint32_t reg;
756 757
757 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 758 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
758 if (data == NULL) 759 if (data == NULL)
@@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
859 advanceFanControlParameters.usFanPWMMinLimit * 860 advanceFanControlParameters.usFanPWMMinLimit *
860 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 861 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
861 862
863 reg = soc15_get_register_offset(DF_HWID, 0,
864 mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
865 mmDF_CS_AON0_DramBaseAddress0);
866 data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
867 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
868 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
869 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
870 "Mem Channel Index Exceeded maximum!",
871 return -EINVAL);
872
862 return result; 873 return result;
863} 874}
864 875
@@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1777 struct vega10_single_dpm_table *dpm_table = 1788 struct vega10_single_dpm_table *dpm_table =
1778 &(data->dpm_table.mem_table); 1789 &(data->dpm_table.mem_table);
1779 int result = 0; 1790 int result = 0;
1780 uint32_t i, j, reg, mem_channels; 1791 uint32_t i, j;
1781 1792
1782 for (i = 0; i < dpm_table->count; i++) { 1793 for (i = 0; i < dpm_table->count; i++) {
1783 result = vega10_populate_single_memory_level(hwmgr, 1794 result = vega10_populate_single_memory_level(hwmgr,
@@ -1801,20 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1801 i++; 1812 i++;
1802 } 1813 }
1803 1814
1804 reg = soc15_get_register_offset(DF_HWID, 0, 1815 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1805 mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
1806 mmDF_CS_AON0_DramBaseAddress0);
1807 mem_channels = (cgs_read_register(hwmgr->device, reg) &
1808 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
1809 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
1810 PP_ASSERT_WITH_CODE(mem_channels < ARRAY_SIZE(channel_number),
1811 "Mem Channel Index Exceeded maximum!",
1812 return -1);
1813
1814 pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
1815 pp_table->MemoryChannelWidth = 1816 pp_table->MemoryChannelWidth =
1816 cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH * 1817 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1817 channel_number[mem_channels]); 1818 channel_number[data->mem_channels]);
1818 1819
1819 pp_table->LowestUclkReservedForUlv = 1820 pp_table->LowestUclkReservedForUlv =
1820 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1821 (uint8_t)(data->lowest_uclk_reserved_for_ulv);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index b4b461c3b8ee..8f7358cc3327 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -389,6 +389,7 @@ struct vega10_hwmgr {
389 uint32_t config_telemetry; 389 uint32_t config_telemetry;
390 uint32_t smu_version; 390 uint32_t smu_version;
391 uint32_t acg_loop_state; 391 uint32_t acg_loop_state;
392 uint32_t mem_channels;
392}; 393};
393 394
394#define VEGA10_DPM2_NEAR_TDP_DEC 10 395#define VEGA10_DPM2_NEAR_TDP_DEC 10
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 704fc8934616..25f4b2e9a44f 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -234,6 +234,10 @@ int drm_connector_init(struct drm_device *dev,
234 config->link_status_property, 234 config->link_status_property,
235 0); 235 0);
236 236
237 drm_object_attach_property(&connector->base,
238 config->non_desktop_property,
239 0);
240
237 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { 241 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
238 drm_object_attach_property(&connector->base, config->prop_crtc_id, 0); 242 drm_object_attach_property(&connector->base, config->prop_crtc_id, 0);
239 } 243 }
@@ -763,6 +767,10 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
763 * value of link-status is "GOOD". If something fails during or after modeset, 767 * value of link-status is "GOOD". If something fails during or after modeset,
764 * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers 768 * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers
765 * should update this value using drm_mode_connector_set_link_status_property(). 769 * should update this value using drm_mode_connector_set_link_status_property().
770 * non_desktop:
771 * Indicates the output should be ignored for purposes of displaying a
772 * standard desktop environment or console. This is most likely because
773 * the output device is not rectilinear.
766 * 774 *
767 * Connectors also have one standardized atomic property: 775 * Connectors also have one standardized atomic property:
768 * 776 *
@@ -811,6 +819,11 @@ int drm_connector_create_standard_properties(struct drm_device *dev)
811 return -ENOMEM; 819 return -ENOMEM;
812 dev->mode_config.link_status_property = prop; 820 dev->mode_config.link_status_property = prop;
813 821
822 prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop");
823 if (!prop)
824 return -ENOMEM;
825 dev->mode_config.non_desktop_property = prop;
826
814 return 0; 827 return 0;
815} 828}
816 829
@@ -1194,6 +1207,10 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector,
1194 if (edid) 1207 if (edid)
1195 size = EDID_LENGTH * (1 + edid->extensions); 1208 size = EDID_LENGTH * (1 + edid->extensions);
1196 1209
1210 drm_object_property_set_value(&connector->base,
1211 dev->mode_config.non_desktop_property,
1212 connector->display_info.non_desktop);
1213
1197 ret = drm_property_replace_global_blob(dev, 1214 ret = drm_property_replace_global_blob(dev,
1198 &connector->edid_blob_ptr, 1215 &connector->edid_blob_ptr,
1199 size, 1216 size,
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 00ddabfbf980..2e8fb51282ef 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -82,6 +82,8 @@
82#define EDID_QUIRK_FORCE_6BPC (1 << 10) 82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
83/* Force 10bpc */ 83/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11) 84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
85/* Non desktop display (i.e. HMD) */
86#define EDID_QUIRK_NON_DESKTOP (1 << 12)
85 87
86struct detailed_mode_closure { 88struct detailed_mode_closure {
87 struct drm_connector *connector; 89 struct drm_connector *connector;
@@ -157,6 +159,9 @@ static const struct edid_quirk {
157 159
158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 160 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 161 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
162
163 /* HTC Vive VR Headset */
164 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
160}; 165};
161 166
162/* 167/*
@@ -4393,7 +4398,7 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
4393} 4398}
4394 4399
4395static void drm_add_display_info(struct drm_connector *connector, 4400static void drm_add_display_info(struct drm_connector *connector,
4396 struct edid *edid) 4401 struct edid *edid, u32 quirks)
4397{ 4402{
4398 struct drm_display_info *info = &connector->display_info; 4403 struct drm_display_info *info = &connector->display_info;
4399 4404
@@ -4407,6 +4412,8 @@ static void drm_add_display_info(struct drm_connector *connector,
4407 info->max_tmds_clock = 0; 4412 info->max_tmds_clock = 0;
4408 info->dvi_dual = false; 4413 info->dvi_dual = false;
4409 4414
4415 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4416
4410 if (edid->revision < 3) 4417 if (edid->revision < 3)
4411 return; 4418 return;
4412 4419
@@ -4627,7 +4634,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4627 * To avoid multiple parsing of same block, lets parse that map 4634 * To avoid multiple parsing of same block, lets parse that map
4628 * from sink info, before parsing CEA modes. 4635 * from sink info, before parsing CEA modes.
4629 */ 4636 */
4630 drm_add_display_info(connector, edid); 4637 drm_add_display_info(connector, edid, quirks);
4631 4638
4632 /* 4639 /*
4633 * EDID spec says modes should be preferred in this order: 4640 * EDID spec says modes should be preferred in this order:
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 116d1f1337c7..07374008f146 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2033,6 +2033,9 @@ static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
2033{ 2033{
2034 bool enable; 2034 bool enable;
2035 2035
2036 if (connector->display_info.non_desktop)
2037 return false;
2038
2036 if (strict) 2039 if (strict)
2037 enable = connector->status == connector_status_connected; 2040 enable = connector->status == connector_status_connected;
2038 else 2041 else
@@ -2052,7 +2055,8 @@ static void drm_enable_connectors(struct drm_fb_helper *fb_helper,
2052 connector = fb_helper->connector_info[i]->connector; 2055 connector = fb_helper->connector_info[i]->connector;
2053 enabled[i] = drm_connector_enabled(connector, true); 2056 enabled[i] = drm_connector_enabled(connector, true);
2054 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, 2057 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
2055 enabled[i] ? "yes" : "no"); 2058 connector->display_info.non_desktop ? "non desktop" : enabled[i] ? "yes" : "no");
2059
2056 any_enabled |= enabled[i]; 2060 any_enabled |= enabled[i];
2057 } 2061 }
2058 2062
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 58e9e0601a61..faf17b83b910 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -210,7 +210,6 @@ static int fsl_dcu_drm_pm_suspend(struct device *dev)
210 return PTR_ERR(fsl_dev->state); 210 return PTR_ERR(fsl_dev->state);
211 } 211 }
212 212
213 clk_disable_unprepare(fsl_dev->pix_clk);
214 clk_disable_unprepare(fsl_dev->clk); 213 clk_disable_unprepare(fsl_dev->clk);
215 214
216 return 0; 215 return 0;
@@ -233,6 +232,7 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
233 if (fsl_dev->tcon) 232 if (fsl_dev->tcon)
234 fsl_tcon_bypass_enable(fsl_dev->tcon); 233 fsl_tcon_bypass_enable(fsl_dev->tcon);
235 fsl_dcu_drm_init_planes(fsl_dev->drm); 234 fsl_dcu_drm_init_planes(fsl_dev->drm);
235 enable_irq(fsl_dev->irq);
236 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state); 236 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
237 237
238 console_lock(); 238 console_lock();
@@ -240,7 +240,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
240 console_unlock(); 240 console_unlock();
241 241
242 drm_kms_helper_poll_enable(fsl_dev->drm); 242 drm_kms_helper_poll_enable(fsl_dev->drm);
243 enable_irq(fsl_dev->irq);
244 243
245 return 0; 244 return 0;
246} 245}
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index edd7d8127d19..c54806d08dd7 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -102,7 +102,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
102{ 102{
103 struct drm_encoder *encoder = &fsl_dev->encoder; 103 struct drm_encoder *encoder = &fsl_dev->encoder;
104 struct drm_connector *connector = &fsl_dev->connector.base; 104 struct drm_connector *connector = &fsl_dev->connector.base;
105 struct drm_mode_config *mode_config = &fsl_dev->drm->mode_config;
106 int ret; 105 int ret;
107 106
108 fsl_dev->connector.encoder = encoder; 107 fsl_dev->connector.encoder = encoder;
@@ -122,10 +121,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
122 if (ret < 0) 121 if (ret < 0)
123 goto err_sysfs; 122 goto err_sysfs;
124 123
125 drm_object_property_set_value(&connector->base,
126 mode_config->dpms_property,
127 DRM_MODE_DPMS_OFF);
128
129 ret = drm_panel_attach(panel, connector); 124 ret = drm_panel_attach(panel, connector);
130 if (ret) { 125 if (ret) {
131 dev_err(fsl_dev->dev, "failed to attach panel\n"); 126 dev_err(fsl_dev->dev, "failed to attach panel\n");
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 53e0b24beda6..9a9961802f5c 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -115,7 +115,7 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc)
115 115
116 if (crtc->state) { 116 if (crtc->state) {
117 if (crtc->state->mode_blob) 117 if (crtc->state->mode_blob)
118 drm_property_unreference_blob(crtc->state->mode_blob); 118 drm_property_blob_put(crtc->state->mode_blob);
119 119
120 state = to_imx_crtc_state(crtc->state); 120 state = to_imx_crtc_state(crtc->state);
121 memset(state, 0, sizeof(*state)); 121 memset(state, 0, sizeof(*state));
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index 8def97d75030..aedecda9728a 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -183,7 +183,7 @@ static int imx_pd_register(struct drm_device *drm,
183 &imx_pd_connector_helper_funcs); 183 &imx_pd_connector_helper_funcs);
184 drm_connector_init(drm, &imxpd->connector, 184 drm_connector_init(drm, &imxpd->connector,
185 &imx_pd_connector_funcs, 185 &imx_pd_connector_funcs,
186 DRM_MODE_CONNECTOR_VGA); 186 DRM_MODE_CONNECTOR_DPI);
187 } 187 }
188 188
189 if (imxpd->panel) 189 if (imxpd->panel)
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 2fcf805d3a16..33b821d6d018 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
245 } 245 }
246 246
247 info->par = rfbdev; 247 info->par = rfbdev;
248 info->skip_vt_switch = true;
249 248
250 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); 249 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
251 if (ret) { 250 if (ret) {
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 4bcacd3f4861..b0a1dedac802 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -174,9 +174,9 @@ struct tegra_sor {
174 174
175 struct reset_control *rst; 175 struct reset_control *rst;
176 struct clk *clk_parent; 176 struct clk *clk_parent;
177 struct clk *clk_brick;
178 struct clk *clk_safe; 177 struct clk *clk_safe;
179 struct clk *clk_src; 178 struct clk *clk_out;
179 struct clk *clk_pad;
180 struct clk *clk_dp; 180 struct clk *clk_dp;
181 struct clk *clk; 181 struct clk *clk;
182 182
@@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
255 255
256 clk_disable_unprepare(sor->clk); 256 clk_disable_unprepare(sor->clk);
257 257
258 err = clk_set_parent(sor->clk, parent); 258 err = clk_set_parent(sor->clk_out, parent);
259 if (err < 0) 259 if (err < 0)
260 return err; 260 return err;
261 261
@@ -266,24 +266,24 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
266 return 0; 266 return 0;
267} 267}
268 268
269struct tegra_clk_sor_brick { 269struct tegra_clk_sor_pad {
270 struct clk_hw hw; 270 struct clk_hw hw;
271 struct tegra_sor *sor; 271 struct tegra_sor *sor;
272}; 272};
273 273
274static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) 274static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
275{ 275{
276 return container_of(hw, struct tegra_clk_sor_brick, hw); 276 return container_of(hw, struct tegra_clk_sor_pad, hw);
277} 277}
278 278
279static const char * const tegra_clk_sor_brick_parents[] = { 279static const char * const tegra_clk_sor_pad_parents[] = {
280 "pll_d2_out0", "pll_dp" 280 "pll_d2_out0", "pll_dp"
281}; 281};
282 282
283static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) 283static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
284{ 284{
285 struct tegra_clk_sor_brick *brick = to_brick(hw); 285 struct tegra_clk_sor_pad *pad = to_pad(hw);
286 struct tegra_sor *sor = brick->sor; 286 struct tegra_sor *sor = pad->sor;
287 u32 value; 287 u32 value;
288 288
289 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 289 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
@@ -304,10 +304,10 @@ static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
304 return 0; 304 return 0;
305} 305}
306 306
307static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) 307static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
308{ 308{
309 struct tegra_clk_sor_brick *brick = to_brick(hw); 309 struct tegra_clk_sor_pad *pad = to_pad(hw);
310 struct tegra_sor *sor = brick->sor; 310 struct tegra_sor *sor = pad->sor;
311 u8 parent = U8_MAX; 311 u8 parent = U8_MAX;
312 u32 value; 312 u32 value;
313 313
@@ -328,33 +328,33 @@ static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
328 return parent; 328 return parent;
329} 329}
330 330
331static const struct clk_ops tegra_clk_sor_brick_ops = { 331static const struct clk_ops tegra_clk_sor_pad_ops = {
332 .set_parent = tegra_clk_sor_brick_set_parent, 332 .set_parent = tegra_clk_sor_pad_set_parent,
333 .get_parent = tegra_clk_sor_brick_get_parent, 333 .get_parent = tegra_clk_sor_pad_get_parent,
334}; 334};
335 335
336static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, 336static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
337 const char *name) 337 const char *name)
338{ 338{
339 struct tegra_clk_sor_brick *brick; 339 struct tegra_clk_sor_pad *pad;
340 struct clk_init_data init; 340 struct clk_init_data init;
341 struct clk *clk; 341 struct clk *clk;
342 342
343 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); 343 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
344 if (!brick) 344 if (!pad)
345 return ERR_PTR(-ENOMEM); 345 return ERR_PTR(-ENOMEM);
346 346
347 brick->sor = sor; 347 pad->sor = sor;
348 348
349 init.name = name; 349 init.name = name;
350 init.flags = 0; 350 init.flags = 0;
351 init.parent_names = tegra_clk_sor_brick_parents; 351 init.parent_names = tegra_clk_sor_pad_parents;
352 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); 352 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
353 init.ops = &tegra_clk_sor_brick_ops; 353 init.ops = &tegra_clk_sor_pad_ops;
354 354
355 brick->hw.init = &init; 355 pad->hw.init = &init;
356 356
357 clk = devm_clk_register(sor->dev, &brick->hw); 357 clk = devm_clk_register(sor->dev, &pad->hw);
358 358
359 return clk; 359 return clk;
360} 360}
@@ -998,8 +998,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
998 998
999 /* switch to safe parent clock */ 999 /* switch to safe parent clock */
1000 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1000 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1001 if (err < 0) 1001 if (err < 0) {
1002 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1002 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1003 return err;
1004 }
1003 1005
1004 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1006 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1005 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1007 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
@@ -2007,8 +2009,10 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2007 2009
2008 /* switch to safe parent clock */ 2010 /* switch to safe parent clock */
2009 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2011 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2010 if (err < 0) 2012 if (err < 0) {
2011 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2013 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2014 return;
2015 }
2012 2016
2013 div = clk_get_rate(sor->clk) / 1000000 * 4; 2017 div = clk_get_rate(sor->clk) / 1000000 * 4;
2014 2018
@@ -2111,13 +2115,17 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2111 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2115 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2112 2116
2113 /* switch to parent clock */ 2117 /* switch to parent clock */
2114 err = clk_set_parent(sor->clk_src, sor->clk_parent); 2118 err = clk_set_parent(sor->clk, sor->clk_parent);
2115 if (err < 0) 2119 if (err < 0) {
2116 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2117
2118 err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2119 if (err < 0)
2120 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2120 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2121 return;
2122 }
2123
2124 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2125 if (err < 0) {
2126 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2127 return;
2128 }
2121 2129
2122 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2130 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2123 2131
@@ -2628,11 +2636,24 @@ static int tegra_sor_probe(struct platform_device *pdev)
2628 } 2636 }
2629 2637
2630 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 2638 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2631 sor->clk_src = devm_clk_get(&pdev->dev, "source"); 2639 struct device_node *np = pdev->dev.of_node;
2632 if (IS_ERR(sor->clk_src)) { 2640 const char *name;
2633 err = PTR_ERR(sor->clk_src); 2641
2634 dev_err(sor->dev, "failed to get source clock: %d\n", 2642 /*
2635 err); 2643 * For backwards compatibility with Tegra210 device trees,
2644 * fall back to the old clock name "source" if the new "out"
2645 * clock is not available.
2646 */
2647 if (of_property_match_string(np, "clock-names", "out") < 0)
2648 name = "source";
2649 else
2650 name = "out";
2651
2652 sor->clk_out = devm_clk_get(&pdev->dev, name);
2653 if (IS_ERR(sor->clk_out)) {
2654 err = PTR_ERR(sor->clk_out);
2655 dev_err(sor->dev, "failed to get %s clock: %d\n",
2656 name, err);
2636 goto remove; 2657 goto remove;
2637 } 2658 }
2638 } 2659 }
@@ -2658,16 +2679,60 @@ static int tegra_sor_probe(struct platform_device *pdev)
2658 goto remove; 2679 goto remove;
2659 } 2680 }
2660 2681
2682 /*
2683 * Starting with Tegra186, the BPMP provides an implementation for
2684 * the pad output clock, so we have to look it up from device tree.
2685 */
2686 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
2687 if (IS_ERR(sor->clk_pad)) {
2688 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
2689 err = PTR_ERR(sor->clk_pad);
2690 goto remove;
2691 }
2692
2693 /*
2694 * If the pad output clock is not available, then we assume
2695 * we're on Tegra210 or earlier and have to provide our own
2696 * implementation.
2697 */
2698 sor->clk_pad = NULL;
2699 }
2700
2701 /*
2702 * The bootloader may have set up the SOR such that it's module clock
2703 * is sourced by one of the display PLLs. However, that doesn't work
2704 * without properly having set up other bits of the SOR.
2705 */
2706 err = clk_set_parent(sor->clk_out, sor->clk_safe);
2707 if (err < 0) {
2708 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
2709 goto remove;
2710 }
2711
2661 platform_set_drvdata(pdev, sor); 2712 platform_set_drvdata(pdev, sor);
2662 pm_runtime_enable(&pdev->dev); 2713 pm_runtime_enable(&pdev->dev);
2663 2714
2664 pm_runtime_get_sync(&pdev->dev); 2715 /*
2665 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); 2716 * On Tegra210 and earlier, provide our own implementation for the
2666 pm_runtime_put(&pdev->dev); 2717 * pad output clock.
2718 */
2719 if (!sor->clk_pad) {
2720 err = pm_runtime_get_sync(&pdev->dev);
2721 if (err < 0) {
2722 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
2723 err);
2724 goto remove;
2725 }
2726
2727 sor->clk_pad = tegra_clk_sor_pad_register(sor,
2728 "sor1_pad_clkout");
2729 pm_runtime_put(&pdev->dev);
2730 }
2667 2731
2668 if (IS_ERR(sor->clk_brick)) { 2732 if (IS_ERR(sor->clk_pad)) {
2669 err = PTR_ERR(sor->clk_brick); 2733 err = PTR_ERR(sor->clk_pad);
2670 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); 2734 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
2735 err);
2671 goto remove; 2736 goto remove;
2672 } 2737 }
2673 2738
diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index 28fed7e206d0..81ac82455ce4 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -12,14 +12,3 @@ config DRM_TILCDC
12 controller, for example AM33xx in beagle-bone, DA8xx, or 12 controller, for example AM33xx in beagle-bone, DA8xx, or
13 OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver. 13 OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver.
14 14
15config DRM_TILCDC_SLAVE_COMPAT
16 bool "Support device tree blobs using TI LCDC Slave binding"
17 depends on DRM_TILCDC
18 default y
19 select OF_RESOLVE
20 select OF_OVERLAY
21 help
22 Choose this option if you need a kernel that is compatible
23 with device tree blobs using the obsolete "ti,tilcdc,slave"
24 binding. If you find "ti,tilcdc,slave"-string from your DTB,
25 you probably need this. Otherwise you do not.
diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile
index b9e1108e5b4e..87f9480e43b0 100644
--- a/drivers/gpu/drm/tilcdc/Makefile
+++ b/drivers/gpu/drm/tilcdc/Makefile
@@ -3,9 +3,6 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
3 ccflags-y += -Werror 3 ccflags-y += -Werror
4endif 4endif
5 5
6obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \
7 tilcdc_slave_compat.dtb.o
8
9tilcdc-y := \ 6tilcdc-y := \
10 tilcdc_plane.o \ 7 tilcdc_plane.o \
11 tilcdc_crtc.o \ 8 tilcdc_crtc.o \
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
deleted file mode 100644
index d2b9e5f04724..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+++ /dev/null
@@ -1,264 +0,0 @@
1/*
2 * Copyright (C) 2015 Texas Instruments
3 * Author: Jyri Sarha <jsarha@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 */
10
11/*
12 * To support the old "ti,tilcdc,slave" binding the binding has to be
13 * transformed to the new external encoder binding.
14 */
15
16#include <linux/kernel.h>
17#include <linux/of.h>
18#include <linux/of_graph.h>
19#include <linux/of_fdt.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22
23#include "tilcdc_slave_compat.h"
24
25struct kfree_table {
26 int total;
27 int num;
28 void **table;
29};
30
31static int __init kfree_table_init(struct kfree_table *kft)
32{
33 kft->total = 32;
34 kft->num = 0;
35 kft->table = kmalloc(kft->total * sizeof(*kft->table),
36 GFP_KERNEL);
37 if (!kft->table)
38 return -ENOMEM;
39
40 return 0;
41}
42
43static int __init kfree_table_add(struct kfree_table *kft, void *p)
44{
45 if (kft->num == kft->total) {
46 void **old = kft->table;
47
48 kft->total *= 2;
49 kft->table = krealloc(old, kft->total * sizeof(*kft->table),
50 GFP_KERNEL);
51 if (!kft->table) {
52 kft->table = old;
53 kfree(p);
54 return -ENOMEM;
55 }
56 }
57 kft->table[kft->num++] = p;
58 return 0;
59}
60
61static void __init kfree_table_free(struct kfree_table *kft)
62{
63 int i;
64
65 for (i = 0; i < kft->num; i++)
66 kfree(kft->table[i]);
67
68 kfree(kft->table);
69}
70
71static
72struct property * __init tilcdc_prop_dup(const struct property *prop,
73 struct kfree_table *kft)
74{
75 struct property *nprop;
76
77 nprop = kzalloc(sizeof(*nprop), GFP_KERNEL);
78 if (!nprop || kfree_table_add(kft, nprop))
79 return NULL;
80
81 nprop->name = kstrdup(prop->name, GFP_KERNEL);
82 if (!nprop->name || kfree_table_add(kft, nprop->name))
83 return NULL;
84
85 nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL);
86 if (!nprop->value || kfree_table_add(kft, nprop->value))
87 return NULL;
88
89 nprop->length = prop->length;
90
91 return nprop;
92}
93
94static void __init tilcdc_copy_props(struct device_node *from,
95 struct device_node *to,
96 const char * const props[],
97 struct kfree_table *kft)
98{
99 struct property *prop;
100 int i;
101
102 for (i = 0; props[i]; i++) {
103 prop = of_find_property(from, props[i], NULL);
104 if (!prop)
105 continue;
106
107 prop = tilcdc_prop_dup(prop, kft);
108 if (!prop)
109 continue;
110
111 prop->next = to->properties;
112 to->properties = prop;
113 }
114}
115
116static int __init tilcdc_prop_str_update(struct property *prop,
117 const char *str,
118 struct kfree_table *kft)
119{
120 prop->value = kstrdup(str, GFP_KERNEL);
121 if (kfree_table_add(kft, prop->value) || !prop->value)
122 return -ENOMEM;
123 prop->length = strlen(str)+1;
124 return 0;
125}
126
127static void __init tilcdc_node_disable(struct device_node *node)
128{
129 struct property *prop;
130
131 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
132 if (!prop)
133 return;
134
135 prop->name = "status";
136 prop->value = "disabled";
137 prop->length = strlen((char *)prop->value)+1;
138
139 of_update_property(node, prop);
140}
141
142static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
143{
144 const int size = __dtb_tilcdc_slave_compat_end -
145 __dtb_tilcdc_slave_compat_begin;
146 static void *overlay_data;
147 struct device_node *overlay;
148
149 if (!size) {
150 pr_warn("%s: No overlay data\n", __func__);
151 return NULL;
152 }
153
154 overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin,
155 size, GFP_KERNEL);
156 if (!overlay_data || kfree_table_add(kft, overlay_data))
157 return NULL;
158
159 of_fdt_unflatten_tree(overlay_data, NULL, &overlay);
160 if (!overlay) {
161 pr_warn("%s: Unfattening overlay tree failed\n", __func__);
162 return NULL;
163 }
164
165 return overlay;
166}
167
168static const struct of_device_id tilcdc_slave_of_match[] __initconst = {
169 { .compatible = "ti,tilcdc,slave", },
170 {},
171};
172
173static const struct of_device_id tilcdc_of_match[] __initconst = {
174 { .compatible = "ti,am33xx-tilcdc", },
175 {},
176};
177
178static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = {
179 { .compatible = "nxp,tda998x", },
180 {},
181};
182
183static const char * const tilcdc_slave_props[] __initconst = {
184 "pinctrl-names",
185 "pinctrl-0",
186 "pinctrl-1",
187 NULL
188};
189
190static void __init tilcdc_convert_slave_node(void)
191{
192 struct device_node *slave = NULL, *lcdc = NULL;
193 struct device_node *i2c = NULL, *fragment = NULL;
194 struct device_node *overlay, *encoder;
195 struct property *prop;
196 /* For all memory needed for the overlay tree. This memory can
197 be freed after the overlay has been applied. */
198 struct kfree_table kft;
199 int ovcs_id, ret;
200
201 if (kfree_table_init(&kft))
202 return;
203
204 lcdc = of_find_matching_node(NULL, tilcdc_of_match);
205 slave = of_find_matching_node(NULL, tilcdc_slave_of_match);
206
207 if (!slave || !of_device_is_available(lcdc))
208 goto out;
209
210 i2c = of_parse_phandle(slave, "i2c", 0);
211 if (!i2c) {
212 pr_err("%s: Can't find i2c node trough phandle\n", __func__);
213 goto out;
214 }
215
216 overlay = tilcdc_get_overlay(&kft);
217 if (!overlay)
218 goto out;
219
220 encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match);
221 if (!encoder) {
222 pr_err("%s: Failed to find tda998x node\n", __func__);
223 goto out;
224 }
225
226 tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft);
227
228 for_each_child_of_node(overlay, fragment) {
229 prop = of_find_property(fragment, "target-path", NULL);
230 if (!prop)
231 continue;
232 if (!strncmp("i2c", (char *)prop->value, prop->length))
233 if (tilcdc_prop_str_update(prop, i2c->full_name, &kft))
234 goto out;
235 if (!strncmp("lcdc", (char *)prop->value, prop->length))
236 if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft))
237 goto out;
238 }
239
240 tilcdc_node_disable(slave);
241
242 ovcs_id = 0;
243 ret = of_overlay_apply(overlay, &ovcs_id);
244 if (ret)
245 pr_err("%s: Applying overlay changeset failed: %d\n",
246 __func__, ret);
247 else
248 pr_info("%s: ti,tilcdc,slave node successfully converted\n",
249 __func__);
250out:
251 kfree_table_free(&kft);
252 of_node_put(i2c);
253 of_node_put(slave);
254 of_node_put(lcdc);
255 of_node_put(fragment);
256}
257
258static int __init tilcdc_slave_compat_init(void)
259{
260 tilcdc_convert_slave_node();
261 return 0;
262}
263
264subsys_initcall(tilcdc_slave_compat_init);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
deleted file mode 100644
index 693f8b0aea2d..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * DTS overlay for converting ti,tilcdc,slave binding to new binding.
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 * Author: Jyri Sarha <jsarha@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 */
11
12/*
13 * target-path property values are simple tags that are replaced with
14 * correct values in tildcdc_slave_compat.c. Some properties are also
15 * copied over from the ti,tilcdc,slave node.
16 */
17
18/dts-v1/;
19/ {
20 fragment@0 {
21 target-path = "i2c";
22 __overlay__ {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 tda19988 {
26 compatible = "nxp,tda998x";
27 reg = <0x70>;
28 status = "okay";
29
30 port {
31 hdmi_0: endpoint@0 {
32 remote-endpoint = <&lcd_0>;
33 };
34 };
35 };
36 };
37 };
38
39 fragment@1 {
40 target-path = "lcdc";
41 __overlay__ {
42 port {
43 lcd_0: endpoint@0 {
44 remote-endpoint = <&hdmi_0>;
45 };
46 };
47 };
48 };
49
50 __local_fixups__ {
51 fragment@0 {
52 __overlay__ {
53 tda19988 {
54 port {
55 endpoint@0 {
56 remote-endpoint = <0>;
57 };
58 };
59 };
60 };
61 };
62 fragment@1 {
63 __overlay__ {
64 port {
65 endpoint@0 {
66 remote-endpoint = <0>;
67 };
68 };
69 };
70 };
71 };
72};
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
deleted file mode 100644
index 403d35d87d0b..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2015 Texas Instruments
3 * Author: Jyri Sarha <jsarha@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17/* This header declares the symbols defined in tilcdc_slave_compat.dts */
18
19#ifndef __TILCDC_SLAVE_COMPAT_H__
20#define __TILCDC_SLAVE_COMPAT_H__
21
22extern uint8_t __dtb_tilcdc_slave_compat_begin[];
23extern uint8_t __dtb_tilcdc_slave_compat_end[];
24
25#endif /* __TILCDC_SLAVE_COMPAT_H__ */
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 7a4b8362dda8..49bfe6e7d005 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -249,11 +249,8 @@ EXPORT_SYMBOL_GPL(ipu_dc_enable);
249 249
250void ipu_dc_enable_channel(struct ipu_dc *dc) 250void ipu_dc_enable_channel(struct ipu_dc *dc)
251{ 251{
252 int di;
253 u32 reg; 252 u32 reg;
254 253
255 di = dc->di;
256
257 reg = readl(dc->base + DC_WR_CH_CONF); 254 reg = readl(dc->base + DC_WR_CH_CONF);
258 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL; 255 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
259 writel(reg, dc->base + DC_WR_CH_CONF); 256 writel(reg, dc->base + DC_WR_CH_CONF);
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 7a7140543012..df9807a3caae 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -284,6 +284,11 @@ struct drm_display_info {
284 * @hdmi: advance features of a HDMI sink. 284 * @hdmi: advance features of a HDMI sink.
285 */ 285 */
286 struct drm_hdmi_info hdmi; 286 struct drm_hdmi_info hdmi;
287
288 /**
289 * @non_desktop: Non desktop display (HMD).
290 */
291 bool non_desktop;
287}; 292};
288 293
289int drm_display_info_set_bus_formats(struct drm_display_info *info, 294int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 0b4ac2ebc610..b21e827c5c78 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -728,6 +728,13 @@ struct drm_mode_config {
728 */ 728 */
729 struct drm_property *suggested_y_property; 729 struct drm_property *suggested_y_property;
730 730
731 /**
732 * @non_desktop_property: Optional connector property with a hint
733 * that device isn't a standard display, and the console/desktop,
734 * should not be displayed on it.
735 */
736 struct drm_property *non_desktop_property;
737
731 /* dumb ioctl parameters */ 738 /* dumb ioctl parameters */
732 uint32_t preferred_depth, prefer_shadow; 739 uint32_t preferred_depth, prefer_shadow;
733 740
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
deleted file mode 100644
index a75d304473d5..000000000000
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ /dev/null
@@ -1,887 +0,0 @@
1/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __MSM_BUS_IDS_H
14#define __MSM_BUS_IDS_H
15
16/* Aggregation types */
17#define AGG_SCHEME_NONE 0
18#define AGG_SCHEME_LEG 1
19#define AGG_SCHEME_1 2
20
21/* Topology related enums */
22#define MSM_BUS_FAB_DEFAULT 0
23#define MSM_BUS_FAB_APPSS 0
24#define MSM_BUS_FAB_SYSTEM 1024
25#define MSM_BUS_FAB_MMSS 2048
26#define MSM_BUS_FAB_SYSTEM_FPB 3072
27#define MSM_BUS_FAB_CPSS_FPB 4096
28
29#define MSM_BUS_FAB_BIMC 0
30#define MSM_BUS_FAB_SYS_NOC 1024
31#define MSM_BUS_FAB_MMSS_NOC 2048
32#define MSM_BUS_FAB_OCMEM_NOC 3072
33#define MSM_BUS_FAB_PERIPH_NOC 4096
34#define MSM_BUS_FAB_CONFIG_NOC 5120
35#define MSM_BUS_FAB_OCMEM_VNOC 6144
36#define MSM_BUS_FAB_MMSS_AHB 2049
37#define MSM_BUS_FAB_A0_NOC 6145
38#define MSM_BUS_FAB_A1_NOC 6146
39#define MSM_BUS_FAB_A2_NOC 6147
40#define MSM_BUS_FAB_GNOC 6148
41#define MSM_BUS_FAB_CR_VIRT 6149
42
43#define MSM_BUS_MASTER_FIRST 1
44#define MSM_BUS_MASTER_AMPSS_M0 1
45#define MSM_BUS_MASTER_AMPSS_M1 2
46#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
47#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
48#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
49#define MSM_BUS_MASTER_SPS 6
50#define MSM_BUS_MASTER_ADM_PORT0 7
51#define MSM_BUS_MASTER_ADM_PORT1 8
52#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
53#define MSM_BUS_MASTER_ADM1_PORT1 10
54#define MSM_BUS_MASTER_LPASS_PROC 11
55#define MSM_BUS_MASTER_MSS_PROCI 12
56#define MSM_BUS_MASTER_MSS_PROCD 13
57#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
58#define MSM_BUS_MASTER_LPASS 15
59#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
60#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
61#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
62#define MSM_BUS_MASTER_ADM1_CI 19
63#define MSM_BUS_MASTER_ADM0_CI 20
64#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
65#define MSM_BUS_MASTER_MDP_PORT0 22
66#define MSM_BUS_MASTER_MDP_PORT1 23
67#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
68#define MSM_BUS_MASTER_ROTATOR 25
69#define MSM_BUS_MASTER_GRAPHICS_3D 26
70#define MSM_BUS_MASTER_JPEG_DEC 27
71#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
72#define MSM_BUS_MASTER_VFE 29
73#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE
74#define MSM_BUS_MASTER_VPE 30
75#define MSM_BUS_MASTER_JPEG_ENC 31
76#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
77#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
78#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
79#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
80#define MSM_BUS_MASTER_SPDM 36
81#define MSM_BUS_MASTER_RPM 37
82#define MSM_BUS_MASTER_MSS 38
83#define MSM_BUS_MASTER_RIVA 39
84#define MSM_BUS_MASTER_SNOC_VMEM 40
85#define MSM_BUS_MASTER_MSS_SW_PROC 41
86#define MSM_BUS_MASTER_MSS_FW_PROC 42
87#define MSM_BUS_MASTER_HMSS 43
88#define MSM_BUS_MASTER_GSS_NAV 44
89#define MSM_BUS_MASTER_PCIE 45
90#define MSM_BUS_MASTER_SATA 46
91#define MSM_BUS_MASTER_CRYPTO 47
92#define MSM_BUS_MASTER_VIDEO_CAP 48
93#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
94#define MSM_BUS_MASTER_VIDEO_ENC 50
95#define MSM_BUS_MASTER_VIDEO_DEC 51
96#define MSM_BUS_MASTER_LPASS_AHB 52
97#define MSM_BUS_MASTER_QDSS_BAM 53
98#define MSM_BUS_MASTER_SNOC_CFG 54
99#define MSM_BUS_MASTER_CRYPTO_CORE0 55
100#define MSM_BUS_MASTER_CRYPTO_CORE1 56
101#define MSM_BUS_MASTER_MSS_NAV 57
102#define MSM_BUS_MASTER_OCMEM_DMA 58
103#define MSM_BUS_MASTER_WCSS 59
104#define MSM_BUS_MASTER_QDSS_ETR 60
105#define MSM_BUS_MASTER_USB3 61
106#define MSM_BUS_MASTER_JPEG 62
107#define MSM_BUS_MASTER_VIDEO_P0 63
108#define MSM_BUS_MASTER_VIDEO_P1 64
109#define MSM_BUS_MASTER_MSS_PROC 65
110#define MSM_BUS_MASTER_JPEG_OCMEM 66
111#define MSM_BUS_MASTER_MDP_OCMEM 67
112#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
113#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
114#define MSM_BUS_MASTER_VFE_OCMEM 70
115#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
116#define MSM_BUS_MASTER_RPM_INST 72
117#define MSM_BUS_MASTER_RPM_DATA 73
118#define MSM_BUS_MASTER_RPM_SYS 74
119#define MSM_BUS_MASTER_DEHR 75
120#define MSM_BUS_MASTER_QDSS_DAP 76
121#define MSM_BUS_MASTER_TIC 77
122#define MSM_BUS_MASTER_SDCC_1 78
123#define MSM_BUS_MASTER_SDCC_3 79
124#define MSM_BUS_MASTER_SDCC_4 80
125#define MSM_BUS_MASTER_SDCC_2 81
126#define MSM_BUS_MASTER_TSIF 82
127#define MSM_BUS_MASTER_BAM_DMA 83
128#define MSM_BUS_MASTER_BLSP_2 84
129#define MSM_BUS_MASTER_USB_HSIC 85
130#define MSM_BUS_MASTER_BLSP_1 86
131#define MSM_BUS_MASTER_USB_HS 87
132#define MSM_BUS_MASTER_PNOC_CFG 88
133#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
134#define MSM_BUS_MASTER_IPA 90
135#define MSM_BUS_MASTER_QPIC 91
136#define MSM_BUS_MASTER_MDPE 92
137#define MSM_BUS_MASTER_USB_HS2 93
138#define MSM_BUS_MASTER_VPU 94
139#define MSM_BUS_MASTER_UFS 95
140#define MSM_BUS_MASTER_BCAST 96
141#define MSM_BUS_MASTER_CRYPTO_CORE2 97
142#define MSM_BUS_MASTER_EMAC 98
143#define MSM_BUS_MASTER_VPU_1 99
144#define MSM_BUS_MASTER_PCIE_1 100
145#define MSM_BUS_MASTER_USB3_1 101
146#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
147#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
148#define MSM_BUS_MASTER_TCU_0 104
149#define MSM_BUS_MASTER_TCU_1 105
150#define MSM_BUS_MASTER_CPP 106
151#define MSM_BUS_MASTER_AUDIO 107
152#define MSM_BUS_MASTER_PCIE_2 108
153#define MSM_BUS_MASTER_VFE1 109
154#define MSM_BUS_MASTER_XM_USB_HS1 110
155#define MSM_BUS_MASTER_PCNOC_BIMC_1 111
156#define MSM_BUS_MASTER_BIMC_PCNOC 112
157#define MSM_BUS_MASTER_XI_USB_HSIC 113
158#define MSM_BUS_MASTER_SGMII 114
159#define MSM_BUS_SPMI_FETCHER 115
160#define MSM_BUS_MASTER_GNOC_BIMC 116
161#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
162#define MSM_BUS_MASTER_CNOC_A2NOC 118
163#define MSM_BUS_MASTER_WLAN 119
164#define MSM_BUS_MASTER_MSS_CE 120
165#define MSM_BUS_MASTER_CDSP_PROC 121
166#define MSM_BUS_MASTER_GNOC_SNOC 122
167#define MSM_BUS_MASTER_PIMEM 123
168#define MSM_BUS_MASTER_MASTER_LAST 124
169
170#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
171#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
172
173#define MSM_BUS_SNOC_MM_INT_0 10000
174#define MSM_BUS_SNOC_MM_INT_1 10001
175#define MSM_BUS_SNOC_MM_INT_2 10002
176#define MSM_BUS_SNOC_MM_INT_BIMC 10003
177#define MSM_BUS_SNOC_INT_0 10004
178#define MSM_BUS_SNOC_INT_1 10005
179#define MSM_BUS_SNOC_INT_BIMC 10006
180#define MSM_BUS_SNOC_BIMC_0_MAS 10007
181#define MSM_BUS_SNOC_BIMC_1_MAS 10008
182#define MSM_BUS_SNOC_QDSS_INT 10009
183#define MSM_BUS_PNOC_SNOC_MAS 10010
184#define MSM_BUS_PNOC_SNOC_SLV 10011
185#define MSM_BUS_PNOC_INT_0 10012
186#define MSM_BUS_PNOC_INT_1 10013
187#define MSM_BUS_PNOC_M_0 10014
188#define MSM_BUS_PNOC_M_1 10015
189#define MSM_BUS_BIMC_SNOC_MAS 10016
190#define MSM_BUS_BIMC_SNOC_SLV 10017
191#define MSM_BUS_PNOC_SLV_0 10018
192#define MSM_BUS_PNOC_SLV_1 10019
193#define MSM_BUS_PNOC_SLV_2 10020
194#define MSM_BUS_PNOC_SLV_3 10021
195#define MSM_BUS_PNOC_SLV_4 10022
196#define MSM_BUS_PNOC_SLV_8 10023
197#define MSM_BUS_PNOC_SLV_9 10024
198#define MSM_BUS_SNOC_BIMC_0_SLV 10025
199#define MSM_BUS_SNOC_BIMC_1_SLV 10026
200#define MSM_BUS_MNOC_BIMC_MAS 10027
201#define MSM_BUS_MNOC_BIMC_SLV 10028
202#define MSM_BUS_BIMC_MNOC_MAS 10029
203#define MSM_BUS_BIMC_MNOC_SLV 10030
204#define MSM_BUS_SNOC_BIMC_MAS 10031
205#define MSM_BUS_SNOC_BIMC_SLV 10032
206#define MSM_BUS_CNOC_SNOC_MAS 10033
207#define MSM_BUS_CNOC_SNOC_SLV 10034
208#define MSM_BUS_SNOC_CNOC_MAS 10035
209#define MSM_BUS_SNOC_CNOC_SLV 10036
210#define MSM_BUS_OVNOC_SNOC_MAS 10037
211#define MSM_BUS_OVNOC_SNOC_SLV 10038
212#define MSM_BUS_SNOC_OVNOC_MAS 10039
213#define MSM_BUS_SNOC_OVNOC_SLV 10040
214#define MSM_BUS_SNOC_PNOC_MAS 10041
215#define MSM_BUS_SNOC_PNOC_SLV 10042
216#define MSM_BUS_BIMC_INT_APPS_EBI 10043
217#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
218#define MSM_BUS_SNOC_BIMC_2_MAS 10045
219#define MSM_BUS_SNOC_BIMC_2_SLV 10046
220#define MSM_BUS_PNOC_SLV_5 10047
221#define MSM_BUS_PNOC_SLV_7 10048
222#define MSM_BUS_PNOC_INT_2 10049
223#define MSM_BUS_PNOC_INT_3 10050
224#define MSM_BUS_PNOC_INT_4 10051
225#define MSM_BUS_PNOC_INT_5 10052
226#define MSM_BUS_PNOC_INT_6 10053
227#define MSM_BUS_PNOC_INT_7 10054
228#define MSM_BUS_BIMC_SNOC_1_MAS 10055
229#define MSM_BUS_BIMC_SNOC_1_SLV 10056
230#define MSM_BUS_PNOC_A1NOC_MAS 10057
231#define MSM_BUS_PNOC_A1NOC_SLV 10058
232#define MSM_BUS_CNOC_A1NOC_MAS 10059
233#define MSM_BUS_A0NOC_SNOC_MAS 10060
234#define MSM_BUS_A0NOC_SNOC_SLV 10061
235#define MSM_BUS_A1NOC_SNOC_SLV 10062
236#define MSM_BUS_A1NOC_SNOC_MAS 10063
237#define MSM_BUS_A2NOC_SNOC_MAS 10064
238#define MSM_BUS_A2NOC_SNOC_SLV 10065
239#define MSM_BUS_SNOC_INT_2 10066
240#define MSM_BUS_A0NOC_QDSS_INT 10067
241#define MSM_BUS_INT_LAST 10068
242
243#define MSM_BUS_INT_TEST_ID 20000
244#define MSM_BUS_INT_TEST_LAST 20050
245
246#define MSM_BUS_SLAVE_FIRST 512
247#define MSM_BUS_SLAVE_EBI_CH0 512
248#define MSM_BUS_SLAVE_EBI_CH1 513
249#define MSM_BUS_SLAVE_AMPSS_L2 514
250#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
251#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
252#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
253#define MSM_BUS_SLAVE_SPS 518
254#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
255#define MSM_BUS_SLAVE_AMPSS 520
256#define MSM_BUS_SLAVE_MSS 521
257#define MSM_BUS_SLAVE_LPASS 522
258#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
259#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
260#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
261#define MSM_BUS_SLAVE_CORESIGHT 526
262#define MSM_BUS_SLAVE_RIVA 527
263#define MSM_BUS_SLAVE_SMI 528
264#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
265#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
266#define MSM_BUS_SLAVE_MM_IMEM 531
267#define MSM_BUS_SLAVE_CRYPTO 532
268#define MSM_BUS_SLAVE_SPDM 533
269#define MSM_BUS_SLAVE_RPM 534
270#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
271#define MSM_BUS_SLAVE_MPM 536
272#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
273#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
274#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
275#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
276#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
277#define MSM_BUS_SLAVE_GSBI1_UART 542
278#define MSM_BUS_SLAVE_GSBI2_UART 543
279#define MSM_BUS_SLAVE_GSBI3_UART 544
280#define MSM_BUS_SLAVE_GSBI4_UART 545
281#define MSM_BUS_SLAVE_GSBI5_UART 546
282#define MSM_BUS_SLAVE_GSBI6_UART 547
283#define MSM_BUS_SLAVE_GSBI7_UART 548
284#define MSM_BUS_SLAVE_GSBI8_UART 549
285#define MSM_BUS_SLAVE_GSBI9_UART 550
286#define MSM_BUS_SLAVE_GSBI10_UART 551
287#define MSM_BUS_SLAVE_GSBI11_UART 552
288#define MSM_BUS_SLAVE_GSBI12_UART 553
289#define MSM_BUS_SLAVE_GSBI1_QUP 554
290#define MSM_BUS_SLAVE_GSBI2_QUP 555
291#define MSM_BUS_SLAVE_GSBI3_QUP 556
292#define MSM_BUS_SLAVE_GSBI4_QUP 557
293#define MSM_BUS_SLAVE_GSBI5_QUP 558
294#define MSM_BUS_SLAVE_GSBI6_QUP 559
295#define MSM_BUS_SLAVE_GSBI7_QUP 560
296#define MSM_BUS_SLAVE_GSBI8_QUP 561
297#define MSM_BUS_SLAVE_GSBI9_QUP 562
298#define MSM_BUS_SLAVE_GSBI10_QUP 563
299#define MSM_BUS_SLAVE_GSBI11_QUP 564
300#define MSM_BUS_SLAVE_GSBI12_QUP 565
301#define MSM_BUS_SLAVE_EBI2_NAND 566
302#define MSM_BUS_SLAVE_EBI2_CS0 567
303#define MSM_BUS_SLAVE_EBI2_CS1 568
304#define MSM_BUS_SLAVE_EBI2_CS2 569
305#define MSM_BUS_SLAVE_EBI2_CS3 570
306#define MSM_BUS_SLAVE_EBI2_CS4 571
307#define MSM_BUS_SLAVE_EBI2_CS5 572
308#define MSM_BUS_SLAVE_USB_FS1 573
309#define MSM_BUS_SLAVE_USB_FS2 574
310#define MSM_BUS_SLAVE_TSIF 575
311#define MSM_BUS_SLAVE_MSM_TSSC 576
312#define MSM_BUS_SLAVE_MSM_PDM 577
313#define MSM_BUS_SLAVE_MSM_DIMEM 578
314#define MSM_BUS_SLAVE_MSM_TCSR 579
315#define MSM_BUS_SLAVE_MSM_PRNG 580
316#define MSM_BUS_SLAVE_GSS 581
317#define MSM_BUS_SLAVE_SATA 582
318#define MSM_BUS_SLAVE_USB3 583
319#define MSM_BUS_SLAVE_WCSS 584
320#define MSM_BUS_SLAVE_OCIMEM 585
321#define MSM_BUS_SLAVE_SNOC_OCMEM 586
322#define MSM_BUS_SLAVE_SERVICE_SNOC 587
323#define MSM_BUS_SLAVE_QDSS_STM 588
324#define MSM_BUS_SLAVE_CAMERA_CFG 589
325#define MSM_BUS_SLAVE_DISPLAY_CFG 590
326#define MSM_BUS_SLAVE_OCMEM_CFG 591
327#define MSM_BUS_SLAVE_CPR_CFG 592
328#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
329#define MSM_BUS_SLAVE_MISC_CFG 594
330#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
331#define MSM_BUS_SLAVE_VENUS_CFG 596
332#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
333#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
334#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
335#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
336#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
337#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
338#define MSM_BUS_SLAVE_SERVICE_MNOC 603
339#define MSM_BUS_SLAVE_OCMEM 604
340#define MSM_BUS_SLAVE_SERVICE_ONOC 605
341#define MSM_BUS_SLAVE_SDCC_1 606
342#define MSM_BUS_SLAVE_SDCC_3 607
343#define MSM_BUS_SLAVE_SDCC_2 608
344#define MSM_BUS_SLAVE_SDCC_4 609
345#define MSM_BUS_SLAVE_BAM_DMA 610
346#define MSM_BUS_SLAVE_BLSP_2 611
347#define MSM_BUS_SLAVE_USB_HSIC 612
348#define MSM_BUS_SLAVE_BLSP_1 613
349#define MSM_BUS_SLAVE_USB_HS 614
350#define MSM_BUS_SLAVE_PDM 615
351#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
352#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
353#define MSM_BUS_SLAVE_PRNG 618
354#define MSM_BUS_SLAVE_SERVICE_PNOC 619
355#define MSM_BUS_SLAVE_CLK_CTL 620
356#define MSM_BUS_SLAVE_CNOC_MSS 621
357#define MSM_BUS_SLAVE_SECURITY 622
358#define MSM_BUS_SLAVE_TCSR 623
359#define MSM_BUS_SLAVE_TLMM 624
360#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
361#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
362#define MSM_BUS_SLAVE_IMEM_CFG 627
363#define MSM_BUS_SLAVE_MESSAGE_RAM 628
364#define MSM_BUS_SLAVE_BIMC_CFG 629
365#define MSM_BUS_SLAVE_BOOT_ROM 630
366#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
367#define MSM_BUS_SLAVE_PMIC_ARB 632
368#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
369#define MSM_BUS_SLAVE_DEHR_CFG 634
370#define MSM_BUS_SLAVE_QDSS_CFG 635
371#define MSM_BUS_SLAVE_RBCPR_CFG 636
372#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
373#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
374#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
375#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
376#define MSM_BUS_SLAVE_PNOC_CFG 641
377#define MSM_BUS_SLAVE_SNOC_CFG 642
378#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
379#define MSM_BUS_SLAVE_PHY_APU_CFG 644
380#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
381#define MSM_BUS_SLAVE_SERVICE_CNOC 646
382#define MSM_BUS_SLAVE_IPS_CFG 647
383#define MSM_BUS_SLAVE_QPIC 648
384#define MSM_BUS_SLAVE_DSI_CFG 649
385#define MSM_BUS_SLAVE_UFS_CFG 650
386#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
387#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
388#define MSM_BUS_SLAVE_PCIE_CFG 653
389#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
390#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
391#define MSM_BUS_SLAVE_AVSYNC_CFG 656
392#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
393#define MSM_BUS_SLAVE_VPU_CFG 658
394#define MSM_BUS_SLAVE_BCAST_CFG 659
395#define MSM_BUS_SLAVE_KLM_CFG 660
396#define MSM_BUS_SLAVE_GENI_IR_CFG 661
397#define MSM_BUS_SLAVE_OCMEM_GFX 662
398#define MSM_BUS_SLAVE_CATS_128 663
399#define MSM_BUS_SLAVE_OCMEM_64 664
400#define MSM_BUS_SLAVE_PCIE_0 665
401#define MSM_BUS_SLAVE_PCIE_1 666
402#define MSM_BUS_SLAVE_PCIE_0_CFG 667
403#define MSM_BUS_SLAVE_PCIE_1_CFG 668
404#define MSM_BUS_SLAVE_SRVC_MNOC 669
405#define MSM_BUS_SLAVE_USB_HS2 670
406#define MSM_BUS_SLAVE_AUDIO 671
407#define MSM_BUS_SLAVE_TCU 672
408#define MSM_BUS_SLAVE_APPSS 673
409#define MSM_BUS_SLAVE_PCIE_PARF 674
410#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
411#define MSM_BUS_SLAVE_IPA_CFG 676
412#define MSM_BUS_SLAVE_A0NOC_SNOC 677
413#define MSM_BUS_SLAVE_A1NOC_SNOC 678
414#define MSM_BUS_SLAVE_A2NOC_SNOC 679
415#define MSM_BUS_SLAVE_HMSS_L3 680
416#define MSM_BUS_SLAVE_PIMEM_CFG 681
417#define MSM_BUS_SLAVE_DCC_CFG 682
418#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
419#define MSM_BUS_SLAVE_PCIE_2_CFG 684
420#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
421#define MSM_BUS_SLAVE_A0NOC_CFG 686
422#define MSM_BUS_SLAVE_A1NOC_CFG 687
423#define MSM_BUS_SLAVE_A2NOC_CFG 688
424#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
425#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
426#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
427#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
428#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
429#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
430#define MSM_BUS_SLAVE_MMAGIC_CFG 695
431#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
432#define MSM_BUS_SLAVE_SSC_CFG 697
433#define MSM_BUS_SLAVE_DSA_CFG 698
434#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
435#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
436#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
437#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
438#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
439#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
440#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
441#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
442#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
443#define MSM_BUS_SLAVE_VMEM_CFG 708
444#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709
445#define MSM_BUS_SLAVE_VMEM 710
446#define MSM_BUS_SLAVE_AHB2PHY 711
447#define MSM_BUS_SLAVE_PIMEM 712
448#define MSM_BUS_SLAVE_SNOC_VMEM 713
449#define MSM_BUS_SLAVE_PCIE_2 714
450#define MSM_BUS_SLAVE_RBCPR_MX 715
451#define MSM_BUS_SLAVE_RBCPR_CX 716
452#define MSM_BUS_SLAVE_BIMC_PCNOC 717
453#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
454#define MSM_BUS_SLAVE_SGMII 719
455#define MSM_BUS_SLAVE_SPMI_FETCHER 720
456#define MSM_BUS_PNOC_SLV_6 721
457#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
458#define MSM_BUS_SLAVE_WLAN 723
459#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
460#define MSM_BUS_SLAVE_CNOC_A2NOC 725
461#define MSM_BUS_SLAVE_GLM 726
462#define MSM_BUS_SLAVE_GNOC_BIMC 727
463#define MSM_BUS_SLAVE_GNOC_SNOC 728
464#define MSM_BUS_SLAVE_QM_CFG 729
465#define MSM_BUS_SLAVE_TLMM_EAST 730
466#define MSM_BUS_SLAVE_TLMM_NORTH 731
467#define MSM_BUS_SLAVE_TLMM_WEST 732
468#define MSM_BUS_SLAVE_SKL 733
469#define MSM_BUS_SLAVE_LPASS_TCM 734
470#define MSM_BUS_SLAVE_TLMM_SOUTH 735
471#define MSM_BUS_SLAVE_TLMM_CENTER 736
472#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737
473#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738
474#define MSM_BUS_SLAVE_CDSP 739
475#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740
476#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741
477#define MSM_BUS_SLAVE_CSI_PHY_CFG 742
478#define MSM_BUS_SLAVE_LAST 743
479
480#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
481#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
482
483/*
484 * ID's used in RPM messages
485 */
486#define ICBID_MASTER_APPSS_PROC 0
487#define ICBID_MASTER_MSS_PROC 1
488#define ICBID_MASTER_MNOC_BIMC 2
489#define ICBID_MASTER_SNOC_BIMC 3
490#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
491#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
492#define ICBID_MASTER_CNOC_MNOC_CFG 5
493#define ICBID_MASTER_GFX3D 6
494#define ICBID_MASTER_JPEG 7
495#define ICBID_MASTER_MDP 8
496#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
497#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
498#define ICBID_MASTER_VIDEO 9
499#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
500#define ICBID_MASTER_VIDEO_P1 10
501#define ICBID_MASTER_VFE 11
502#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
503#define ICBID_MASTER_CNOC_ONOC_CFG 12
504#define ICBID_MASTER_JPEG_OCMEM 13
505#define ICBID_MASTER_MDP_OCMEM 14
506#define ICBID_MASTER_VIDEO_P0_OCMEM 15
507#define ICBID_MASTER_VIDEO_P1_OCMEM 16
508#define ICBID_MASTER_VFE_OCMEM 17
509#define ICBID_MASTER_LPASS_AHB 18
510#define ICBID_MASTER_QDSS_BAM 19
511#define ICBID_MASTER_SNOC_CFG 20
512#define ICBID_MASTER_BIMC_SNOC 21
513#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
514#define ICBID_MASTER_CNOC_SNOC 22
515#define ICBID_MASTER_CRYPTO 23
516#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
517#define ICBID_MASTER_CRYPTO_CORE1 24
518#define ICBID_MASTER_LPASS_PROC 25
519#define ICBID_MASTER_MSS 26
520#define ICBID_MASTER_MSS_NAV 27
521#define ICBID_MASTER_OCMEM_DMA 28
522#define ICBID_MASTER_PNOC_SNOC 29
523#define ICBID_MASTER_WCSS 30
524#define ICBID_MASTER_QDSS_ETR 31
525#define ICBID_MASTER_USB3 32
526#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
527#define ICBID_MASTER_SDCC_1 33
528#define ICBID_MASTER_SDCC_3 34
529#define ICBID_MASTER_SDCC_2 35
530#define ICBID_MASTER_SDCC_4 36
531#define ICBID_MASTER_TSIF 37
532#define ICBID_MASTER_BAM_DMA 38
533#define ICBID_MASTER_BLSP_2 39
534#define ICBID_MASTER_USB_HSIC 40
535#define ICBID_MASTER_BLSP_1 41
536#define ICBID_MASTER_USB_HS 42
537#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
538#define ICBID_MASTER_PNOC_CFG 43
539#define ICBID_MASTER_SNOC_PNOC 44
540#define ICBID_MASTER_RPM_INST 45
541#define ICBID_MASTER_RPM_DATA 46
542#define ICBID_MASTER_RPM_SYS 47
543#define ICBID_MASTER_DEHR 48
544#define ICBID_MASTER_QDSS_DAP 49
545#define ICBID_MASTER_SPDM 50
546#define ICBID_MASTER_TIC 51
547#define ICBID_MASTER_SNOC_CNOC 52
548#define ICBID_MASTER_GFX3D_OCMEM 53
549#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
550#define ICBID_MASTER_OVIRT_SNOC 54
551#define ICBID_MASTER_SNOC_OVIRT 55
552#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
553#define ICBID_MASTER_ONOC_OVIRT 56
554#define ICBID_MASTER_USB_HS2 57
555#define ICBID_MASTER_QPIC 58
556#define ICBID_MASTER_IPA 59
557#define ICBID_MASTER_DSI 60
558#define ICBID_MASTER_MDP1 61
559#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
560#define ICBID_MASTER_VPU_PROC 62
561#define ICBID_MASTER_VPU 63
562#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
563#define ICBID_MASTER_CRYPTO_CORE2 64
564#define ICBID_MASTER_PCIE_0 65
565#define ICBID_MASTER_PCIE_1 66
566#define ICBID_MASTER_SATA 67
567#define ICBID_MASTER_UFS 68
568#define ICBID_MASTER_USB3_1 69
569#define ICBID_MASTER_VIDEO_OCMEM 70
570#define ICBID_MASTER_VPU1 71
571#define ICBID_MASTER_VCAP 72
572#define ICBID_MASTER_EMAC 73
573#define ICBID_MASTER_BCAST 74
574#define ICBID_MASTER_MMSS_PROC 75
575#define ICBID_MASTER_SNOC_BIMC_1 76
576#define ICBID_MASTER_SNOC_PCNOC 77
577#define ICBID_MASTER_AUDIO 78
578#define ICBID_MASTER_MM_INT_0 79
579#define ICBID_MASTER_MM_INT_1 80
580#define ICBID_MASTER_MM_INT_2 81
581#define ICBID_MASTER_MM_INT_BIMC 82
582#define ICBID_MASTER_MSS_INT 83
583#define ICBID_MASTER_PCNOC_CFG 84
584#define ICBID_MASTER_PCNOC_INT_0 85
585#define ICBID_MASTER_PCNOC_INT_1 86
586#define ICBID_MASTER_PCNOC_M_0 87
587#define ICBID_MASTER_PCNOC_M_1 88
588#define ICBID_MASTER_PCNOC_S_0 89
589#define ICBID_MASTER_PCNOC_S_1 90
590#define ICBID_MASTER_PCNOC_S_2 91
591#define ICBID_MASTER_PCNOC_S_3 92
592#define ICBID_MASTER_PCNOC_S_4 93
593#define ICBID_MASTER_PCNOC_S_6 94
594#define ICBID_MASTER_PCNOC_S_7 95
595#define ICBID_MASTER_PCNOC_S_8 96
596#define ICBID_MASTER_PCNOC_S_9 97
597#define ICBID_MASTER_QDSS_INT 98
598#define ICBID_MASTER_SNOC_INT_0 99
599#define ICBID_MASTER_SNOC_INT_1 100
600#define ICBID_MASTER_SNOC_INT_BIMC 101
601#define ICBID_MASTER_TCU_0 102
602#define ICBID_MASTER_TCU_1 103
603#define ICBID_MASTER_BIMC_INT_0 104
604#define ICBID_MASTER_BIMC_INT_1 105
605#define ICBID_MASTER_CAMERA 106
606#define ICBID_MASTER_RICA 107
607#define ICBID_MASTER_SNOC_BIMC_2 108
608#define ICBID_MASTER_BIMC_SNOC_1 109
609#define ICBID_MASTER_A0NOC_SNOC 110
610#define ICBID_MASTER_A1NOC_SNOC 111
611#define ICBID_MASTER_A2NOC_SNOC 112
612#define ICBID_MASTER_PIMEM 113
613#define ICBID_MASTER_SNOC_VMEM 114
614#define ICBID_MASTER_CPP 115
615#define ICBID_MASTER_CNOC_A1NOC 116
616#define ICBID_MASTER_PNOC_A1NOC 117
617#define ICBID_MASTER_HMSS 118
618#define ICBID_MASTER_PCIE_2 119
619#define ICBID_MASTER_ROTATOR 120
620#define ICBID_MASTER_VENUS_VMEM 121
621#define ICBID_MASTER_DCC 122
622#define ICBID_MASTER_MCDMA 123
623#define ICBID_MASTER_PCNOC_INT_2 124
624#define ICBID_MASTER_PCNOC_INT_3 125
625#define ICBID_MASTER_PCNOC_INT_4 126
626#define ICBID_MASTER_PCNOC_INT_5 127
627#define ICBID_MASTER_PCNOC_INT_6 128
628#define ICBID_MASTER_PCNOC_S_5 129
629#define ICBID_MASTER_SENSORS_AHB 130
630#define ICBID_MASTER_SENSORS_PROC 131
631#define ICBID_MASTER_QSPI 132
632#define ICBID_MASTER_VFE1 133
633#define ICBID_MASTER_SNOC_INT_2 134
634#define ICBID_MASTER_SMMNOC_BIMC 135
635#define ICBID_MASTER_CRVIRT_A1NOC 136
636#define ICBID_MASTER_XM_USB_HS1 137
637#define ICBID_MASTER_XI_USB_HS1 138
638#define ICBID_MASTER_PCNOC_BIMC_1 139
639#define ICBID_MASTER_BIMC_PCNOC 140
640#define ICBID_MASTER_XI_HSIC 141
641#define ICBID_MASTER_SGMII 142
642#define ICBID_MASTER_SPMI_FETCHER 143
643#define ICBID_MASTER_GNOC_BIMC 144
644#define ICBID_MASTER_CRVIRT_A2NOC 145
645#define ICBID_MASTER_CNOC_A2NOC 146
646#define ICBID_MASTER_WLAN 147
647#define ICBID_MASTER_MSS_CE 148
648#define ICBID_MASTER_CDSP_PROC 149
649#define ICBID_MASTER_GNOC_SNOC 150
650
651#define ICBID_SLAVE_EBI1 0
652#define ICBID_SLAVE_APPSS_L2 1
653#define ICBID_SLAVE_BIMC_SNOC 2
654#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
655#define ICBID_SLAVE_CAMERA_CFG 3
656#define ICBID_SLAVE_DISPLAY_CFG 4
657#define ICBID_SLAVE_OCMEM_CFG 5
658#define ICBID_SLAVE_CPR_CFG 6
659#define ICBID_SLAVE_CPR_XPU_CFG 7
660#define ICBID_SLAVE_MISC_CFG 8
661#define ICBID_SLAVE_MISC_XPU_CFG 9
662#define ICBID_SLAVE_VENUS_CFG 10
663#define ICBID_SLAVE_GFX3D_CFG 11
664#define ICBID_SLAVE_MMSS_CLK_CFG 12
665#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
666#define ICBID_SLAVE_MNOC_MPU_CFG 14
667#define ICBID_SLAVE_ONOC_MPU_CFG 15
668#define ICBID_SLAVE_MNOC_BIMC 16
669#define ICBID_SLAVE_SERVICE_MNOC 17
670#define ICBID_SLAVE_OCMEM 18
671#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
672#define ICBID_SLAVE_SERVICE_ONOC 19
673#define ICBID_SLAVE_APPSS 20
674#define ICBID_SLAVE_LPASS 21
675#define ICBID_SLAVE_USB3 22
676#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
677#define ICBID_SLAVE_WCSS 23
678#define ICBID_SLAVE_SNOC_BIMC 24
679#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
680#define ICBID_SLAVE_SNOC_CNOC 25
681#define ICBID_SLAVE_IMEM 26
682#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
683#define ICBID_SLAVE_SNOC_OVIRT 27
684#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
685#define ICBID_SLAVE_SNOC_PNOC 28
686#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
687#define ICBID_SLAVE_SERVICE_SNOC 29
688#define ICBID_SLAVE_QDSS_STM 30
689#define ICBID_SLAVE_SDCC_1 31
690#define ICBID_SLAVE_SDCC_3 32
691#define ICBID_SLAVE_SDCC_2 33
692#define ICBID_SLAVE_SDCC_4 34
693#define ICBID_SLAVE_TSIF 35
694#define ICBID_SLAVE_BAM_DMA 36
695#define ICBID_SLAVE_BLSP_2 37
696#define ICBID_SLAVE_USB_HSIC 38
697#define ICBID_SLAVE_BLSP_1 39
698#define ICBID_SLAVE_USB_HS 40
699#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
700#define ICBID_SLAVE_PDM 41
701#define ICBID_SLAVE_PERIPH_APU_CFG 42
702#define ICBID_SLAVE_PNOC_MPU_CFG 43
703#define ICBID_SLAVE_PRNG 44
704#define ICBID_SLAVE_PNOC_SNOC 45
705#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
706#define ICBID_SLAVE_SERVICE_PNOC 46
707#define ICBID_SLAVE_CLK_CTL 47
708#define ICBID_SLAVE_CNOC_MSS 48
709#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
710#define ICBID_SLAVE_SECURITY 49
711#define ICBID_SLAVE_TCSR 50
712#define ICBID_SLAVE_TLMM 51
713#define ICBID_SLAVE_CRYPTO_0_CFG 52
714#define ICBID_SLAVE_CRYPTO_1_CFG 53
715#define ICBID_SLAVE_IMEM_CFG 54
716#define ICBID_SLAVE_MESSAGE_RAM 55
717#define ICBID_SLAVE_BIMC_CFG 56
718#define ICBID_SLAVE_BOOT_ROM 57
719#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
720#define ICBID_SLAVE_PMIC_ARB 59
721#define ICBID_SLAVE_SPDM_WRAPPER 60
722#define ICBID_SLAVE_DEHR_CFG 61
723#define ICBID_SLAVE_MPM 62
724#define ICBID_SLAVE_QDSS_CFG 63
725#define ICBID_SLAVE_RBCPR_CFG 64
726#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
727#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
728#define ICBID_SLAVE_CNOC_MNOC_CFG 66
729#define ICBID_SLAVE_SNOC_MPU_CFG 67
730#define ICBID_SLAVE_CNOC_ONOC_CFG 68
731#define ICBID_SLAVE_PNOC_CFG 69
732#define ICBID_SLAVE_SNOC_CFG 70
733#define ICBID_SLAVE_EBI1_DLL_CFG 71
734#define ICBID_SLAVE_PHY_APU_CFG 72
735#define ICBID_SLAVE_EBI1_PHY_CFG 73
736#define ICBID_SLAVE_RPM 74
737#define ICBID_SLAVE_CNOC_SNOC 75
738#define ICBID_SLAVE_SERVICE_CNOC 76
739#define ICBID_SLAVE_OVIRT_SNOC 77
740#define ICBID_SLAVE_OVIRT_OCMEM 78
741#define ICBID_SLAVE_USB_HS2 79
742#define ICBID_SLAVE_QPIC 80
743#define ICBID_SLAVE_IPS_CFG 81
744#define ICBID_SLAVE_DSI_CFG 82
745#define ICBID_SLAVE_USB3_1 83
746#define ICBID_SLAVE_PCIE_0 84
747#define ICBID_SLAVE_PCIE_1 85
748#define ICBID_SLAVE_PSS_SMMU_CFG 86
749#define ICBID_SLAVE_CRYPTO_2_CFG 87
750#define ICBID_SLAVE_PCIE_0_CFG 88
751#define ICBID_SLAVE_PCIE_1_CFG 89
752#define ICBID_SLAVE_SATA_CFG 90
753#define ICBID_SLAVE_SPSS_GENI_IR 91
754#define ICBID_SLAVE_UFS_CFG 92
755#define ICBID_SLAVE_AVSYNC_CFG 93
756#define ICBID_SLAVE_VPU_CFG 94
757#define ICBID_SLAVE_USB_PHY_CFG 95
758#define ICBID_SLAVE_RBCPR_MX_CFG 96
759#define ICBID_SLAVE_PCIE_PARF 97
760#define ICBID_SLAVE_VCAP_CFG 98
761#define ICBID_SLAVE_EMAC_CFG 99
762#define ICBID_SLAVE_BCAST_CFG 100
763#define ICBID_SLAVE_KLM_CFG 101
764#define ICBID_SLAVE_DISPLAY_PWM 102
765#define ICBID_SLAVE_GENI 103
766#define ICBID_SLAVE_SNOC_BIMC_1 104
767#define ICBID_SLAVE_AUDIO 105
768#define ICBID_SLAVE_CATS_0 106
769#define ICBID_SLAVE_CATS_1 107
770#define ICBID_SLAVE_MM_INT_0 108
771#define ICBID_SLAVE_MM_INT_1 109
772#define ICBID_SLAVE_MM_INT_2 110
773#define ICBID_SLAVE_MM_INT_BIMC 111
774#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
775#define ICBID_SLAVE_MSS_INT 113
776#define ICBID_SLAVE_PCNOC_INT_0 114
777#define ICBID_SLAVE_PCNOC_INT_1 115
778#define ICBID_SLAVE_PCNOC_M_0 116
779#define ICBID_SLAVE_PCNOC_M_1 117
780#define ICBID_SLAVE_PCNOC_S_0 118
781#define ICBID_SLAVE_PCNOC_S_1 119
782#define ICBID_SLAVE_PCNOC_S_2 120
783#define ICBID_SLAVE_PCNOC_S_3 121
784#define ICBID_SLAVE_PCNOC_S_4 122
785#define ICBID_SLAVE_PCNOC_S_6 123
786#define ICBID_SLAVE_PCNOC_S_7 124
787#define ICBID_SLAVE_PCNOC_S_8 125
788#define ICBID_SLAVE_PCNOC_S_9 126
789#define ICBID_SLAVE_PRNG_XPU_CFG 127
790#define ICBID_SLAVE_QDSS_INT 128
791#define ICBID_SLAVE_RPM_XPU_CFG 129
792#define ICBID_SLAVE_SNOC_INT_0 130
793#define ICBID_SLAVE_SNOC_INT_1 131
794#define ICBID_SLAVE_SNOC_INT_BIMC 132
795#define ICBID_SLAVE_TCU 133
796#define ICBID_SLAVE_BIMC_INT_0 134
797#define ICBID_SLAVE_BIMC_INT_1 135
798#define ICBID_SLAVE_RICA_CFG 136
799#define ICBID_SLAVE_SNOC_BIMC_2 137
800#define ICBID_SLAVE_BIMC_SNOC_1 138
801#define ICBID_SLAVE_PNOC_A1NOC 139
802#define ICBID_SLAVE_SNOC_VMEM 140
803#define ICBID_SLAVE_A0NOC_SNOC 141
804#define ICBID_SLAVE_A1NOC_SNOC 142
805#define ICBID_SLAVE_A2NOC_SNOC 143
806#define ICBID_SLAVE_A0NOC_CFG 144
807#define ICBID_SLAVE_A0NOC_MPU_CFG 145
808#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
809#define ICBID_SLAVE_A1NOC_CFG 147
810#define ICBID_SLAVE_A1NOC_MPU_CFG 148
811#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
812#define ICBID_SLAVE_A2NOC_CFG 150
813#define ICBID_SLAVE_A2NOC_MPU_CFG 151
814#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
815#define ICBID_SLAVE_AHB2PHY 153
816#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
817#define ICBID_SLAVE_DCC_CFG 155
818#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
819#define ICBID_SLAVE_DSA_CFG 157
820#define ICBID_SLAVE_DSA_MPU_CFG 158
821#define ICBID_SLAVE_SSC_MPU_CFG 159
822#define ICBID_SLAVE_HMSS_L3 160
823#define ICBID_SLAVE_LPASS_SMMU_CFG 161
824#define ICBID_SLAVE_MMAGIC_CFG 162
825#define ICBID_SLAVE_PCIE20_AHB2PHY 163
826#define ICBID_SLAVE_PCIE_2 164
827#define ICBID_SLAVE_PCIE_2_CFG 165
828#define ICBID_SLAVE_PIMEM 166
829#define ICBID_SLAVE_PIMEM_CFG 167
830#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
831#define ICBID_SLAVE_RBCPR_CX 169
832#define ICBID_SLAVE_RBCPR_MX 170
833#define ICBID_SLAVE_SMMU_CPP_CFG 171
834#define ICBID_SLAVE_SMMU_JPEG_CFG 172
835#define ICBID_SLAVE_SMMU_MDP_CFG 173
836#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
837#define ICBID_SLAVE_SMMU_VENUS_CFG 175
838#define ICBID_SLAVE_SMMU_VFE_CFG 176
839#define ICBID_SLAVE_SSC_CFG 177
840#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
841#define ICBID_SLAVE_VMEM 179
842#define ICBID_SLAVE_VMEM_CFG 180
843#define ICBID_SLAVE_QDSS_MPU_CFG 181
844#define ICBID_SLAVE_USB3_PHY_CFG 182
845#define ICBID_SLAVE_IPA_CFG 183
846#define ICBID_SLAVE_PCNOC_INT_2 184
847#define ICBID_SLAVE_PCNOC_INT_3 185
848#define ICBID_SLAVE_PCNOC_INT_4 186
849#define ICBID_SLAVE_PCNOC_INT_5 187
850#define ICBID_SLAVE_PCNOC_INT_6 188
851#define ICBID_SLAVE_PCNOC_S_5 189
852#define ICBID_SLAVE_QSPI 190
853#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
854#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
855#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
856#define ICBID_SLAVE_MSS_MPU_CFG 194
857#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
858#define ICBID_SLAVE_SKL 196
859#define ICBID_SLAVE_SNOC_INT_2 197
860#define ICBID_SLAVE_SMMNOC_BIMC 198
861#define ICBID_SLAVE_CRVIRT_A1NOC 199
862#define ICBID_SLAVE_SGMII 200
863#define ICBID_SLAVE_QHS4_APPS 201
864#define ICBID_SLAVE_BIMC_PCNOC 202
865#define ICBID_SLAVE_PCNOC_BIMC_1 203
866#define ICBID_SLAVE_SPMI_FETCHER 204
867#define ICBID_SLAVE_MMSS_SMMU_CFG 205
868#define ICBID_SLAVE_WLAN 206
869#define ICBID_SLAVE_CRVIRT_A2NOC 207
870#define ICBID_SLAVE_CNOC_A2NOC 208
871#define ICBID_SLAVE_GLM 209
872#define ICBID_SLAVE_GNOC_BIMC 210
873#define ICBID_SLAVE_GNOC_SNOC 211
874#define ICBID_SLAVE_QM_CFG 212
875#define ICBID_SLAVE_TLMM_EAST 213
876#define ICBID_SLAVE_TLMM_NORTH 214
877#define ICBID_SLAVE_TLMM_WEST 215
878#define ICBID_SLAVE_LPASS_TCM 216
879#define ICBID_SLAVE_TLMM_SOUTH 217
880#define ICBID_SLAVE_TLMM_CENTER 218
881#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219
882#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220
883#define ICBID_SLAVE_CDSP 221
884#define ICBID_SLAVE_CDSP_SMMU_CFG 222
885#define ICBID_SLAVE_LPASS_MPU_CFG 223
886#define ICBID_SLAVE_CSI_PHY_CFG 224
887#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 04:18:53 -0400