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authorJayachandran C <jnair@caviumnetworks.com>2017-10-10 02:27:55 -0400
committerWolfram Sang <wsa@the-dreams.de>2017-10-17 17:53:16 -0400
commitc347b8fc22b21899154cc153a4951aaf226b4e1a (patch)
tree2dd182ae80e703a6b3b53889099c0beab3969e70
parent1977dbefe92c0baefefb62927df6e3908af8c453 (diff)
i2c: xlp9xx: Get clock frequency with clk API
Get the input clock frequency to the controller from the linux clk API, if it is available. This allows us to pass in the block input frequency either from ACPI (using APD) or from device tree. The old hardcoded frequency is used as default for backwards compatibility. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Signed-off-by: Kamlakant Patel <kamlakant.patel@cavium.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
-rw-r--r--drivers/i2c/busses/i2c-xlp9xx.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xlp9xx.c
index 6b106e94bc09..f0bef2d5306c 100644
--- a/drivers/i2c/busses/i2c-xlp9xx.c
+++ b/drivers/i2c/busses/i2c-xlp9xx.c
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include <linux/acpi.h> 9#include <linux/acpi.h>
10#include <linux/clk.h>
10#include <linux/completion.h> 11#include <linux/completion.h>
11#include <linux/i2c.h> 12#include <linux/i2c.h>
12#include <linux/init.h> 13#include <linux/init.h>
@@ -84,6 +85,7 @@ struct xlp9xx_i2c_dev {
84 u32 __iomem *base; 85 u32 __iomem *base;
85 u32 msg_buf_remaining; 86 u32 msg_buf_remaining;
86 u32 msg_len; 87 u32 msg_len;
88 u32 ip_clk_hz;
87 u32 clk_hz; 89 u32 clk_hz;
88 u32 msg_err; 90 u32 msg_err;
89 u8 *msg_buf; 91 u8 *msg_buf;
@@ -213,7 +215,7 @@ static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
213 * The controller uses 5 * SCL clock internally. 215 * The controller uses 5 * SCL clock internally.
214 * So prescale value should be divided by 5. 216 * So prescale value should be divided by 5.
215 */ 217 */
216 prescale = DIV_ROUND_UP(XLP9XX_I2C_IP_CLK_FREQ, priv->clk_hz); 218 prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
217 prescale = ((prescale - 8) / 5) - 1; 219 prescale = ((prescale - 8) / 5) - 1;
218 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST); 220 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
219 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN | 221 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
@@ -342,9 +344,19 @@ static const struct i2c_algorithm xlp9xx_i2c_algo = {
342static int xlp9xx_i2c_get_frequency(struct platform_device *pdev, 344static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
343 struct xlp9xx_i2c_dev *priv) 345 struct xlp9xx_i2c_dev *priv)
344{ 346{
347 struct clk *clk;
345 u32 freq; 348 u32 freq;
346 int err; 349 int err;
347 350
351 clk = devm_clk_get(&pdev->dev, NULL);
352 if (IS_ERR(clk)) {
353 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
354 dev_dbg(&pdev->dev, "using default input frequency %u\n",
355 priv->ip_clk_hz);
356 } else {
357 priv->ip_clk_hz = clk_get_rate(clk);
358 }
359
348 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq); 360 err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
349 if (err) { 361 if (err) {
350 freq = XLP9XX_I2C_DEFAULT_FREQ; 362 freq = XLP9XX_I2C_DEFAULT_FREQ;