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authorAndrey Smirnov <andrew.smirnov@gmail.com>2019-04-14 20:46:29 -0400
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-05-01 06:35:47 -0400
commitc2c708bc1dbf9655211d3843e2f36c7951059cf0 (patch)
treefc89fc9794bf6655c205f355b2a4f2d45942b958
parent3ca4133253a7ff37e56b3b00f1e03c3e7d20ea89 (diff)
PCI: imx6: Simplify pcie_phy_poll_ack()
Simplify pcie_phy_poll_ack() by incorporating shifting into constant definition and convert the code to use 'bool'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 669e01353026..3fd084357488 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -112,7 +112,7 @@ struct imx6_pcie {
112#define PCIE_PHY_CTRL_RD BIT(19) 112#define PCIE_PHY_CTRL_RD BIT(19)
113 113
114#define PCIE_PHY_STAT (PL_OFFSET + 0x110) 114#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
115#define PCIE_PHY_STAT_ACK_LOC 16 115#define PCIE_PHY_STAT_ACK BIT(16)
116 116
117#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 117#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
118 118
@@ -151,16 +151,16 @@ struct imx6_pcie {
151#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 151#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
152#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 152#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
153 153
154static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) 154static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
155{ 155{
156 struct dw_pcie *pci = imx6_pcie->pci; 156 struct dw_pcie *pci = imx6_pcie->pci;
157 u32 val; 157 bool val;
158 u32 max_iterations = 10; 158 u32 max_iterations = 10;
159 u32 wait_counter = 0; 159 u32 wait_counter = 0;
160 160
161 do { 161 do {
162 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 162 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
163 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 163 PCIE_PHY_STAT_ACK;
164 wait_counter++; 164 wait_counter++;
165 165
166 if (val == exp_val) 166 if (val == exp_val)
@@ -184,14 +184,14 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
184 val |= PCIE_PHY_CTRL_CAP_ADR; 184 val |= PCIE_PHY_CTRL_CAP_ADR;
185 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 185 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
186 186
187 ret = pcie_phy_poll_ack(imx6_pcie, 1); 187 ret = pcie_phy_poll_ack(imx6_pcie, true);
188 if (ret) 188 if (ret)
189 return ret; 189 return ret;
190 190
191 val = PCIE_PHY_CTRL_DATA(addr); 191 val = PCIE_PHY_CTRL_DATA(addr);
192 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 192 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
193 193
194 return pcie_phy_poll_ack(imx6_pcie, 0); 194 return pcie_phy_poll_ack(imx6_pcie, false);
195} 195}
196 196
197/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 197/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
@@ -209,7 +209,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
209 phy_ctl = PCIE_PHY_CTRL_RD; 209 phy_ctl = PCIE_PHY_CTRL_RD;
210 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 210 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
211 211
212 ret = pcie_phy_poll_ack(imx6_pcie, 1); 212 ret = pcie_phy_poll_ack(imx6_pcie, true);
213 if (ret) 213 if (ret)
214 return ret; 214 return ret;
215 215
@@ -219,7 +219,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
219 /* deassert Read signal */ 219 /* deassert Read signal */
220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
221 221
222 return pcie_phy_poll_ack(imx6_pcie, 0); 222 return pcie_phy_poll_ack(imx6_pcie, false);
223} 223}
224 224
225static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) 225static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
@@ -241,7 +241,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
241 var |= PCIE_PHY_CTRL_CAP_DAT; 241 var |= PCIE_PHY_CTRL_CAP_DAT;
242 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 242 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
243 243
244 ret = pcie_phy_poll_ack(imx6_pcie, 1); 244 ret = pcie_phy_poll_ack(imx6_pcie, true);
245 if (ret) 245 if (ret)
246 return ret; 246 return ret;
247 247
@@ -250,7 +250,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
250 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 250 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
251 251
252 /* wait for ack de-assertion */ 252 /* wait for ack de-assertion */
253 ret = pcie_phy_poll_ack(imx6_pcie, 0); 253 ret = pcie_phy_poll_ack(imx6_pcie, false);
254 if (ret) 254 if (ret)
255 return ret; 255 return ret;
256 256
@@ -259,7 +259,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
259 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 259 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
260 260
261 /* wait for ack */ 261 /* wait for ack */
262 ret = pcie_phy_poll_ack(imx6_pcie, 1); 262 ret = pcie_phy_poll_ack(imx6_pcie, true);
263 if (ret) 263 if (ret)
264 return ret; 264 return ret;
265 265
@@ -268,7 +268,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
268 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 268 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
269 269
270 /* wait for ack de-assertion */ 270 /* wait for ack de-assertion */
271 ret = pcie_phy_poll_ack(imx6_pcie, 0); 271 ret = pcie_phy_poll_ack(imx6_pcie, false);
272 if (ret) 272 if (ret)
273 return ret; 273 return ret;
274 274