diff options
author | Archit Taneja <architt@codeaurora.org> | 2017-03-23 06:28:11 -0400 |
---|---|---|
committer | Rob Clark <robdclark@gmail.com> | 2017-04-08 06:59:35 -0400 |
commit | c26b4f6cfb2774d13f9ae41cbaaf30f30ac417c6 (patch) | |
tree | 5f600ab5e2126e131141f325a89e5bbab93dda24 | |
parent | 7a10ee9b579e04241f981d8e237124aa8762c4c4 (diff) |
drm/msm/mdp5: Configure 'right' hwpipe
Now that we have a right hwpipe in mdp5_plane_state, configure it
mdp5_plane_mode_set(). The only parameters that vary between the
left and right hwpipes are the src_w, src_img_w, src_x and crtc_x
as we just even chop the fb into left and right halves.
Add a mdp5_plane_right_pipe() which will be used by the crtc code
to set up LM stages.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r-- | drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 46 |
2 files changed, 46 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 5653917bcc9d..8bdb7ee4983b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | |||
@@ -275,6 +275,7 @@ void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms); | |||
275 | 275 | ||
276 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane); | 276 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane); |
277 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane); | 277 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane); |
278 | enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane); | ||
278 | struct drm_plane *mdp5_plane_init(struct drm_device *dev, | 279 | struct drm_plane *mdp5_plane_init(struct drm_device *dev, |
279 | enum drm_plane_type type); | 280 | enum drm_plane_type type); |
280 | 281 | ||
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c index caedb9faeae2..a38c5fe6cc19 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | |||
@@ -881,6 +881,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, | |||
881 | struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; | 881 | struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; |
882 | struct mdp5_kms *mdp5_kms = get_kms(plane); | 882 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
883 | enum mdp5_pipe pipe = hwpipe->pipe; | 883 | enum mdp5_pipe pipe = hwpipe->pipe; |
884 | struct mdp5_hw_pipe *right_hwpipe; | ||
884 | const struct mdp_format *format; | 885 | const struct mdp_format *format; |
885 | uint32_t nplanes, config = 0; | 886 | uint32_t nplanes, config = 0; |
886 | struct phase_step step = { 0 }; | 887 | struct phase_step step = { 0 }; |
@@ -894,6 +895,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, | |||
894 | uint32_t src_x, src_y; | 895 | uint32_t src_x, src_y; |
895 | uint32_t src_w, src_h; | 896 | uint32_t src_w, src_h; |
896 | uint32_t src_img_w, src_img_h; | 897 | uint32_t src_img_w, src_img_h; |
898 | uint32_t src_x_r; | ||
899 | int crtc_x_r; | ||
897 | unsigned long flags; | 900 | unsigned long flags; |
898 | int ret; | 901 | int ret; |
899 | 902 | ||
@@ -929,6 +932,21 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, | |||
929 | fb->base.id, src_x, src_y, src_w, src_h, | 932 | fb->base.id, src_x, src_y, src_w, src_h, |
930 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); | 933 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); |
931 | 934 | ||
935 | right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; | ||
936 | if (right_hwpipe) { | ||
937 | /* | ||
938 | * if the plane comprises of 2 hw pipes, assume that the width | ||
939 | * is split equally across them. The only parameters that varies | ||
940 | * between the 2 pipes are src_x and crtc_x | ||
941 | */ | ||
942 | crtc_w /= 2; | ||
943 | src_w /= 2; | ||
944 | src_img_w /= 2; | ||
945 | |||
946 | crtc_x_r = crtc_x + crtc_w; | ||
947 | src_x_r = src_x + src_w; | ||
948 | } | ||
949 | |||
932 | ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); | 950 | ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); |
933 | if (ret) | 951 | if (ret) |
934 | return ret; | 952 | return ret; |
@@ -965,6 +983,12 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, | |||
965 | crtc_x, crtc_y, crtc_w, crtc_h, | 983 | crtc_x, crtc_y, crtc_w, crtc_h, |
966 | src_img_w, src_img_h, | 984 | src_img_w, src_img_h, |
967 | src_x, src_y, src_w, src_h); | 985 | src_x, src_y, src_w, src_h); |
986 | if (right_hwpipe) | ||
987 | mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, | ||
988 | config, hdecm, vdecm, hflip, vflip, | ||
989 | crtc_x_r, crtc_y, crtc_w, crtc_h, | ||
990 | src_img_w, src_img_h, | ||
991 | src_x_r, src_y, src_w, src_h); | ||
968 | 992 | ||
969 | spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); | 993 | spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); |
970 | 994 | ||
@@ -1051,6 +1075,10 @@ slow: | |||
1051 | src_x, src_y, src_w, src_h, ctx); | 1075 | src_x, src_y, src_w, src_h, ctx); |
1052 | } | 1076 | } |
1053 | 1077 | ||
1078 | /* | ||
1079 | * Use this func and the one below only after the atomic state has been | ||
1080 | * successfully swapped | ||
1081 | */ | ||
1054 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) | 1082 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) |
1055 | { | 1083 | { |
1056 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); | 1084 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); |
@@ -1061,14 +1089,30 @@ enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) | |||
1061 | return pstate->hwpipe->pipe; | 1089 | return pstate->hwpipe->pipe; |
1062 | } | 1090 | } |
1063 | 1091 | ||
1092 | enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) | ||
1093 | { | ||
1094 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); | ||
1095 | |||
1096 | if (!pstate->r_hwpipe) | ||
1097 | return SSPP_NONE; | ||
1098 | |||
1099 | return pstate->r_hwpipe->pipe; | ||
1100 | } | ||
1101 | |||
1064 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane) | 1102 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane) |
1065 | { | 1103 | { |
1066 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); | 1104 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); |
1105 | u32 mask; | ||
1067 | 1106 | ||
1068 | if (WARN_ON(!pstate->hwpipe)) | 1107 | if (WARN_ON(!pstate->hwpipe)) |
1069 | return 0; | 1108 | return 0; |
1070 | 1109 | ||
1071 | return pstate->hwpipe->flush_mask; | 1110 | mask = pstate->hwpipe->flush_mask; |
1111 | |||
1112 | if (pstate->r_hwpipe) | ||
1113 | mask |= pstate->r_hwpipe->flush_mask; | ||
1114 | |||
1115 | return mask; | ||
1072 | } | 1116 | } |
1073 | 1117 | ||
1074 | /* initialize plane */ | 1118 | /* initialize plane */ |