drm/amd/pp: Delete unnecessary function argument

in populate_single_graphic_level for smu7

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5 files changed, 8 insertions, 18 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 61dbbf19fed9..6cdaed06da0b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -411,8 +411,7 @@ static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
 }
 
 static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-                uint32_t clock, uint16_t sclk_al_threshold,
-                struct SMU7_Discrete_GraphicsLevel *level)
+                uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)
 {
         int result;
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -438,7 +437,7 @@ static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                                 clock,
                                 &level->MinVddcPhases);
 
-        level->ActivityLevel = sclk_al_threshold;
+        level->ActivityLevel = data->current_profile_setting.sclk_activity;
         level->CcPwrDynRm = 0;
         level->CcPwrDynRm1 = 0;
         level->EnabledForActivity = 0;
@@ -492,7 +491,6 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = ci_populate_single_graphic_level(hwmgr,
                                 dpm_table->sclk_table.dpm_levels[i].value,
-                                data->current_profile_setting.sclk_activity,
                                 &levels[i]);
                 if (result)
                         return result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 1d0bc6632217..9d5ccdbc391d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -968,8 +968,7 @@ static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 }
 
 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-                uint32_t clock, uint16_t sclk_al_threshold,
-                struct SMU73_Discrete_GraphicsLevel *level)
+                uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)
 {
         int result;
         /* PP_Clocks minClocks; */
@@ -996,7 +995,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                         return result);
 
         level->SclkFrequency = clock;
-        level->ActivityLevel = sclk_al_threshold;
+        level->ActivityLevel = data->current_profile_setting.sclk_activity;
         level->CcPwrDynRm = 0;
         level->CcPwrDynRm1 = 0;
         level->EnabledForActivity = 0;
@@ -1059,7 +1058,6 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = fiji_populate_single_graphic_level(hwmgr,
                                 dpm_table->sclk_table.dpm_levels[i].value,
-                                data->current_profile_setting.sclk_activity,
                                 &levels[i]);
                 if (result)
                         return result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index bf58a684d624..11aeb150a97f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -894,7 +894,6 @@ static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
 
 static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                                                 uint32_t engine_clock,
-                                uint16_t sclk_activity_level_threshold,
                                 SMU71_Discrete_GraphicsLevel *graphic_level)
 {
         int result;
@@ -920,7 +919,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                                 &graphic_level->MinVddcPhases);
 
         /* Indicates maximum activity level for this performance level. 50% for now*/
-        graphic_level->ActivityLevel = sclk_activity_level_threshold;
+        graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
 
         graphic_level->CcPwrDynRm = 0;
         graphic_level->CcPwrDynRm1 = 0;
@@ -985,7 +984,6 @@ static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = iceland_populate_single_graphic_level(hwmgr,
                                         dpm_table->sclk_table.dpm_levels[i].value,
-                                        data->current_profile_setting.sclk_activity,
                                         &(smu_data->smc_state_table.GraphicsLevel[i]));
                 if (result != 0)
                         return result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index d2f8e34e0a4e..bfb2c85d3c60 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -934,8 +934,7 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 }
 
 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-                uint32_t clock, uint16_t sclk_al_threshold,
-                struct SMU74_Discrete_GraphicsLevel *level)
+                uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
 {
         int result;
         /* PP_Clocks minClocks; */
@@ -962,7 +961,7 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                         "can not find VDDC voltage value for "
                         "VDDC engine clock dependency table",
                         return result);
-        level->ActivityLevel = sclk_al_threshold;
+        level->ActivityLevel = data->current_profile_setting.sclk_activity;
 
         level->CcPwrDynRm = 0;
         level->CcPwrDynRm1 = 0;
@@ -1033,7 +1032,6 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 
                 result = polaris10_populate_single_graphic_level(hwmgr,
                                 dpm_table->sclk_table.dpm_levels[i].value,
-                                hw_data->current_profile_setting.sclk_activity,
                                 &(smu_data->smc_state_table.GraphicsLevel[i]));
                 if (result)
                         return result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 70888478533f..748d98528c07 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -608,7 +608,6 @@ static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 
 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
                                                 uint32_t engine_clock,
-                                uint16_t sclk_activity_level_threshold,
                                 SMU72_Discrete_GraphicsLevel *graphic_level)
 {
         int result;
@@ -636,7 +635,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
         /* SCLK frequency in units of 10KHz*/
         graphic_level->SclkFrequency = engine_clock;
         /* Indicates maximum activity level for this performance level. 50% for now*/
-        graphic_level->ActivityLevel = sclk_activity_level_threshold;
+        graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
 
         graphic_level->CcPwrDynRm = 0;
         graphic_level->CcPwrDynRm1 = 0;
@@ -704,7 +703,6 @@ static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
         for (i = 0; i < dpm_table->sclk_table.count; i++) {
                 result = tonga_populate_single_graphic_level(hwmgr,
                                         dpm_table->sclk_table.dpm_levels[i].value,
-                                        data->current_profile_setting.sclk_activity,
                                         &(smu_data->smc_state_table.GraphicsLevel[i]));
                 if (result != 0)
                         return result;