diff options
author | Manish Dusane <manish.dusane@qlogic.com> | 2013-03-07 05:43:07 -0500 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2013-04-10 14:31:01 -0400 |
commit | c18b78ede52d2ac8c664449bccaf36753a3c419b (patch) | |
tree | f2a22030a404b1c95f0fc4db53e53c0f852837fa | |
parent | 27db682bf07fdc105af38827dbbd67d6f0a4ae04 (diff) |
[SCSI] qla4xxx: Take E-port out of reset before disabling pause frames
Problem Description:
Disabling pause frames might cause hardware wedging needing a power cycle.
This might happen if the Eport is not initialized and is in reset.
Solution:
Before disabling pause frames ensure that eport is out of reset.
Signed-off-by: Manish Dusane <manish.dusane@qlogic.com>
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_83xx.c | 28 | ||||
-rw-r--r-- | drivers/scsi/qla4xxx/ql4_83xx.h | 10 |
2 files changed, 38 insertions, 0 deletions
diff --git a/drivers/scsi/qla4xxx/ql4_83xx.c b/drivers/scsi/qla4xxx/ql4_83xx.c index 5d8fe4f75650..d607eb8e24cb 100644 --- a/drivers/scsi/qla4xxx/ql4_83xx.c +++ b/drivers/scsi/qla4xxx/ql4_83xx.c | |||
@@ -1629,9 +1629,37 @@ static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha) | |||
1629 | ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n"); | 1629 | ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n"); |
1630 | } | 1630 | } |
1631 | 1631 | ||
1632 | /** | ||
1633 | * qla4_83xx_eport_init - Initialize EPort. | ||
1634 | * @ha: Pointer to host adapter structure. | ||
1635 | * | ||
1636 | * If EPort hardware is in reset state before disabling pause, there would be | ||
1637 | * serious hardware wedging issues. To prevent this perform eport init everytime | ||
1638 | * before disabling pause frames. | ||
1639 | **/ | ||
1640 | static void qla4_83xx_eport_init(struct scsi_qla_host *ha) | ||
1641 | { | ||
1642 | /* Clear the 8 registers */ | ||
1643 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0); | ||
1644 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0); | ||
1645 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0); | ||
1646 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0); | ||
1647 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0); | ||
1648 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0); | ||
1649 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0); | ||
1650 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0); | ||
1651 | |||
1652 | /* Write any value to Reset Control register */ | ||
1653 | qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF); | ||
1654 | |||
1655 | ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n"); | ||
1656 | } | ||
1657 | |||
1632 | void qla4_83xx_disable_pause(struct scsi_qla_host *ha) | 1658 | void qla4_83xx_disable_pause(struct scsi_qla_host *ha) |
1633 | { | 1659 | { |
1634 | ha->isp_ops->idc_lock(ha); | 1660 | ha->isp_ops->idc_lock(ha); |
1661 | /* Before disabling pause frames, ensure that eport is not in reset */ | ||
1662 | qla4_83xx_eport_init(ha); | ||
1635 | qla4_83xx_dump_pause_control_regs(ha); | 1663 | qla4_83xx_dump_pause_control_regs(ha); |
1636 | __qla4_83xx_disable_pause(ha); | 1664 | __qla4_83xx_disable_pause(ha); |
1637 | ha->isp_ops->idc_unlock(ha); | 1665 | ha->isp_ops->idc_unlock(ha); |
diff --git a/drivers/scsi/qla4xxx/ql4_83xx.h b/drivers/scsi/qla4xxx/ql4_83xx.h index 6a00f903f2a6..fab237fa32cc 100644 --- a/drivers/scsi/qla4xxx/ql4_83xx.h +++ b/drivers/scsi/qla4xxx/ql4_83xx.h | |||
@@ -55,6 +55,16 @@ | |||
55 | #define QLA83XX_SET_PAUSE_VAL 0x0 | 55 | #define QLA83XX_SET_PAUSE_VAL 0x0 |
56 | #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF | 56 | #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF |
57 | 57 | ||
58 | #define QLA83XX_RESET_CONTROL 0x28084E50 | ||
59 | #define QLA83XX_RESET_REG 0x28084E60 | ||
60 | #define QLA83XX_RESET_PORT0 0x28084E70 | ||
61 | #define QLA83XX_RESET_PORT1 0x28084E80 | ||
62 | #define QLA83XX_RESET_PORT2 0x28084E90 | ||
63 | #define QLA83XX_RESET_PORT3 0x28084EA0 | ||
64 | #define QLA83XX_RESET_SRE_SHIM 0x28084EB0 | ||
65 | #define QLA83XX_RESET_EPG_SHIM 0x28084EC0 | ||
66 | #define QLA83XX_RESET_ETHER_PCS 0x28084ED0 | ||
67 | |||
58 | /* qla_83xx_reg_tbl registers */ | 68 | /* qla_83xx_reg_tbl registers */ |
59 | #define QLA83XX_PEG_HALT_STATUS1 0x34A8 | 69 | #define QLA83XX_PEG_HALT_STATUS1 0x34A8 |
60 | #define QLA83XX_PEG_HALT_STATUS2 0x34AC | 70 | #define QLA83XX_PEG_HALT_STATUS2 0x34AC |