diff options
author | Huang Rui <ray.huang@amd.com> | 2019-06-14 04:12:51 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-25 14:54:32 -0400 |
commit | c12d410ff2932009c89289174a0eb99f25968b05 (patch) | |
tree | 1d6b2813bef0ced7f1fd9b55fc4a1578fda066d3 | |
parent | cb2a782eb8087d1bed61f58aa38fe06a693031d7 (diff) |
drm/amd/powerplay: make mmhub pg bit configured by pg_flags
The mmhub pg features enabling should be indicated by pg_flags.
Reported-by: Lijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 0c837207085e..c8e79dda7daa 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c | |||
@@ -508,7 +508,8 @@ static int nv_common_early_init(void *handle) | |||
508 | AMD_CG_SUPPORT_BIF_MGCG | | 508 | AMD_CG_SUPPORT_BIF_MGCG | |
509 | AMD_CG_SUPPORT_BIF_LS; | 509 | AMD_CG_SUPPORT_BIF_LS; |
510 | adev->pg_flags = AMD_PG_SUPPORT_VCN | | 510 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
511 | AMD_PG_SUPPORT_VCN_DPG; | 511 | AMD_PG_SUPPORT_VCN_DPG | |
512 | AMD_PG_SUPPORT_MMHUB; | ||
512 | adev->external_rev_id = adev->rev_id + 0x1; | 513 | adev->external_rev_id = adev->rev_id + 0x1; |
513 | break; | 514 | break; |
514 | default: | 515 | default: |
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index d1246981e3ac..a83b19697a6d 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c | |||
@@ -325,7 +325,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | |||
325 | | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) | 325 | | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) |
326 | | FEATURE_MASK(FEATURE_THERMAL_BIT) | 326 | | FEATURE_MASK(FEATURE_THERMAL_BIT) |
327 | | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | 327 | | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) |
328 | | FEATURE_MASK(FEATURE_MMHUB_PG_BIT) | ||
329 | | FEATURE_MASK(FEATURE_ATHUB_PG_BIT) | 328 | | FEATURE_MASK(FEATURE_ATHUB_PG_BIT) |
330 | | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | 329 | | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) |
331 | | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) | 330 | | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) |
@@ -346,6 +345,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | |||
346 | *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT); | 345 | *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT); |
347 | } | 346 | } |
348 | 347 | ||
348 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) | ||
349 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); | ||
350 | |||
349 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) | 351 | if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) |
350 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); | 352 | *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); |
351 | 353 | ||