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authorThomas Gleixner <tglx@linutronix.de>2017-10-17 02:49:37 -0400
committerThomas Gleixner <tglx@linutronix.de>2017-10-17 02:53:15 -0400
commitc0fc9b1350a317da22b310d68117b0d01cb9065e (patch)
tree0f361a7689123044f6df95d9823bff0aec941d2a
parent97d21003df3e7504c899b1701546f18ff475966f (diff)
x86/tsc: Make CONFIG_X86_TSC=n build work again
tsc_async_resets is only available when CONFIG_X86_TSC=y. So a build with CONFIG_X86_TSC=n breaks: arch/x86/kernel/tsc.o: In function `tsc_init': (.init.text+0x87b): undefined reference to `tsc_async_resets' Add a stub define for the TSC=n case. Side note: This config switch should simply be removed. Reported-by: kbuild test robot <fengguang.wu@intel.com> Fixes: 341102c3ef29 ("x86/tsc: Add option that TSC on Socket 0 being non-zero is valid") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Mike Travis <mike.travis@hpe.com>
-rw-r--r--arch/x86/include/asm/tsc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 79125f3609c4..c016167720b1 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -42,7 +42,11 @@ extern unsigned long native_calibrate_tsc(void);
42extern unsigned long long native_sched_clock_from_tsc(u64 tsc); 42extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
43 43
44extern int tsc_clocksource_reliable; 44extern int tsc_clocksource_reliable;
45#ifdef CONFIG_X86_TSC
45extern bool tsc_async_resets; 46extern bool tsc_async_resets;
47#else
48# define tsc_async_resets false
49#endif
46 50
47/* 51/*
48 * Boot-time check whether the TSCs are synchronized across 52 * Boot-time check whether the TSCs are synchronized across