drm/i915/bdw: Sampler power bypass disable

BDW-A workaround.

BDW Bug #1899812

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ffd103a5d472..1d557291fb28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5009,6 +5009,7 @@
 
 #define HALF_SLICE_CHICKEN3             0xe184
 #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1<<8)
+#define   GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
 
 #define G4X_AUD_VID_DID                 (dev_priv->info->display_mmio_offset + 0x62020)
 #define INTEL_AUDIO_DEVCL               0x808629FB
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e036ba06be99..7e0039e8c2d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5290,6 +5290,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
              "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
         I915_WRITE(HALF_SLICE_CHICKEN3,
                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
+        I915_WRITE(HALF_SLICE_CHICKEN3,
+                   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
         /* WaSwitchSolVfFArbitrationPriority */