drm/amdgpu: split athub clock gating from mmhub

Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5 files changed, 154 insertions, 44 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 8afa0bceb460..464bfe52745f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -154,6 +154,7 @@ amdgpu-y += \
 
 # add ATHUB block
 amdgpu-y += \
+        athub_v1_0.o \
         athub_v2_0.o
 
 # add amdkfd interfaces
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
new file mode 100644
index 000000000000..d9cc746af5e6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "athub_v1_0.h"
+
+#include "athub/athub_1_0_offset.h"
+#include "athub/athub_1_0_sh_mask.h"
+#include "vega10_enum.h"
+
+#include "soc15_common.h"
+
+static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                                   bool enable)
+{
+        uint32_t def, data;
+
+        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+                data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+        else
+                data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+
+        if (def != data)
+                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+                                                  bool enable)
+{
+        uint32_t def, data;
+
+        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+            (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+                data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+        else
+                data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+
+        if(def != data)
+                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
+                               enum amd_clockgating_state state)
+{
+        if (amdgpu_sriov_vf(adev))
+                return 0;
+
+        switch (adev->asic_type) {
+        case CHIP_VEGA10:
+        case CHIP_VEGA12:
+        case CHIP_VEGA20:
+        case CHIP_RAVEN:
+                athub_update_medium_grain_clock_gating(adev,
+                                state == AMD_CG_STATE_GATE ? true : false);
+                athub_update_medium_grain_light_sleep(adev,
+                                state == AMD_CG_STATE_GATE ? true : false);
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+        int data;
+
+        if (amdgpu_sriov_vf(adev))
+                *flags = 0;
+
+        /* AMD_CG_SUPPORT_ATHUB_MGCG */
+        data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+        if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+                *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
+
+        /* AMD_CG_SUPPORT_ATHUB_LS */
+        if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
+                *flags |= AMD_CG_SUPPORT_ATHUB_LS;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
new file mode 100644
index 000000000000..b279af59e34f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __ATHUB_V1_0_H__
+#define __ATHUB_V1_0_H__
+
+int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
+                               enum amd_clockgating_state state);
+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7206e55dfb55..cf0241ee4e6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -47,6 +47,7 @@
 
 #include "gfxhub_v1_0.h"
 #include "mmhub_v1_0.h"
+#include "athub_v1_0.h"
 #include "gfxhub_v1_1.h"
 #include "mmhub_v9_4.h"
 #include "umc_v6_1.h"
@@ -1470,7 +1471,11 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
         if (adev->asic_type == CHIP_ARCTURUS)
                 return 0;
 
-        return mmhub_v1_0_set_clockgating(adev, state);
+        mmhub_v1_0_set_clockgating(adev, state);
+
+        athub_v1_0_set_clockgating(adev, state);
+
+        return 0;
 }
 
 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
@@ -1481,6 +1486,8 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
                 return;
 
         mmhub_v1_0_get_clockgating(adev, flags);
+
+        athub_v1_0_get_clockgating(adev, flags);
 }
 
 static int gmc_v9_0_set_powergating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index fa961e0b6f2f..c3a98d964ce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -26,8 +26,6 @@
 #include "mmhub/mmhub_1_0_offset.h"
 #include "mmhub/mmhub_1_0_sh_mask.h"
 #include "mmhub/mmhub_1_0_default.h"
-#include "athub/athub_1_0_offset.h"
-#include "athub/athub_1_0_sh_mask.h"
 #include "vega10_enum.h"
 
 #include "soc15_common.h"
@@ -491,22 +489,6 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 }
 
-static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
-                                                   bool enable)
-{
-        uint32_t def, data;
-
-        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
-
-        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
-                data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
-        else
-                data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
-
-        if (def != data)
-                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
-}
-
 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
                                                        bool enable)
 {
@@ -523,23 +505,6 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 }
 
-static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
-                                                  bool enable)
-{
-        uint32_t def, data;
-
-        def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
-
-        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
-            (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
-                data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
-        else
-                data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
-
-        if(def != data)
-                WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
-}
-
 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
                                enum amd_clockgating_state state)
 {
@@ -553,12 +518,8 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
         case CHIP_RAVEN:
                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
                                 state == AMD_CG_STATE_GATE ? true : false);
-                athub_update_medium_grain_clock_gating(adev,
-                                state == AMD_CG_STATE_GATE ? true : false);
                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
                                 state == AMD_CG_STATE_GATE ? true : false);
-                athub_update_medium_grain_light_sleep(adev,
-                                state == AMD_CG_STATE_GATE ? true : false);
                 break;
         default:
                 break;
@@ -569,18 +530,26 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 
 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
-        int data;
+        int data, data1;
 
         if (amdgpu_sriov_vf(adev))
                 *flags = 0;
 
+        data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
+
+        data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+
         /* AMD_CG_SUPPORT_MC_MGCG */
-        data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
-        if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+        if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
+            !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 
         /* AMD_CG_SUPPORT_MC_LS */
-        data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
                 *flags |= AMD_CG_SUPPORT_MC_LS;
 }