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authorPeng Fan <van.freenix@gmail.com>2016-07-04 05:38:22 -0400
committerWill Deacon <will.deacon@arm.com>2016-07-06 13:31:51 -0400
commitbee140044579fbfdad5fd98717c0405d7b492226 (patch)
tree3722b8a6f2c838e577b0cdb60e45a41f0f6834e8
parent7c6d90e2bb1a98b86d73b9e8ab4d97ed5507e37c (diff)
iommu/arm-smmu: Use devm_request_irq and devm_free_irq
Use devm_request_irq to simplify error handling path, when probe smmu device. Also devm_{request|free}_irq when init or destroy domain context. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--drivers/iommu/arm-smmu.c24
1 files changed, 10 insertions, 14 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ab365ec6184d..4f49fe29f202 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -987,8 +987,8 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
987 * handler seeing a half-initialised domain state. 987 * handler seeing a half-initialised domain state.
988 */ 988 */
989 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; 989 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
990 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, 990 ret = devm_request_irq(smmu->dev, irq, arm_smmu_context_fault,
991 "arm-smmu-context-fault", domain); 991 IRQF_SHARED, "arm-smmu-context-fault", domain);
992 if (ret < 0) { 992 if (ret < 0) {
993 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", 993 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
994 cfg->irptndx, irq); 994 cfg->irptndx, irq);
@@ -1028,7 +1028,7 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
1028 1028
1029 if (cfg->irptndx != INVALID_IRPTNDX) { 1029 if (cfg->irptndx != INVALID_IRPTNDX) {
1030 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; 1030 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
1031 free_irq(irq, domain); 1031 devm_free_irq(smmu->dev, irq, domain);
1032 } 1032 }
1033 1033
1034 free_io_pgtable_ops(smmu_domain->pgtbl_ops); 1034 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
@@ -1986,15 +1986,15 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1986 } 1986 }
1987 1987
1988 for (i = 0; i < smmu->num_global_irqs; ++i) { 1988 for (i = 0; i < smmu->num_global_irqs; ++i) {
1989 err = request_irq(smmu->irqs[i], 1989 err = devm_request_irq(smmu->dev, smmu->irqs[i],
1990 arm_smmu_global_fault, 1990 arm_smmu_global_fault,
1991 IRQF_SHARED, 1991 IRQF_SHARED,
1992 "arm-smmu global fault", 1992 "arm-smmu global fault",
1993 smmu); 1993 smmu);
1994 if (err) { 1994 if (err) {
1995 dev_err(dev, "failed to request global IRQ %d (%u)\n", 1995 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1996 i, smmu->irqs[i]); 1996 i, smmu->irqs[i]);
1997 goto out_free_irqs; 1997 goto out_put_masters;
1998 } 1998 }
1999 } 1999 }
2000 2000
@@ -2006,10 +2006,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
2006 arm_smmu_device_reset(smmu); 2006 arm_smmu_device_reset(smmu);
2007 return 0; 2007 return 0;
2008 2008
2009out_free_irqs:
2010 while (i--)
2011 free_irq(smmu->irqs[i], smmu);
2012
2013out_put_masters: 2009out_put_masters:
2014 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { 2010 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2015 struct arm_smmu_master *master 2011 struct arm_smmu_master *master
@@ -2050,7 +2046,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
2050 dev_err(dev, "removing device with active domains!\n"); 2046 dev_err(dev, "removing device with active domains!\n");
2051 2047
2052 for (i = 0; i < smmu->num_global_irqs; ++i) 2048 for (i = 0; i < smmu->num_global_irqs; ++i)
2053 free_irq(smmu->irqs[i], smmu); 2049 devm_free_irq(smmu->dev, smmu->irqs[i], smmu);
2054 2050
2055 /* Turn the thing off */ 2051 /* Turn the thing off */
2056 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); 2052 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);