drm/amdgpu: fix vce3 instance handling

Need to properly handle the instances for the idle
checks and soft reset.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 42 insertions, 6 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5642b8eb92ad..f0656dfb53f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -32,8 +32,8 @@
 #include "vid.h"
 #include "vce/vce_3_0_d.h"
 #include "vce/vce_3_0_sh_mask.h"
-#include "oss/oss_2_0_d.h"
-#include "oss/oss_2_0_sh_mask.h"
+#include "oss/oss_3_0_d.h"
+#include "oss/oss_3_0_sh_mask.h"
 #include "gca/gfx_8_0_d.h"
 #include "smu/smu_7_1_2_d.h"
 #include "smu/smu_7_1_2_sh_mask.h"
@@ -426,17 +426,41 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
 static bool vce_v3_0_is_idle(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        u32 mask = 0;
+        int idx;
 
-        return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
+        for (idx = 0; idx < 2; ++idx) {
+                if (adev->vce.harvest_config & (1 << idx))
+                        continue;
+
+                if (idx == 0)
+                        mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
+                else
+                        mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
+        }
+
+        return !(RREG32(mmSRBM_STATUS2) & mask);
 }
 
 static int vce_v3_0_wait_for_idle(void *handle)
 {
         unsigned i;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        u32 mask = 0;
+        int idx;
+
+        for (idx = 0; idx < 2; ++idx) {
+                if (adev->vce.harvest_config & (1 << idx))
+                        continue;
+
+                if (idx == 0)
+                        mask |= SRBM_STATUS2__VCE0_BUSY_MASK;
+                else
+                        mask |= SRBM_STATUS2__VCE1_BUSY_MASK;
+        }
 
         for (i = 0; i < adev->usec_timeout; i++) {
-                if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
+                if (!(RREG32(mmSRBM_STATUS2) & mask))
                         return 0;
         }
         return -ETIMEDOUT;
@@ -445,9 +469,21 @@ static int vce_v3_0_wait_for_idle(void *handle)
 static int vce_v3_0_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        u32 mask = 0;
+        int idx;
+
+        for (idx = 0; idx < 2; ++idx) {
+                if (adev->vce.harvest_config & (1 << idx))
+                        continue;
 
-        WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
-                        ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
+                if (idx == 0)
+                        mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
+                else
+                        mask |= SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
+        }
+        WREG32_P(mmSRBM_SOFT_RESET, mask,
+                 ~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK |
+                   SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK));
         mdelay(5);
 
         return vce_v3_0_start(adev);