diff options
author | Arnd Bergmann <arnd@arndb.de> | 2016-09-14 18:28:52 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2016-09-14 18:28:52 -0400 |
commit | be46f95b54e00922a506d9b3ecf588cc8255d310 (patch) | |
tree | b8ca0a50850536c0c2f39ededad3e426d75ac01e | |
parent | f6b2dae76e0e138f8b4b6c375f10d2f8272982be (diff) | |
parent | 9ba63e3cc849cdaf3b675c47cc51fe35419e5117 (diff) |
Merge tag 'pxa-for-4.9' of https://github.com/rjarzmik/linux into next/soc
Pull "This is the pxa changes for v4.9 cycle" from Robert Jarzmik:
This cycle is covering :
- the removal of the legacy DMA API
This is the major contributor to the negative diffstat, as dmaengine
have taken over in this area.
- IDE subsystem defconfig fixes
- preparation for pxa25x to be device-tree compliant
- various irq related fixes
* tag 'pxa-for-4.9' of https://github.com/rjarzmik/linux:
ARM: pxa: pxa_cplds: fix interrupt handling
ARM: pxa: remove irq init from dt machines
ARM: pxa: Use kmalloc_array() in pxa_pm_init()
ARM: pxa: magician: Remove duplicated I2C pins declaration
ARM: pxa: fix GPIO double shifts
arm: trizeps4_defconfig: disable IDE subsystem
arm: pxa255-idp_defconfig: disable IDE subsystem
arm: lpda270_defconfig: disable IDE subsystem
arm: colibri_pxa270_defconfig: disable IDE subsystem
ARM: pxa: add pxa25x device-tree support
ARM: pxa: prepare pxa25x interrupts for device-tree platforms
ARM: pxa: remove platform dma code
ARM: pxa: remove devicetree boards from pxa_defconfig
24 files changed, 95 insertions, 563 deletions
diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 0b9211b2b73b..3146ad055716 100644 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig | |||
@@ -83,7 +83,6 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
83 | CONFIG_BLK_DEV_NBD=y | 83 | CONFIG_BLK_DEV_NBD=y |
84 | CONFIG_BLK_DEV_RAM=y | 84 | CONFIG_BLK_DEV_RAM=y |
85 | CONFIG_BLK_DEV_RAM_COUNT=8 | 85 | CONFIG_BLK_DEV_RAM_COUNT=8 |
86 | CONFIG_IDE=y | ||
87 | CONFIG_NETDEVICES=y | 86 | CONFIG_NETDEVICES=y |
88 | CONFIG_PHYLIB=y | 87 | CONFIG_PHYLIB=y |
89 | CONFIG_NET_ETHERNET=y | 88 | CONFIG_NET_ETHERNET=y |
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig index 1c8c9ee71d31..a9dd1e93b556 100644 --- a/arch/arm/configs/lpd270_defconfig +++ b/arch/arm/configs/lpd270_defconfig | |||
@@ -31,7 +31,6 @@ CONFIG_MTD_CFI_GEOMETRY=y | |||
31 | # CONFIG_MTD_CFI_I1 is not set | 31 | # CONFIG_MTD_CFI_I1 is not set |
32 | CONFIG_MTD_CFI_INTELEXT=y | 32 | CONFIG_MTD_CFI_INTELEXT=y |
33 | CONFIG_BLK_DEV_NBD=y | 33 | CONFIG_BLK_DEV_NBD=y |
34 | CONFIG_IDE=y | ||
35 | CONFIG_NETDEVICES=y | 34 | CONFIG_NETDEVICES=y |
36 | CONFIG_NET_ETHERNET=y | 35 | CONFIG_NET_ETHERNET=y |
37 | CONFIG_SMC91X=y | 36 | CONFIG_SMC91X=y |
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig index 917a070b4bb9..088627ad875f 100644 --- a/arch/arm/configs/pxa255-idp_defconfig +++ b/arch/arm/configs/pxa255-idp_defconfig | |||
@@ -28,7 +28,6 @@ CONFIG_MTD_CFI_GEOMETRY=y | |||
28 | # CONFIG_MTD_MAP_BANK_WIDTH_2 is not set | 28 | # CONFIG_MTD_MAP_BANK_WIDTH_2 is not set |
29 | # CONFIG_MTD_CFI_I1 is not set | 29 | # CONFIG_MTD_CFI_I1 is not set |
30 | CONFIG_MTD_CFI_INTELEXT=y | 30 | CONFIG_MTD_CFI_INTELEXT=y |
31 | CONFIG_IDE=y | ||
32 | CONFIG_NETDEVICES=y | 31 | CONFIG_NETDEVICES=y |
33 | CONFIG_NET_ETHERNET=y | 32 | CONFIG_NET_ETHERNET=y |
34 | CONFIG_SMC91X=y | 33 | CONFIG_SMC91X=y |
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index dc5517eaf09f..a016ecc0084b 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig | |||
@@ -26,8 +26,6 @@ CONFIG_PARTITION_ADVANCED=y | |||
26 | CONFIG_LDM_PARTITION=y | 26 | CONFIG_LDM_PARTITION=y |
27 | CONFIG_CMDLINE_PARTITION=y | 27 | CONFIG_CMDLINE_PARTITION=y |
28 | CONFIG_ARCH_PXA=y | 28 | CONFIG_ARCH_PXA=y |
29 | CONFIG_MACH_PXA27X_DT=y | ||
30 | CONFIG_MACH_PXA3XX_DT=y | ||
31 | CONFIG_ARCH_LUBBOCK=y | 29 | CONFIG_ARCH_LUBBOCK=y |
32 | CONFIG_MACH_MAINSTONE=y | 30 | CONFIG_MACH_MAINSTONE=y |
33 | CONFIG_MACH_ZYLONITE300=y | 31 | CONFIG_MACH_ZYLONITE300=y |
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig index 0ada29d568ec..492f7f3eb4ac 100644 --- a/arch/arm/configs/trizeps4_defconfig +++ b/arch/arm/configs/trizeps4_defconfig | |||
@@ -94,8 +94,6 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
94 | CONFIG_BLK_DEV_NBD=y | 94 | CONFIG_BLK_DEV_NBD=y |
95 | CONFIG_BLK_DEV_RAM=y | 95 | CONFIG_BLK_DEV_RAM=y |
96 | CONFIG_BLK_DEV_RAM_COUNT=8 | 96 | CONFIG_BLK_DEV_RAM_COUNT=8 |
97 | CONFIG_IDE=y | ||
98 | CONFIG_BLK_DEV_IDECS=m | ||
99 | CONFIG_SCSI=y | 97 | CONFIG_SCSI=y |
100 | CONFIG_BLK_DEV_SD=y | 98 | CONFIG_BLK_DEV_SD=y |
101 | CONFIG_CHR_DEV_SG=y | 99 | CONFIG_CHR_DEV_SG=y |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index cd894d69e766..76fbc115ec33 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
@@ -4,6 +4,17 @@ menu "Intel PXA2xx/PXA3xx Implementations" | |||
4 | 4 | ||
5 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" | 5 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" |
6 | 6 | ||
7 | config MACH_PXA25X_DT | ||
8 | bool "Support PXA25x platforms from device tree" | ||
9 | select PINCTRL | ||
10 | select POWER_SUPPLY | ||
11 | select PXA25x | ||
12 | select USE_OF | ||
13 | help | ||
14 | Include support for Marvell PXA25x based platforms using | ||
15 | the device tree. Needn't select any other machine while | ||
16 | MACH_PXA25x_DT is enabled. | ||
17 | |||
7 | config MACH_PXA27X_DT | 18 | config MACH_PXA27X_DT |
8 | bool "Support PXA27x platforms from device tree" | 19 | bool "Support PXA27x platforms from device tree" |
9 | select PINCTRL | 20 | select PINCTRL |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 2ceed407eda9..ef25dc597f30 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
@@ -19,8 +19,9 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
19 | # NOTE: keep the order of boards in accordance to their order in Kconfig | 19 | # NOTE: keep the order of boards in accordance to their order in Kconfig |
20 | 20 | ||
21 | # Device Tree support | 21 | # Device Tree support |
22 | obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o | 22 | obj-$(CONFIG_MACH_PXA25X_DT) += pxa-dt.o |
23 | obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o | 23 | obj-$(CONFIG_MACH_PXA27X_DT) += pxa-dt.o |
24 | obj-$(CONFIG_MACH_PXA3XX_DT) += pxa-dt.o | ||
24 | 25 | ||
25 | # Intel/Marvell Dev Platforms | 26 | # Intel/Marvell Dev Platforms |
26 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 27 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index d9206811be9b..c71c483f410e 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c | |||
@@ -131,16 +131,11 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm) | |||
131 | return is_resume; | 131 | return is_resume; |
132 | } | 132 | } |
133 | 133 | ||
134 | static unsigned long corgi_charger_wakeup(void) | 134 | static bool corgi_charger_wakeup(void) |
135 | { | 135 | { |
136 | unsigned long ret; | 136 | return !gpio_get_value(CORGI_GPIO_AC_IN) || |
137 | 137 | !gpio_get_value(CORGI_GPIO_KEY_INT) || | |
138 | ret = (!gpio_get_value(CORGI_GPIO_AC_IN) << GPIO_bit(CORGI_GPIO_AC_IN)) | 138 | !gpio_get_value(CORGI_GPIO_WAKEUP); |
139 | | (!gpio_get_value(CORGI_GPIO_KEY_INT) | ||
140 | << GPIO_bit(CORGI_GPIO_KEY_INT)) | ||
141 | | (!gpio_get_value(CORGI_GPIO_WAKEUP) | ||
142 | << GPIO_bit(CORGI_GPIO_WAKEUP)); | ||
143 | return ret; | ||
144 | } | 139 | } |
145 | 140 | ||
146 | unsigned long corgipm_read_devdata(int type) | 141 | unsigned long corgipm_read_devdata(int type) |
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 4a13c32fb705..04580c407276 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h | |||
@@ -54,3 +54,4 @@ extern struct platform_device pxa3xx_device_gpio; | |||
54 | extern struct platform_device pxa93x_device_gpio; | 54 | extern struct platform_device pxa93x_device_gpio; |
55 | 55 | ||
56 | void __init pxa_register_device(struct platform_device *dev, void *data); | 56 | void __init pxa_register_device(struct platform_device *dev, void *data); |
57 | void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors); | ||
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 0b1dbb54871a..75e3f611e5d8 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
@@ -33,14 +33,12 @@ extern void __init pxa26x_init_irq(void); | |||
33 | 33 | ||
34 | #define pxa27x_handle_irq ichp_handle_irq | 34 | #define pxa27x_handle_irq ichp_handle_irq |
35 | extern int __init pxa27x_clocks_init(void); | 35 | extern int __init pxa27x_clocks_init(void); |
36 | extern void __init pxa27x_dt_init_irq(void); | ||
37 | extern unsigned pxa27x_get_clk_frequency_khz(int); | 36 | extern unsigned pxa27x_get_clk_frequency_khz(int); |
38 | extern void __init pxa27x_init_irq(void); | 37 | extern void __init pxa27x_init_irq(void); |
39 | extern void __init pxa27x_map_io(void); | 38 | extern void __init pxa27x_map_io(void); |
40 | 39 | ||
41 | #define pxa3xx_handle_irq ichp_handle_irq | 40 | #define pxa3xx_handle_irq ichp_handle_irq |
42 | extern int __init pxa3xx_clocks_init(void); | 41 | extern int __init pxa3xx_clocks_init(void); |
43 | extern void __init pxa3xx_dt_init_irq(void); | ||
44 | extern void __init pxa3xx_init_irq(void); | 42 | extern void __init pxa3xx_init_irq(void); |
45 | extern void __init pxa3xx_map_io(void); | 43 | extern void __init pxa3xx_map_io(void); |
46 | 44 | ||
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 5bd55894a48d..20026bdc6b24 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h | |||
@@ -17,5 +17,4 @@ | |||
17 | /* DMA Controller Registers Definitions */ | 17 | /* DMA Controller Registers Definitions */ |
18 | #define DMAC_REGS_VIRT io_p2v(0x40000000) | 18 | #define DMAC_REGS_VIRT io_p2v(0x40000000) |
19 | 19 | ||
20 | #include <plat/dma.h> | ||
21 | #endif /* _ASM_ARCH_DMA_H */ | 20 | #endif /* _ASM_ARCH_DMA_H */ |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index abc918169367..6f8837ebbf91 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
@@ -121,10 +121,6 @@ static unsigned long magician_pin_config[] __initdata = { | |||
121 | GPIO107_GPIO, /* DS1WM_IRQ */ | 121 | GPIO107_GPIO, /* DS1WM_IRQ */ |
122 | GPIO108_GPIO, /* GSM_READY */ | 122 | GPIO108_GPIO, /* GSM_READY */ |
123 | GPIO115_GPIO, /* nPEN_IRQ */ | 123 | GPIO115_GPIO, /* nPEN_IRQ */ |
124 | |||
125 | /* I2C */ | ||
126 | GPIO117_I2C_SCL, | ||
127 | GPIO118_I2C_SDA, | ||
128 | }; | 124 | }; |
129 | 125 | ||
130 | /* | 126 | /* |
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 388463b99090..e7450fb49d24 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c | |||
@@ -104,8 +104,9 @@ static int __init pxa_pm_init(void) | |||
104 | return -EINVAL; | 104 | return -EINVAL; |
105 | } | 105 | } |
106 | 106 | ||
107 | sleep_save = kmalloc(pxa_cpu_pm_fns->save_count * sizeof(unsigned long), | 107 | sleep_save = kmalloc_array(pxa_cpu_pm_fns->save_count, |
108 | GFP_KERNEL); | 108 | sizeof(*sleep_save), |
109 | GFP_KERNEL); | ||
109 | if (!sleep_save) { | 110 | if (!sleep_save) { |
110 | printk(KERN_ERR "failed to alloc memory for pm save\n"); | 111 | printk(KERN_ERR "failed to alloc memory for pm save\n"); |
111 | return -ENOMEM; | 112 | return -ENOMEM; |
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c index f128133a8f30..aa9b255f5570 100644 --- a/arch/arm/mach-pxa/pxa-dt.c +++ b/arch/arm/mach-pxa/pxa-dt.c | |||
@@ -18,20 +18,16 @@ | |||
18 | 18 | ||
19 | #include "generic.h" | 19 | #include "generic.h" |
20 | 20 | ||
21 | #ifdef CONFIG_PXA3xx | 21 | #ifdef CONFIG_PXA25x |
22 | static const char *const pxa3xx_dt_board_compat[] __initconst = { | 22 | static const char * const pxa25x_dt_board_compat[] __initconst = { |
23 | "marvell,pxa300", | 23 | "marvell,pxa250", |
24 | "marvell,pxa310", | ||
25 | "marvell,pxa320", | ||
26 | NULL, | 24 | NULL, |
27 | }; | 25 | }; |
28 | 26 | ||
29 | DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") | 27 | DT_MACHINE_START(PXA25X_DT, "Marvell PXA25x (Device Tree Support)") |
30 | .map_io = pxa3xx_map_io, | 28 | .map_io = pxa25x_map_io, |
31 | .init_irq = pxa3xx_dt_init_irq, | ||
32 | .handle_irq = pxa3xx_handle_irq, | ||
33 | .restart = pxa_restart, | 29 | .restart = pxa_restart, |
34 | .dt_compat = pxa3xx_dt_board_compat, | 30 | .dt_compat = pxa25x_dt_board_compat, |
35 | MACHINE_END | 31 | MACHINE_END |
36 | #endif | 32 | #endif |
37 | 33 | ||
@@ -41,11 +37,24 @@ static const char * const pxa27x_dt_board_compat[] __initconst = { | |||
41 | NULL, | 37 | NULL, |
42 | }; | 38 | }; |
43 | 39 | ||
44 | DT_MACHINE_START(PXA27X_DT, "Marvell PXA2xx (Device Tree Support)") | 40 | DT_MACHINE_START(PXA27X_DT, "Marvell PXA27x (Device Tree Support)") |
45 | .map_io = pxa27x_map_io, | 41 | .map_io = pxa27x_map_io, |
46 | .init_irq = pxa27x_dt_init_irq, | ||
47 | .handle_irq = pxa27x_handle_irq, | ||
48 | .restart = pxa_restart, | 42 | .restart = pxa_restart, |
49 | .dt_compat = pxa27x_dt_board_compat, | 43 | .dt_compat = pxa27x_dt_board_compat, |
50 | MACHINE_END | 44 | MACHINE_END |
51 | #endif | 45 | #endif |
46 | |||
47 | #ifdef CONFIG_PXA3xx | ||
48 | static const char *const pxa3xx_dt_board_compat[] __initconst = { | ||
49 | "marvell,pxa300", | ||
50 | "marvell,pxa310", | ||
51 | "marvell,pxa320", | ||
52 | NULL, | ||
53 | }; | ||
54 | |||
55 | DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)") | ||
56 | .map_io = pxa3xx_map_io, | ||
57 | .restart = pxa_restart, | ||
58 | .dt_compat = pxa3xx_dt_board_compat, | ||
59 | MACHINE_END | ||
60 | #endif | ||
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 823504f48f80..12b94357fbc1 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/suspend.h> | 25 | #include <linux/suspend.h> |
26 | #include <linux/syscore_ops.h> | 26 | #include <linux/syscore_ops.h> |
27 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
28 | #include <linux/irqchip.h> | ||
28 | 29 | ||
29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
30 | #include <asm/suspend.h> | 31 | #include <asm/suspend.h> |
@@ -151,6 +152,16 @@ void __init pxa26x_init_irq(void) | |||
151 | } | 152 | } |
152 | #endif | 153 | #endif |
153 | 154 | ||
155 | static int __init __init | ||
156 | pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent) | ||
157 | { | ||
158 | pxa_dt_irq_init(pxa25x_set_wake); | ||
159 | set_handle_irq(ichp_handle_irq); | ||
160 | |||
161 | return 0; | ||
162 | } | ||
163 | IRQCHIP_DECLARE(pxa25x_intc, "marvell,pxa-intc", pxa25x_dt_init_irq); | ||
164 | |||
154 | static struct map_desc pxa25x_io_desc[] __initdata = { | 165 | static struct map_desc pxa25x_io_desc[] __initdata = { |
155 | { /* Mem Ctl */ | 166 | { /* Mem Ctl */ |
156 | .virtual = (unsigned long)SMEMC_VIRT, | 167 | .virtual = (unsigned long)SMEMC_VIRT, |
@@ -198,20 +209,17 @@ static int __init pxa25x_init(void) | |||
198 | 209 | ||
199 | reset_status = RCSR; | 210 | reset_status = RCSR; |
200 | 211 | ||
201 | if ((ret = pxa_init_dma(IRQ_DMA, 16))) | ||
202 | return ret; | ||
203 | |||
204 | pxa25x_init_pm(); | 212 | pxa25x_init_pm(); |
205 | 213 | ||
206 | register_syscore_ops(&pxa_irq_syscore_ops); | 214 | register_syscore_ops(&pxa_irq_syscore_ops); |
207 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); | 215 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); |
208 | 216 | ||
209 | pxa2xx_set_dmac_info(16, 40); | 217 | if (!of_have_populated_dt()) { |
210 | pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); | 218 | pxa2xx_set_dmac_info(16, 40); |
211 | ret = platform_add_devices(pxa25x_devices, | 219 | pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); |
212 | ARRAY_SIZE(pxa25x_devices)); | 220 | ret = platform_add_devices(pxa25x_devices, |
213 | if (ret) | 221 | ARRAY_SIZE(pxa25x_devices)); |
214 | return ret; | 222 | } |
215 | } | 223 | } |
216 | 224 | ||
217 | return ret; | 225 | return ret; |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 2eaa341dd3f8..c0185c5c5a08 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/irqchip.h> | ||
19 | #include <linux/suspend.h> | 20 | #include <linux/suspend.h> |
20 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
21 | #include <linux/syscore_ops.h> | 22 | #include <linux/syscore_ops.h> |
@@ -233,11 +234,15 @@ void __init pxa27x_init_irq(void) | |||
233 | pxa_init_irq(34, pxa27x_set_wake); | 234 | pxa_init_irq(34, pxa27x_set_wake); |
234 | } | 235 | } |
235 | 236 | ||
236 | void __init pxa27x_dt_init_irq(void) | 237 | static int __init |
238 | pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent) | ||
237 | { | 239 | { |
238 | if (IS_ENABLED(CONFIG_OF)) | 240 | pxa_dt_irq_init(pxa27x_set_wake); |
239 | pxa_dt_irq_init(pxa27x_set_wake); | 241 | set_handle_irq(ichp_handle_irq); |
242 | |||
243 | return 0; | ||
240 | } | 244 | } |
245 | IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq); | ||
241 | 246 | ||
242 | static struct map_desc pxa27x_io_desc[] __initdata = { | 247 | static struct map_desc pxa27x_io_desc[] __initdata = { |
243 | { /* Mem Ctl */ | 248 | { /* Mem Ctl */ |
@@ -300,9 +305,6 @@ static int __init pxa27x_init(void) | |||
300 | 305 | ||
301 | reset_status = RCSR; | 306 | reset_status = RCSR; |
302 | 307 | ||
303 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) | ||
304 | return ret; | ||
305 | |||
306 | pxa27x_init_pm(); | 308 | pxa27x_init_pm(); |
307 | 309 | ||
308 | register_syscore_ops(&pxa_irq_syscore_ops); | 310 | register_syscore_ops(&pxa_irq_syscore_ops); |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 3c9184d1d6b9..87acc96388c7 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/pm.h> | 19 | #include <linux/pm.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | #include <linux/irqchip.h> | ||
22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
23 | #include <linux/of.h> | 24 | #include <linux/of.h> |
24 | #include <linux/syscore_ops.h> | 25 | #include <linux/syscore_ops.h> |
@@ -356,11 +357,16 @@ void __init pxa3xx_init_irq(void) | |||
356 | } | 357 | } |
357 | 358 | ||
358 | #ifdef CONFIG_OF | 359 | #ifdef CONFIG_OF |
359 | void __init pxa3xx_dt_init_irq(void) | 360 | static int __init __init |
361 | pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent) | ||
360 | { | 362 | { |
361 | __pxa3xx_init_irq(); | 363 | __pxa3xx_init_irq(); |
362 | pxa_dt_irq_init(pxa3xx_set_wake); | 364 | pxa_dt_irq_init(pxa3xx_set_wake); |
365 | set_handle_irq(ichp_handle_irq); | ||
366 | |||
367 | return 0; | ||
363 | } | 368 | } |
369 | IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq); | ||
364 | #endif /* CONFIG_OF */ | 370 | #endif /* CONFIG_OF */ |
365 | 371 | ||
366 | static struct map_desc pxa3xx_io_desc[] __initdata = { | 372 | static struct map_desc pxa3xx_io_desc[] __initdata = { |
@@ -438,9 +444,6 @@ static int __init pxa3xx_init(void) | |||
438 | */ | 444 | */ |
439 | NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; | 445 | NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; |
440 | 446 | ||
441 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) | ||
442 | return ret; | ||
443 | |||
444 | pxa3xx_init_pm(); | 447 | pxa3xx_init_pm(); |
445 | 448 | ||
446 | register_syscore_ops(&pxa_irq_syscore_ops); | 449 | register_syscore_ops(&pxa_irq_syscore_ops); |
diff --git a/arch/arm/mach-pxa/pxa_cplds_irqs.c b/arch/arm/mach-pxa/pxa_cplds_irqs.c index 2385052b0ce1..e362f865fcd2 100644 --- a/arch/arm/mach-pxa/pxa_cplds_irqs.c +++ b/arch/arm/mach-pxa/pxa_cplds_irqs.c | |||
@@ -41,30 +41,35 @@ static irqreturn_t cplds_irq_handler(int in_irq, void *d) | |||
41 | unsigned long pending; | 41 | unsigned long pending; |
42 | unsigned int bit; | 42 | unsigned int bit; |
43 | 43 | ||
44 | pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; | 44 | do { |
45 | for_each_set_bit(bit, &pending, CPLDS_NB_IRQ) | 45 | pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; |
46 | generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit)); | 46 | for_each_set_bit(bit, &pending, CPLDS_NB_IRQ) { |
47 | generic_handle_irq(irq_find_mapping(fpga->irqdomain, | ||
48 | bit)); | ||
49 | } | ||
50 | } while (pending); | ||
47 | 51 | ||
48 | return IRQ_HANDLED; | 52 | return IRQ_HANDLED; |
49 | } | 53 | } |
50 | 54 | ||
51 | static void cplds_irq_mask_ack(struct irq_data *d) | 55 | static void cplds_irq_mask(struct irq_data *d) |
52 | { | 56 | { |
53 | struct cplds *fpga = irq_data_get_irq_chip_data(d); | 57 | struct cplds *fpga = irq_data_get_irq_chip_data(d); |
54 | unsigned int cplds_irq = irqd_to_hwirq(d); | 58 | unsigned int cplds_irq = irqd_to_hwirq(d); |
55 | unsigned int set, bit = BIT(cplds_irq); | 59 | unsigned int bit = BIT(cplds_irq); |
56 | 60 | ||
57 | fpga->irq_mask &= ~bit; | 61 | fpga->irq_mask &= ~bit; |
58 | writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); | 62 | writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); |
59 | set = readl(fpga->base + FPGA_IRQ_SET_CLR); | ||
60 | writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); | ||
61 | } | 63 | } |
62 | 64 | ||
63 | static void cplds_irq_unmask(struct irq_data *d) | 65 | static void cplds_irq_unmask(struct irq_data *d) |
64 | { | 66 | { |
65 | struct cplds *fpga = irq_data_get_irq_chip_data(d); | 67 | struct cplds *fpga = irq_data_get_irq_chip_data(d); |
66 | unsigned int cplds_irq = irqd_to_hwirq(d); | 68 | unsigned int cplds_irq = irqd_to_hwirq(d); |
67 | unsigned int bit = BIT(cplds_irq); | 69 | unsigned int set, bit = BIT(cplds_irq); |
70 | |||
71 | set = readl(fpga->base + FPGA_IRQ_SET_CLR); | ||
72 | writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); | ||
68 | 73 | ||
69 | fpga->irq_mask |= bit; | 74 | fpga->irq_mask |= bit; |
70 | writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); | 75 | writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); |
@@ -72,7 +77,8 @@ static void cplds_irq_unmask(struct irq_data *d) | |||
72 | 77 | ||
73 | static struct irq_chip cplds_irq_chip = { | 78 | static struct irq_chip cplds_irq_chip = { |
74 | .name = "pxa_cplds", | 79 | .name = "pxa_cplds", |
75 | .irq_mask_ack = cplds_irq_mask_ack, | 80 | .irq_ack = cplds_irq_mask, |
81 | .irq_mask = cplds_irq_mask, | ||
76 | .irq_unmask = cplds_irq_unmask, | 82 | .irq_unmask = cplds_irq_unmask, |
77 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, | 83 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, |
78 | }; | 84 | }; |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index b80eab9993c5..249b7bd5fbc4 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
@@ -744,7 +744,7 @@ static int sharpsl_off_charge_battery(void) | |||
744 | time = RCNR; | 744 | time = RCNR; |
745 | while (1) { | 745 | while (1) { |
746 | /* Check if any wakeup event had occurred */ | 746 | /* Check if any wakeup event had occurred */ |
747 | if (sharpsl_pm.machinfo->charger_wakeup() != 0) | 747 | if (sharpsl_pm.machinfo->charger_wakeup()) |
748 | return 0; | 748 | return 0; |
749 | /* Check for timeout */ | 749 | /* Check for timeout */ |
750 | if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) | 750 | if ((RCNR - time) > SHARPSL_WAIT_CO_TIME) |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.h b/arch/arm/mach-pxa/sharpsl_pm.h index 905be6755f04..fa75b6df8134 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.h +++ b/arch/arm/mach-pxa/sharpsl_pm.h | |||
@@ -34,7 +34,7 @@ struct sharpsl_charger_machinfo { | |||
34 | #define SHARPSL_STATUS_LOCK 5 | 34 | #define SHARPSL_STATUS_LOCK 5 |
35 | #define SHARPSL_STATUS_CHRGFULL 6 | 35 | #define SHARPSL_STATUS_CHRGFULL 6 |
36 | #define SHARPSL_STATUS_FATAL 7 | 36 | #define SHARPSL_STATUS_FATAL 7 |
37 | unsigned long (*charger_wakeup)(void); | 37 | bool (*charger_wakeup)(void); |
38 | int (*should_wakeup)(unsigned int resume_on_alarm); | 38 | int (*should_wakeup)(unsigned int resume_on_alarm); |
39 | void (*backlight_limit)(int); | 39 | void (*backlight_limit)(int); |
40 | int (*backlight_get_status) (void); | 40 | int (*backlight_get_status) (void); |
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index ea9f9034cb54..4e64a140252e 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c | |||
@@ -165,13 +165,10 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm) | |||
165 | return is_resume; | 165 | return is_resume; |
166 | } | 166 | } |
167 | 167 | ||
168 | static unsigned long spitz_charger_wakeup(void) | 168 | static bool spitz_charger_wakeup(void) |
169 | { | 169 | { |
170 | unsigned long ret; | 170 | return !gpio_get_value(SPITZ_GPIO_KEY_INT) || |
171 | ret = ((!gpio_get_value(SPITZ_GPIO_KEY_INT) | 171 | gpio_get_value(SPITZ_GPIO_SYNC); |
172 | << GPIO_bit(SPITZ_GPIO_KEY_INT)) | ||
173 | | gpio_get_value(SPITZ_GPIO_SYNC)); | ||
174 | return ret; | ||
175 | } | 172 | } |
176 | 173 | ||
177 | unsigned long spitzpm_read_devdata(int type) | 174 | unsigned long spitzpm_read_devdata(int type) |
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 557b134db772..2f06a2e8b1dd 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile | |||
@@ -3,8 +3,6 @@ | |||
3 | # | 3 | # |
4 | ccflags-$(CONFIG_ARCH_MMP) := -I$(srctree)/$(src)/include | 4 | ccflags-$(CONFIG_ARCH_MMP) := -I$(srctree)/$(src)/include |
5 | 5 | ||
6 | obj-$(CONFIG_ARCH_PXA) := dma.o | ||
7 | |||
8 | obj-$(CONFIG_PXA3xx) += mfp.o | 6 | obj-$(CONFIG_PXA3xx) += mfp.o |
9 | obj-$(CONFIG_ARCH_MMP) += mfp.o | 7 | obj-$(CONFIG_ARCH_MMP) += mfp.o |
10 | 8 | ||
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c deleted file mode 100644 index de2b061889ec..000000000000 --- a/arch/arm/plat-pxa/dma.c +++ /dev/null | |||
@@ -1,386 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/plat-pxa/dma.c | ||
3 | * | ||
4 | * PXA DMA registration and IRQ dispatching | ||
5 | * | ||
6 | * Author: Nicolas Pitre | ||
7 | * Created: Nov 15, 2001 | ||
8 | * Copyright: MontaVista Software Inc. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/module.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/slab.h> | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/interrupt.h> | ||
20 | #include <linux/errno.h> | ||
21 | #include <linux/dma-mapping.h> | ||
22 | |||
23 | #include <asm/irq.h> | ||
24 | #include <asm/memory.h> | ||
25 | #include <mach/hardware.h> | ||
26 | #include <mach/dma.h> | ||
27 | |||
28 | #define DMA_DEBUG_NAME "pxa_dma" | ||
29 | #define DMA_MAX_REQUESTERS 64 | ||
30 | |||
31 | struct dma_channel { | ||
32 | char *name; | ||
33 | pxa_dma_prio prio; | ||
34 | void (*irq_handler)(int, void *); | ||
35 | void *data; | ||
36 | spinlock_t lock; | ||
37 | }; | ||
38 | |||
39 | static struct dma_channel *dma_channels; | ||
40 | static int num_dma_channels; | ||
41 | |||
42 | /* | ||
43 | * Debug fs | ||
44 | */ | ||
45 | #ifdef CONFIG_DEBUG_FS | ||
46 | #include <linux/debugfs.h> | ||
47 | #include <linux/uaccess.h> | ||
48 | #include <linux/seq_file.h> | ||
49 | |||
50 | static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan; | ||
51 | |||
52 | static int dbg_show_requester_chan(struct seq_file *s, void *p) | ||
53 | { | ||
54 | int chan = (int)s->private; | ||
55 | int i; | ||
56 | u32 drcmr; | ||
57 | |||
58 | seq_printf(s, "DMA channel %d requesters list :\n", chan); | ||
59 | for (i = 0; i < DMA_MAX_REQUESTERS; i++) { | ||
60 | drcmr = DRCMR(i); | ||
61 | if ((drcmr & DRCMR_CHLNUM) == chan) | ||
62 | seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", | ||
63 | i, !!(drcmr & DRCMR_MAPVLD)); | ||
64 | } | ||
65 | |||
66 | return 0; | ||
67 | } | ||
68 | |||
69 | static inline int dbg_burst_from_dcmd(u32 dcmd) | ||
70 | { | ||
71 | int burst = (dcmd >> 16) & 0x3; | ||
72 | |||
73 | return burst ? 4 << burst : 0; | ||
74 | } | ||
75 | |||
76 | static int is_phys_valid(unsigned long addr) | ||
77 | { | ||
78 | return pfn_valid(__phys_to_pfn(addr)); | ||
79 | } | ||
80 | |||
81 | #define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "") | ||
82 | #define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "") | ||
83 | |||
84 | static int dbg_show_descriptors(struct seq_file *s, void *p) | ||
85 | { | ||
86 | int chan = (int)s->private; | ||
87 | int i, max_show = 20, burst, width; | ||
88 | u32 dcmd; | ||
89 | unsigned long phys_desc; | ||
90 | struct pxa_dma_desc *desc; | ||
91 | unsigned long flags; | ||
92 | |||
93 | spin_lock_irqsave(&dma_channels[chan].lock, flags); | ||
94 | phys_desc = DDADR(chan); | ||
95 | |||
96 | seq_printf(s, "DMA channel %d descriptors :\n", chan); | ||
97 | seq_printf(s, "[%03d] First descriptor unknown\n", 0); | ||
98 | for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { | ||
99 | desc = phys_to_virt(phys_desc); | ||
100 | dcmd = desc->dcmd; | ||
101 | burst = dbg_burst_from_dcmd(dcmd); | ||
102 | width = (1 << ((dcmd >> 14) & 0x3)) >> 1; | ||
103 | |||
104 | seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", | ||
105 | i, phys_desc, desc); | ||
106 | seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); | ||
107 | seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); | ||
108 | seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); | ||
109 | seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", | ||
110 | dcmd, | ||
111 | DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), | ||
112 | DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), | ||
113 | DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), | ||
114 | DCMD_STR(ENDIAN), burst, width, | ||
115 | dcmd & DCMD_LENGTH); | ||
116 | phys_desc = desc->ddadr; | ||
117 | } | ||
118 | if (i == max_show) | ||
119 | seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", | ||
120 | i, phys_desc); | ||
121 | else | ||
122 | seq_printf(s, "[%03d] Desc at %08lx is %s\n", | ||
123 | i, phys_desc, phys_desc == DDADR_STOP ? | ||
124 | "DDADR_STOP" : "invalid"); | ||
125 | |||
126 | spin_unlock_irqrestore(&dma_channels[chan].lock, flags); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static int dbg_show_chan_state(struct seq_file *s, void *p) | ||
132 | { | ||
133 | int chan = (int)s->private; | ||
134 | u32 dcsr, dcmd; | ||
135 | int burst, width; | ||
136 | static char *str_prio[] = { "high", "normal", "low" }; | ||
137 | |||
138 | dcsr = DCSR(chan); | ||
139 | dcmd = DCMD(chan); | ||
140 | burst = dbg_burst_from_dcmd(dcmd); | ||
141 | width = (1 << ((dcmd >> 14) & 0x3)) >> 1; | ||
142 | |||
143 | seq_printf(s, "DMA channel %d\n", chan); | ||
144 | seq_printf(s, "\tPriority : %s\n", str_prio[dma_channels[chan].prio]); | ||
145 | seq_printf(s, "\tUnaligned transfer bit: %s\n", | ||
146 | DALGN & (1 << chan) ? "yes" : "no"); | ||
147 | seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", | ||
148 | dcsr, DCSR_STR(RUN), DCSR_STR(NODESC), | ||
149 | DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN), | ||
150 | DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN), | ||
151 | DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST), | ||
152 | DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND), | ||
153 | DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR), | ||
154 | DCSR_STR(STARTINTR), DCSR_STR(BUSERR)); | ||
155 | |||
156 | seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", | ||
157 | dcmd, | ||
158 | DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR), | ||
159 | DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG), | ||
160 | DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN), | ||
161 | DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH); | ||
162 | seq_printf(s, "\tDSADR = %08x\n", DSADR(chan)); | ||
163 | seq_printf(s, "\tDTADR = %08x\n", DTADR(chan)); | ||
164 | seq_printf(s, "\tDDADR = %08x\n", DDADR(chan)); | ||
165 | |||
166 | return 0; | ||
167 | } | ||
168 | |||
169 | static int dbg_show_state(struct seq_file *s, void *p) | ||
170 | { | ||
171 | /* basic device status */ | ||
172 | seq_puts(s, "DMA engine status\n"); | ||
173 | seq_printf(s, "\tChannel number: %d\n", num_dma_channels); | ||
174 | |||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | #define DBGFS_FUNC_DECL(name) \ | ||
179 | static int dbg_open_##name(struct inode *inode, struct file *file) \ | ||
180 | { \ | ||
181 | return single_open(file, dbg_show_##name, inode->i_private); \ | ||
182 | } \ | ||
183 | static const struct file_operations dbg_fops_##name = { \ | ||
184 | .owner = THIS_MODULE, \ | ||
185 | .open = dbg_open_##name, \ | ||
186 | .llseek = seq_lseek, \ | ||
187 | .read = seq_read, \ | ||
188 | .release = single_release, \ | ||
189 | } | ||
190 | |||
191 | DBGFS_FUNC_DECL(state); | ||
192 | DBGFS_FUNC_DECL(chan_state); | ||
193 | DBGFS_FUNC_DECL(descriptors); | ||
194 | DBGFS_FUNC_DECL(requester_chan); | ||
195 | |||
196 | static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir) | ||
197 | { | ||
198 | char chan_name[11]; | ||
199 | struct dentry *chan, *chan_state = NULL, *chan_descr = NULL; | ||
200 | struct dentry *chan_reqs = NULL; | ||
201 | void *dt; | ||
202 | |||
203 | scnprintf(chan_name, sizeof(chan_name), "%d", ch); | ||
204 | chan = debugfs_create_dir(chan_name, chandir); | ||
205 | dt = (void *)ch; | ||
206 | |||
207 | if (chan) | ||
208 | chan_state = debugfs_create_file("state", 0400, chan, dt, | ||
209 | &dbg_fops_chan_state); | ||
210 | if (chan_state) | ||
211 | chan_descr = debugfs_create_file("descriptors", 0400, chan, dt, | ||
212 | &dbg_fops_descriptors); | ||
213 | if (chan_descr) | ||
214 | chan_reqs = debugfs_create_file("requesters", 0400, chan, dt, | ||
215 | &dbg_fops_requester_chan); | ||
216 | if (!chan_reqs) | ||
217 | goto err_state; | ||
218 | |||
219 | return chan; | ||
220 | |||
221 | err_state: | ||
222 | debugfs_remove_recursive(chan); | ||
223 | return NULL; | ||
224 | } | ||
225 | |||
226 | static void pxa_dma_init_debugfs(void) | ||
227 | { | ||
228 | int i; | ||
229 | struct dentry *chandir; | ||
230 | |||
231 | dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL); | ||
232 | if (IS_ERR(dbgfs_root) || !dbgfs_root) | ||
233 | goto err_root; | ||
234 | |||
235 | dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL, | ||
236 | &dbg_fops_state); | ||
237 | if (!dbgfs_state) | ||
238 | goto err_state; | ||
239 | |||
240 | dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels, | ||
241 | GFP_KERNEL); | ||
242 | if (!dbgfs_chan) | ||
243 | goto err_alloc; | ||
244 | |||
245 | chandir = debugfs_create_dir("channels", dbgfs_root); | ||
246 | if (!chandir) | ||
247 | goto err_chandir; | ||
248 | |||
249 | for (i = 0; i < num_dma_channels; i++) { | ||
250 | dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir); | ||
251 | if (!dbgfs_chan[i]) | ||
252 | goto err_chans; | ||
253 | } | ||
254 | |||
255 | return; | ||
256 | err_chans: | ||
257 | err_chandir: | ||
258 | kfree(dbgfs_chan); | ||
259 | err_alloc: | ||
260 | err_state: | ||
261 | debugfs_remove_recursive(dbgfs_root); | ||
262 | err_root: | ||
263 | pr_err("pxa_dma: debugfs is not available\n"); | ||
264 | } | ||
265 | |||
266 | static void __exit pxa_dma_cleanup_debugfs(void) | ||
267 | { | ||
268 | debugfs_remove_recursive(dbgfs_root); | ||
269 | } | ||
270 | #else | ||
271 | static inline void pxa_dma_init_debugfs(void) {} | ||
272 | static inline void pxa_dma_cleanup_debugfs(void) {} | ||
273 | #endif | ||
274 | |||
275 | int pxa_request_dma (char *name, pxa_dma_prio prio, | ||
276 | void (*irq_handler)(int, void *), | ||
277 | void *data) | ||
278 | { | ||
279 | unsigned long flags; | ||
280 | int i, found = 0; | ||
281 | |||
282 | /* basic sanity checks */ | ||
283 | if (!name || !irq_handler) | ||
284 | return -EINVAL; | ||
285 | |||
286 | local_irq_save(flags); | ||
287 | |||
288 | do { | ||
289 | /* try grabbing a DMA channel with the requested priority */ | ||
290 | for (i = 0; i < num_dma_channels; i++) { | ||
291 | if ((dma_channels[i].prio == prio) && | ||
292 | !dma_channels[i].name && | ||
293 | !pxad_toggle_reserved_channel(i)) { | ||
294 | found = 1; | ||
295 | break; | ||
296 | } | ||
297 | } | ||
298 | /* if requested prio group is full, try a hier priority */ | ||
299 | } while (!found && prio--); | ||
300 | |||
301 | if (found) { | ||
302 | DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | ||
303 | dma_channels[i].name = name; | ||
304 | dma_channels[i].irq_handler = irq_handler; | ||
305 | dma_channels[i].data = data; | ||
306 | } else { | ||
307 | printk (KERN_WARNING "No more available DMA channels for %s\n", name); | ||
308 | i = -ENODEV; | ||
309 | } | ||
310 | |||
311 | local_irq_restore(flags); | ||
312 | return i; | ||
313 | } | ||
314 | EXPORT_SYMBOL(pxa_request_dma); | ||
315 | |||
316 | void pxa_free_dma (int dma_ch) | ||
317 | { | ||
318 | unsigned long flags; | ||
319 | |||
320 | if (!dma_channels[dma_ch].name) { | ||
321 | printk (KERN_CRIT | ||
322 | "%s: trying to free channel %d which is already freed\n", | ||
323 | __func__, dma_ch); | ||
324 | return; | ||
325 | } | ||
326 | |||
327 | local_irq_save(flags); | ||
328 | DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | ||
329 | dma_channels[dma_ch].name = NULL; | ||
330 | pxad_toggle_reserved_channel(dma_ch); | ||
331 | local_irq_restore(flags); | ||
332 | } | ||
333 | EXPORT_SYMBOL(pxa_free_dma); | ||
334 | |||
335 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) | ||
336 | { | ||
337 | int i, dint = DINT, done = 0; | ||
338 | struct dma_channel *channel; | ||
339 | |||
340 | while (dint) { | ||
341 | i = __ffs(dint); | ||
342 | dint &= (dint - 1); | ||
343 | channel = &dma_channels[i]; | ||
344 | if (channel->name && channel->irq_handler) { | ||
345 | channel->irq_handler(i, channel->data); | ||
346 | done++; | ||
347 | } | ||
348 | } | ||
349 | if (done) | ||
350 | return IRQ_HANDLED; | ||
351 | else | ||
352 | return IRQ_NONE; | ||
353 | } | ||
354 | |||
355 | int __init pxa_init_dma(int irq, int num_ch) | ||
356 | { | ||
357 | int i, ret; | ||
358 | |||
359 | dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL); | ||
360 | if (dma_channels == NULL) | ||
361 | return -ENOMEM; | ||
362 | |||
363 | /* dma channel priorities on pxa2xx processors: | ||
364 | * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH | ||
365 | * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM | ||
366 | * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW | ||
367 | */ | ||
368 | for (i = 0; i < num_ch; i++) { | ||
369 | DCSR(i) = 0; | ||
370 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); | ||
371 | spin_lock_init(&dma_channels[i].lock); | ||
372 | } | ||
373 | |||
374 | ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA", | ||
375 | dma_channels); | ||
376 | if (ret) { | ||
377 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); | ||
378 | kfree(dma_channels); | ||
379 | return ret; | ||
380 | } | ||
381 | num_dma_channels = num_ch; | ||
382 | |||
383 | pxa_dma_init_debugfs(); | ||
384 | |||
385 | return 0; | ||
386 | } | ||
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h deleted file mode 100644 index ceba3e4184fc..000000000000 --- a/arch/arm/plat-pxa/include/plat/dma.h +++ /dev/null | |||
@@ -1,100 +0,0 @@ | |||
1 | #ifndef __PLAT_DMA_H | ||
2 | #define __PLAT_DMA_H | ||
3 | |||
4 | #define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x)))) | ||
5 | |||
6 | #define DCSR(n) DMAC_REG((n) << 2) | ||
7 | #define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */ | ||
8 | #define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */ | ||
9 | #define DDADR(n) DMAC_REG(0x0200 + ((n) << 4)) | ||
10 | #define DSADR(n) DMAC_REG(0x0204 + ((n) << 4)) | ||
11 | #define DTADR(n) DMAC_REG(0x0208 + ((n) << 4)) | ||
12 | #define DCMD(n) DMAC_REG(0x020c + ((n) << 4)) | ||
13 | #define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \ | ||
14 | (((n) & 0x3f) << 2)) | ||
15 | |||
16 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
17 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
18 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
19 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
20 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
21 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
22 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
23 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
24 | |||
25 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
26 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
27 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
28 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
29 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
30 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
31 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
32 | |||
33 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
34 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
35 | |||
36 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
37 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
38 | |||
39 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
40 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
41 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
42 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
43 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
44 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
45 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
46 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
47 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
48 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
49 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
50 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
51 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
52 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
53 | |||
54 | /* | ||
55 | * Descriptor structure for PXA's DMA engine | ||
56 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
57 | */ | ||
58 | |||
59 | typedef struct pxa_dma_desc { | ||
60 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
61 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
62 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
63 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
64 | } pxa_dma_desc; | ||
65 | |||
66 | typedef enum { | ||
67 | DMA_PRIO_HIGH = 0, | ||
68 | DMA_PRIO_MEDIUM = 1, | ||
69 | DMA_PRIO_LOW = 2 | ||
70 | } pxa_dma_prio; | ||
71 | |||
72 | /* | ||
73 | * DMA registration | ||
74 | */ | ||
75 | |||
76 | int __init pxa_init_dma(int irq, int num_ch); | ||
77 | |||
78 | int pxa_request_dma (char *name, | ||
79 | pxa_dma_prio prio, | ||
80 | void (*irq_handler)(int, void *), | ||
81 | void *data); | ||
82 | |||
83 | void pxa_free_dma (int dma_ch); | ||
84 | |||
85 | /* | ||
86 | * Cooperation with pxa_dma + dmaengine while there remains at least one pxa | ||
87 | * driver not converted to dmaengine. | ||
88 | */ | ||
89 | #if defined(CONFIG_PXA_DMA) | ||
90 | extern int pxad_toggle_reserved_channel(int legacy_channel); | ||
91 | #else | ||
92 | static inline int pxad_toggle_reserved_channel(int legacy_channel) | ||
93 | { | ||
94 | return 0; | ||
95 | } | ||
96 | #endif | ||
97 | |||
98 | extern void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors); | ||
99 | |||
100 | #endif /* __PLAT_DMA_H */ | ||