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authorArthur Kiyanovski <akiyano@amazon.com>2018-10-11 04:26:27 -0400
committerDavid S. Miller <davem@davemloft.net>2018-10-11 13:13:51 -0400
commitbe26667cb3947c90322467f1d15ad86b02350e00 (patch)
tree2b9a10f922ea0045b47828026d8fea9f44059c2c
parent3a7b9d8ddd200bdafaa3ef75b8544d2403eaa03b (diff)
net: ena: fix indentations in ena_defs for better readability
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/amazon/ena/ena_admin_defs.h334
-rw-r--r--drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h223
-rw-r--r--drivers/net/ethernet/amazon/ena/ena_regs_defs.h206
3 files changed, 338 insertions, 425 deletions
diff --git a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
index b439ec1b3edb..9f80b73f90b1 100644
--- a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
+++ b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
@@ -32,119 +32,81 @@
32#ifndef _ENA_ADMIN_H_ 32#ifndef _ENA_ADMIN_H_
33#define _ENA_ADMIN_H_ 33#define _ENA_ADMIN_H_
34 34
35enum ena_admin_aq_opcode {
36 ENA_ADMIN_CREATE_SQ = 1,
37
38 ENA_ADMIN_DESTROY_SQ = 2,
39
40 ENA_ADMIN_CREATE_CQ = 3,
41
42 ENA_ADMIN_DESTROY_CQ = 4,
43
44 ENA_ADMIN_GET_FEATURE = 8,
45 35
46 ENA_ADMIN_SET_FEATURE = 9, 36enum ena_admin_aq_opcode {
47 37 ENA_ADMIN_CREATE_SQ = 1,
48 ENA_ADMIN_GET_STATS = 11, 38 ENA_ADMIN_DESTROY_SQ = 2,
39 ENA_ADMIN_CREATE_CQ = 3,
40 ENA_ADMIN_DESTROY_CQ = 4,
41 ENA_ADMIN_GET_FEATURE = 8,
42 ENA_ADMIN_SET_FEATURE = 9,
43 ENA_ADMIN_GET_STATS = 11,
49}; 44};
50 45
51enum ena_admin_aq_completion_status { 46enum ena_admin_aq_completion_status {
52 ENA_ADMIN_SUCCESS = 0, 47 ENA_ADMIN_SUCCESS = 0,
53 48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
54 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 49 ENA_ADMIN_BAD_OPCODE = 2,
55 50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
56 ENA_ADMIN_BAD_OPCODE = 2, 51 ENA_ADMIN_MALFORMED_REQUEST = 4,
57
58 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
59
60 ENA_ADMIN_MALFORMED_REQUEST = 4,
61
62 /* Additional status is provided in ACQ entry extended_status */ 52 /* Additional status is provided in ACQ entry extended_status */
63 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 53 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
64 54 ENA_ADMIN_UNKNOWN_ERROR = 6,
65 ENA_ADMIN_UNKNOWN_ERROR = 6, 55 ENA_ADMIN_RESOURCE_BUSY = 7,
66
67 ENA_ADMIN_RESOURCE_BUSY = 7,
68}; 56};
69 57
70enum ena_admin_aq_feature_id { 58enum ena_admin_aq_feature_id {
71 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
72 60 ENA_ADMIN_MAX_QUEUES_NUM = 2,
73 ENA_ADMIN_MAX_QUEUES_NUM = 2, 61 ENA_ADMIN_HW_HINTS = 3,
74 62 ENA_ADMIN_LLQ = 4,
75 ENA_ADMIN_HW_HINTS = 3, 63 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
76 64 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
77 ENA_ADMIN_LLQ = 4, 65 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
78 66 ENA_ADMIN_MTU = 14,
79 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 67 ENA_ADMIN_RSS_HASH_INPUT = 18,
80 68 ENA_ADMIN_INTERRUPT_MODERATION = 20,
81 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 69 ENA_ADMIN_AENQ_CONFIG = 26,
82 70 ENA_ADMIN_LINK_CONFIG = 27,
83 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 71 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
84 72 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
85 ENA_ADMIN_MTU = 14,
86
87 ENA_ADMIN_RSS_HASH_INPUT = 18,
88
89 ENA_ADMIN_INTERRUPT_MODERATION = 20,
90
91 ENA_ADMIN_AENQ_CONFIG = 26,
92
93 ENA_ADMIN_LINK_CONFIG = 27,
94
95 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
96
97 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
98}; 73};
99 74
100enum ena_admin_placement_policy_type { 75enum ena_admin_placement_policy_type {
101 /* descriptors and headers are in host memory */ 76 /* descriptors and headers are in host memory */
102 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 77 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
103
104 /* descriptors and headers are in device memory (a.k.a Low Latency 78 /* descriptors and headers are in device memory (a.k.a Low Latency
105 * Queue) 79 * Queue)
106 */ 80 */
107 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 81 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
108}; 82};
109 83
110enum ena_admin_link_types { 84enum ena_admin_link_types {
111 ENA_ADMIN_LINK_SPEED_1G = 0x1, 85 ENA_ADMIN_LINK_SPEED_1G = 0x1,
112 86 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
113 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 87 ENA_ADMIN_LINK_SPEED_5G = 0x4,
114 88 ENA_ADMIN_LINK_SPEED_10G = 0x8,
115 ENA_ADMIN_LINK_SPEED_5G = 0x4, 89 ENA_ADMIN_LINK_SPEED_25G = 0x10,
116 90 ENA_ADMIN_LINK_SPEED_40G = 0x20,
117 ENA_ADMIN_LINK_SPEED_10G = 0x8, 91 ENA_ADMIN_LINK_SPEED_50G = 0x40,
118 92 ENA_ADMIN_LINK_SPEED_100G = 0x80,
119 ENA_ADMIN_LINK_SPEED_25G = 0x10, 93 ENA_ADMIN_LINK_SPEED_200G = 0x100,
120 94 ENA_ADMIN_LINK_SPEED_400G = 0x200,
121 ENA_ADMIN_LINK_SPEED_40G = 0x20,
122
123 ENA_ADMIN_LINK_SPEED_50G = 0x40,
124
125 ENA_ADMIN_LINK_SPEED_100G = 0x80,
126
127 ENA_ADMIN_LINK_SPEED_200G = 0x100,
128
129 ENA_ADMIN_LINK_SPEED_400G = 0x200,
130}; 95};
131 96
132enum ena_admin_completion_policy_type { 97enum ena_admin_completion_policy_type {
133 /* completion queue entry for each sq descriptor */ 98 /* completion queue entry for each sq descriptor */
134 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 99 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
135
136 /* completion queue entry upon request in sq descriptor */ 100 /* completion queue entry upon request in sq descriptor */
137 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 101 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
138
139 /* current queue head pointer is updated in OS memory upon sq 102 /* current queue head pointer is updated in OS memory upon sq
140 * descriptor request 103 * descriptor request
141 */ 104 */
142 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 105 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
143
144 /* current queue head pointer is updated in OS memory for each sq 106 /* current queue head pointer is updated in OS memory for each sq
145 * descriptor 107 * descriptor
146 */ 108 */
147 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 109 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
148}; 110};
149 111
150/* basic stats return ena_admin_basic_stats while extanded stats return a 112/* basic stats return ena_admin_basic_stats while extanded stats return a
@@ -152,15 +114,13 @@ enum ena_admin_completion_policy_type {
152 * device id 114 * device id
153 */ 115 */
154enum ena_admin_get_stats_type { 116enum ena_admin_get_stats_type {
155 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 117 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
156 118 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
157 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
158}; 119};
159 120
160enum ena_admin_get_stats_scope { 121enum ena_admin_get_stats_scope {
161 ENA_ADMIN_SPECIFIC_QUEUE = 0, 122 ENA_ADMIN_SPECIFIC_QUEUE = 0,
162 123 ENA_ADMIN_ETH_TRAFFIC = 1,
163 ENA_ADMIN_ETH_TRAFFIC = 1,
164}; 124};
165 125
166struct ena_admin_aq_common_desc { 126struct ena_admin_aq_common_desc {
@@ -231,7 +191,9 @@ struct ena_admin_acq_common_desc {
231 191
232 u16 extended_status; 192 u16 extended_status;
233 193
234 /* serves as a hint what AQ entries can be revoked */ 194 /* indicates to the driver which AQ entry has been consumed by the
195 * device and could be reused
196 */
235 u16 sq_head_indx; 197 u16 sq_head_indx;
236}; 198};
237 199
@@ -300,9 +262,8 @@ struct ena_admin_aq_create_sq_cmd {
300}; 262};
301 263
302enum ena_admin_sq_direction { 264enum ena_admin_sq_direction {
303 ENA_ADMIN_SQ_DIRECTION_TX = 1, 265 ENA_ADMIN_SQ_DIRECTION_TX = 1,
304 266 ENA_ADMIN_SQ_DIRECTION_RX = 2,
305 ENA_ADMIN_SQ_DIRECTION_RX = 2,
306}; 267};
307 268
308struct ena_admin_acq_create_sq_resp_desc { 269struct ena_admin_acq_create_sq_resp_desc {
@@ -664,9 +625,8 @@ struct ena_admin_feature_offload_desc {
664}; 625};
665 626
666enum ena_admin_hash_functions { 627enum ena_admin_hash_functions {
667 ENA_ADMIN_TOEPLITZ = 1, 628 ENA_ADMIN_TOEPLITZ = 1,
668 629 ENA_ADMIN_CRC32 = 2,
669 ENA_ADMIN_CRC32 = 2,
670}; 630};
671 631
672struct ena_admin_feature_rss_flow_hash_control { 632struct ena_admin_feature_rss_flow_hash_control {
@@ -692,50 +652,35 @@ struct ena_admin_feature_rss_flow_hash_function {
692 652
693/* RSS flow hash protocols */ 653/* RSS flow hash protocols */
694enum ena_admin_flow_hash_proto { 654enum ena_admin_flow_hash_proto {
695 ENA_ADMIN_RSS_TCP4 = 0, 655 ENA_ADMIN_RSS_TCP4 = 0,
696 656 ENA_ADMIN_RSS_UDP4 = 1,
697 ENA_ADMIN_RSS_UDP4 = 1, 657 ENA_ADMIN_RSS_TCP6 = 2,
698 658 ENA_ADMIN_RSS_UDP6 = 3,
699 ENA_ADMIN_RSS_TCP6 = 2, 659 ENA_ADMIN_RSS_IP4 = 4,
700 660 ENA_ADMIN_RSS_IP6 = 5,
701 ENA_ADMIN_RSS_UDP6 = 3, 661 ENA_ADMIN_RSS_IP4_FRAG = 6,
702 662 ENA_ADMIN_RSS_NOT_IP = 7,
703 ENA_ADMIN_RSS_IP4 = 4,
704
705 ENA_ADMIN_RSS_IP6 = 5,
706
707 ENA_ADMIN_RSS_IP4_FRAG = 6,
708
709 ENA_ADMIN_RSS_NOT_IP = 7,
710
711 /* TCPv6 with extension header */ 663 /* TCPv6 with extension header */
712 ENA_ADMIN_RSS_TCP6_EX = 8, 664 ENA_ADMIN_RSS_TCP6_EX = 8,
713
714 /* IPv6 with extension header */ 665 /* IPv6 with extension header */
715 ENA_ADMIN_RSS_IP6_EX = 9, 666 ENA_ADMIN_RSS_IP6_EX = 9,
716 667 ENA_ADMIN_RSS_PROTO_NUM = 16,
717 ENA_ADMIN_RSS_PROTO_NUM = 16,
718}; 668};
719 669
720/* RSS flow hash fields */ 670/* RSS flow hash fields */
721enum ena_admin_flow_hash_fields { 671enum ena_admin_flow_hash_fields {
722 /* Ethernet Dest Addr */ 672 /* Ethernet Dest Addr */
723 ENA_ADMIN_RSS_L2_DA = BIT(0), 673 ENA_ADMIN_RSS_L2_DA = BIT(0),
724
725 /* Ethernet Src Addr */ 674 /* Ethernet Src Addr */
726 ENA_ADMIN_RSS_L2_SA = BIT(1), 675 ENA_ADMIN_RSS_L2_SA = BIT(1),
727
728 /* ipv4/6 Dest Addr */ 676 /* ipv4/6 Dest Addr */
729 ENA_ADMIN_RSS_L3_DA = BIT(2), 677 ENA_ADMIN_RSS_L3_DA = BIT(2),
730
731 /* ipv4/6 Src Addr */ 678 /* ipv4/6 Src Addr */
732 ENA_ADMIN_RSS_L3_SA = BIT(3), 679 ENA_ADMIN_RSS_L3_SA = BIT(3),
733
734 /* tcp/udp Dest Port */ 680 /* tcp/udp Dest Port */
735 ENA_ADMIN_RSS_L4_DP = BIT(4), 681 ENA_ADMIN_RSS_L4_DP = BIT(4),
736
737 /* tcp/udp Src Port */ 682 /* tcp/udp Src Port */
738 ENA_ADMIN_RSS_L4_SP = BIT(5), 683 ENA_ADMIN_RSS_L4_SP = BIT(5),
739}; 684};
740 685
741struct ena_admin_proto_input { 686struct ena_admin_proto_input {
@@ -774,19 +719,13 @@ struct ena_admin_feature_rss_flow_hash_input {
774}; 719};
775 720
776enum ena_admin_os_type { 721enum ena_admin_os_type {
777 ENA_ADMIN_OS_LINUX = 1, 722 ENA_ADMIN_OS_LINUX = 1,
778 723 ENA_ADMIN_OS_WIN = 2,
779 ENA_ADMIN_OS_WIN = 2, 724 ENA_ADMIN_OS_DPDK = 3,
780 725 ENA_ADMIN_OS_FREEBSD = 4,
781 ENA_ADMIN_OS_DPDK = 3, 726 ENA_ADMIN_OS_IPXE = 5,
782 727 ENA_ADMIN_OS_ESXI = 6,
783 ENA_ADMIN_OS_FREEBSD = 4, 728 ENA_ADMIN_OS_GROUPS_NUM = 6,
784
785 ENA_ADMIN_OS_IPXE = 5,
786
787 ENA_ADMIN_OS_ESXI = 6,
788
789 ENA_ADMIN_OS_GROUPS_NUM = 6,
790}; 729};
791 730
792struct ena_admin_host_info { 731struct ena_admin_host_info {
@@ -981,25 +920,18 @@ struct ena_admin_aenq_common_desc {
981 920
982/* asynchronous event notification groups */ 921/* asynchronous event notification groups */
983enum ena_admin_aenq_group { 922enum ena_admin_aenq_group {
984 ENA_ADMIN_LINK_CHANGE = 0, 923 ENA_ADMIN_LINK_CHANGE = 0,
985 924 ENA_ADMIN_FATAL_ERROR = 1,
986 ENA_ADMIN_FATAL_ERROR = 1, 925 ENA_ADMIN_WARNING = 2,
987 926 ENA_ADMIN_NOTIFICATION = 3,
988 ENA_ADMIN_WARNING = 2, 927 ENA_ADMIN_KEEP_ALIVE = 4,
989 928 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
990 ENA_ADMIN_NOTIFICATION = 3,
991
992 ENA_ADMIN_KEEP_ALIVE = 4,
993
994 ENA_ADMIN_AENQ_GROUPS_NUM = 5,
995}; 929};
996 930
997enum ena_admin_aenq_notification_syndrom { 931enum ena_admin_aenq_notification_syndrom {
998 ENA_ADMIN_SUSPEND = 0, 932 ENA_ADMIN_SUSPEND = 0,
999 933 ENA_ADMIN_RESUME = 1,
1000 ENA_ADMIN_RESUME = 1, 934 ENA_ADMIN_UPDATE_HINTS = 2,
1001
1002 ENA_ADMIN_UPDATE_HINTS = 2,
1003}; 935};
1004 936
1005struct ena_admin_aenq_entry { 937struct ena_admin_aenq_entry {
@@ -1034,27 +966,27 @@ struct ena_admin_ena_mmio_req_read_less_resp {
1034}; 966};
1035 967
1036/* aq_common_desc */ 968/* aq_common_desc */
1037#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 969#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1038#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 970#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1039#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 971#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1040#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 972#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1041#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 973#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1042#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 974#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1043 975
1044/* sq */ 976/* sq */
1045#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 977#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1046#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 978#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1047 979
1048/* acq_common_desc */ 980/* acq_common_desc */
1049#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 981#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1050#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 982#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1051 983
1052/* aq_create_sq_cmd */ 984/* aq_create_sq_cmd */
1053#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 985#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1054#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 986#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1055#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 987#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1056#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 988#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1057#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 989#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1058#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 990#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1059 991
1060/* aq_create_cq_cmd */ 992/* aq_create_cq_cmd */
@@ -1063,12 +995,12 @@ struct ena_admin_ena_mmio_req_read_less_resp {
1063#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 995#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1064 996
1065/* get_set_feature_common_desc */ 997/* get_set_feature_common_desc */
1066#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 998#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1067 999
1068/* get_feature_link_desc */ 1000/* get_feature_link_desc */
1069#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1001#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1070#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1002#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1071#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1003#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1072 1004
1073/* feature_offload_desc */ 1005/* feature_offload_desc */
1074#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1006#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
@@ -1080,19 +1012,19 @@ struct ena_admin_ena_mmio_req_read_less_resp {
1080#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1012#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1081#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1013#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1082#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1014#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1083#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1015#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1084#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1016#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1085#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1017#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1086#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1018#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1087#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1019#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1088#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1020#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1089#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1021#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1090#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1022#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1091#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1023#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1092#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1024#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1093#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1025#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1094#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1026#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1095#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1027#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1096 1028
1097/* feature_rss_flow_hash_function */ 1029/* feature_rss_flow_hash_function */
1098#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1030#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
@@ -1100,32 +1032,32 @@ struct ena_admin_ena_mmio_req_read_less_resp {
1100 1032
1101/* feature_rss_flow_hash_input */ 1033/* feature_rss_flow_hash_input */
1102#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1034#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1103#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1035#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1104#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1036#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1105#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1037#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1106#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1038#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1107#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1039#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1108#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1040#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1109#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1041#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1110 1042
1111/* host_info */ 1043/* host_info */
1112#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1044#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1113#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1045#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1114#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1046#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1115#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1047#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1116#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1048#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1117#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1049#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1118#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1050#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1119#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1051#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1120#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1052#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1121#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1053#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1122#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1054#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1123#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1055#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1124 1056
1125/* aenq_common_desc */ 1057/* aenq_common_desc */
1126#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1058#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1127 1059
1128/* aenq_link_change_desc */ 1060/* aenq_link_change_desc */
1129#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1061#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1130 1062
1131#endif /*_ENA_ADMIN_H_ */ 1063#endif /*_ENA_ADMIN_H_ */
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
index 4c5ccaa13c42..00e0f056a741 100644
--- a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
@@ -33,25 +33,18 @@
33#define _ENA_ETH_IO_H_ 33#define _ENA_ETH_IO_H_
34 34
35enum ena_eth_io_l3_proto_index { 35enum ena_eth_io_l3_proto_index {
36 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 36 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
37 37 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
38 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 38 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
39 39 ENA_ETH_IO_L3_PROTO_FCOE = 21,
40 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 40 ENA_ETH_IO_L3_PROTO_ROCE = 22,
41
42 ENA_ETH_IO_L3_PROTO_FCOE = 21,
43
44 ENA_ETH_IO_L3_PROTO_ROCE = 22,
45}; 41};
46 42
47enum ena_eth_io_l4_proto_index { 43enum ena_eth_io_l4_proto_index {
48 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 44 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
49 45 ENA_ETH_IO_L4_PROTO_TCP = 12,
50 ENA_ETH_IO_L4_PROTO_TCP = 12, 46 ENA_ETH_IO_L4_PROTO_UDP = 13,
51 47 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
52 ENA_ETH_IO_L4_PROTO_UDP = 13,
53
54 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
55}; 48};
56 49
57struct ena_eth_io_tx_desc { 50struct ena_eth_io_tx_desc {
@@ -307,116 +300,116 @@ struct ena_eth_io_numa_node_cfg_reg {
307}; 300};
308 301
309/* tx_desc */ 302/* tx_desc */
310#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 303#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
311#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 304#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
312#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 305#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
313#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 306#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
314#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 307#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
315#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 308#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
316#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 309#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
317#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 310#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
318#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 311#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
319#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 312#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
320#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 313#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
321#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 314#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
322#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 315#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
323#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 316#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
324#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 317#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
325#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 318#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
326#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 319#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
327#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 320#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
328#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 321#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
329#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 322#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
330#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 323#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
331#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 324#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
332#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 325#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
333#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 326#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
334#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 327#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
335#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 328#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
336#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 329#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
337#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 330#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
338#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 331#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
339#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 332#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
340#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 333#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
341#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 334#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
342#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 335#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
343 336
344/* tx_meta_desc */ 337/* tx_meta_desc */
345#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 338#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
346#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 339#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
347#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 340#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
348#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 341#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
349#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 342#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
350#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 343#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
351#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 344#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
352#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 345#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
353#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 346#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
354#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 347#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
355#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 348#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
356#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 349#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
357#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 350#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
358#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 351#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
359#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 352#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
360#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 353#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
361#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 354#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
362#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 355#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
363#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 356#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
364#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 357#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
365#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 358#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
366#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 359#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
367#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 360#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
368#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 361#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
369#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 362#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
370#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 363#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
371#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 364#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
372 365
373/* tx_cdesc */ 366/* tx_cdesc */
374#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 367#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
375 368
376/* rx_desc */ 369/* rx_desc */
377#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 370#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
378#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 371#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
379#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 372#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
380#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 373#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
381#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 374#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
382#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 375#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
383#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 376#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
384 377
385/* rx_cdesc_base */ 378/* rx_cdesc_base */
386#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 379#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
387#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 380#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
388#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 381#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
389#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 382#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
390#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 383#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
391#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 384#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
392#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 385#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
393#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 386#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
394#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 387#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
395#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 388#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
396#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 389#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
397#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 390#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
398#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) 391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
399#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 392#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
400#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 393#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
401#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 394#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
402#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 395#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
403#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 396#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
404#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 397#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
405#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 398#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
406#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 399#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
407#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 400#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
408#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 401#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
409 402
410/* intr_reg */ 403/* intr_reg */
411#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 404#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
412#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 405#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
413#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 406#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
414#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 407#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
415#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 408#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
416 409
417/* numa_node_cfg_reg */ 410/* numa_node_cfg_reg */
418#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 411#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
419#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 412#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
420#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 413#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
421 414
422#endif /*_ENA_ETH_IO_H_ */ 415#endif /*_ENA_ETH_IO_H_ */
diff --git a/drivers/net/ethernet/amazon/ena/ena_regs_defs.h b/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
index 48ca97fbe7bc..04fcafcc059c 100644
--- a/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
+++ b/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
@@ -33,137 +33,125 @@
33#define _ENA_REGS_H_ 33#define _ENA_REGS_H_
34 34
35enum ena_regs_reset_reason_types { 35enum ena_regs_reset_reason_types {
36 ENA_REGS_RESET_NORMAL = 0, 36 ENA_REGS_RESET_NORMAL = 0,
37 37 ENA_REGS_RESET_KEEP_ALIVE_TO = 1,
38 ENA_REGS_RESET_KEEP_ALIVE_TO = 1, 38 ENA_REGS_RESET_ADMIN_TO = 2,
39 39 ENA_REGS_RESET_MISS_TX_CMPL = 3,
40 ENA_REGS_RESET_ADMIN_TO = 2, 40 ENA_REGS_RESET_INV_RX_REQ_ID = 4,
41 41 ENA_REGS_RESET_INV_TX_REQ_ID = 5,
42 ENA_REGS_RESET_MISS_TX_CMPL = 3, 42 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6,
43 43 ENA_REGS_RESET_INIT_ERR = 7,
44 ENA_REGS_RESET_INV_RX_REQ_ID = 4, 44 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,
45 45 ENA_REGS_RESET_OS_TRIGGER = 9,
46 ENA_REGS_RESET_INV_TX_REQ_ID = 5, 46 ENA_REGS_RESET_OS_NETDEV_WD = 10,
47 47 ENA_REGS_RESET_SHUTDOWN = 11,
48 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6, 48 ENA_REGS_RESET_USER_TRIGGER = 12,
49 49 ENA_REGS_RESET_GENERIC = 13,
50 ENA_REGS_RESET_INIT_ERR = 7, 50 ENA_REGS_RESET_MISS_INTERRUPT = 14,
51
52 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,
53
54 ENA_REGS_RESET_OS_TRIGGER = 9,
55
56 ENA_REGS_RESET_OS_NETDEV_WD = 10,
57
58 ENA_REGS_RESET_SHUTDOWN = 11,
59
60 ENA_REGS_RESET_USER_TRIGGER = 12,
61
62 ENA_REGS_RESET_GENERIC = 13,
63
64 ENA_REGS_RESET_MISS_INTERRUPT = 14,
65}; 51};
66 52
67/* ena_registers offsets */ 53/* ena_registers offsets */
68#define ENA_REGS_VERSION_OFF 0x0 54
69#define ENA_REGS_CONTROLLER_VERSION_OFF 0x4 55/* 0 base */
70#define ENA_REGS_CAPS_OFF 0x8 56#define ENA_REGS_VERSION_OFF 0x0
71#define ENA_REGS_CAPS_EXT_OFF 0xc 57#define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
72#define ENA_REGS_AQ_BASE_LO_OFF 0x10 58#define ENA_REGS_CAPS_OFF 0x8
73#define ENA_REGS_AQ_BASE_HI_OFF 0x14 59#define ENA_REGS_CAPS_EXT_OFF 0xc
74#define ENA_REGS_AQ_CAPS_OFF 0x18 60#define ENA_REGS_AQ_BASE_LO_OFF 0x10
75#define ENA_REGS_ACQ_BASE_LO_OFF 0x20 61#define ENA_REGS_AQ_BASE_HI_OFF 0x14
76#define ENA_REGS_ACQ_BASE_HI_OFF 0x24 62#define ENA_REGS_AQ_CAPS_OFF 0x18
77#define ENA_REGS_ACQ_CAPS_OFF 0x28 63#define ENA_REGS_ACQ_BASE_LO_OFF 0x20
78#define ENA_REGS_AQ_DB_OFF 0x2c 64#define ENA_REGS_ACQ_BASE_HI_OFF 0x24
79#define ENA_REGS_ACQ_TAIL_OFF 0x30 65#define ENA_REGS_ACQ_CAPS_OFF 0x28
80#define ENA_REGS_AENQ_CAPS_OFF 0x34 66#define ENA_REGS_AQ_DB_OFF 0x2c
81#define ENA_REGS_AENQ_BASE_LO_OFF 0x38 67#define ENA_REGS_ACQ_TAIL_OFF 0x30
82#define ENA_REGS_AENQ_BASE_HI_OFF 0x3c 68#define ENA_REGS_AENQ_CAPS_OFF 0x34
83#define ENA_REGS_AENQ_HEAD_DB_OFF 0x40 69#define ENA_REGS_AENQ_BASE_LO_OFF 0x38
84#define ENA_REGS_AENQ_TAIL_OFF 0x44 70#define ENA_REGS_AENQ_BASE_HI_OFF 0x3c
85#define ENA_REGS_INTR_MASK_OFF 0x4c 71#define ENA_REGS_AENQ_HEAD_DB_OFF 0x40
86#define ENA_REGS_DEV_CTL_OFF 0x54 72#define ENA_REGS_AENQ_TAIL_OFF 0x44
87#define ENA_REGS_DEV_STS_OFF 0x58 73#define ENA_REGS_INTR_MASK_OFF 0x4c
88#define ENA_REGS_MMIO_REG_READ_OFF 0x5c 74#define ENA_REGS_DEV_CTL_OFF 0x54
89#define ENA_REGS_MMIO_RESP_LO_OFF 0x60 75#define ENA_REGS_DEV_STS_OFF 0x58
90#define ENA_REGS_MMIO_RESP_HI_OFF 0x64 76#define ENA_REGS_MMIO_REG_READ_OFF 0x5c
91#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68 77#define ENA_REGS_MMIO_RESP_LO_OFF 0x60
78#define ENA_REGS_MMIO_RESP_HI_OFF 0x64
79#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68
92 80
93/* version register */ 81/* version register */
94#define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff 82#define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff
95#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8 83#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8
96#define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 84#define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00
97 85
98/* controller_version register */ 86/* controller_version register */
99#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 87#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff
100#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8 88#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8
101#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 89#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00
102#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16 90#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16
103#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 91#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000
104#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24 92#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24
105#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 93#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000
106 94
107/* caps register */ 95/* caps register */
108#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 96#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1
109#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1 97#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1
110#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 98#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
111#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8 99#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
112#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 100#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
113#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16 101#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
114#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 102#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
115 103
116/* aq_caps register */ 104/* aq_caps register */
117#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 105#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
118#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16 106#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16
119#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 107#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000
120 108
121/* acq_caps register */ 109/* acq_caps register */
122#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 110#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff
123#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16 111#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16
124#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000 112#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000
125 113
126/* aenq_caps register */ 114/* aenq_caps register */
127#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 115#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff
128#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16 116#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16
129#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000 117#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000
130 118
131/* dev_ctl register */ 119/* dev_ctl register */
132#define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 120#define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1
133#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1 121#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1
134#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 122#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2
135#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2 123#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2
136#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4 124#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
137#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3 125#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
138#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8 126#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
139#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28 127#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28
140#define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000 128#define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
141 129
142/* dev_sts register */ 130/* dev_sts register */
143#define ENA_REGS_DEV_STS_READY_MASK 0x1 131#define ENA_REGS_DEV_STS_READY_MASK 0x1
144#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 132#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1
145#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 133#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2
146#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 134#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2
147#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 135#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4
148#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 136#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3
149#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 137#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8
150#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4 138#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4
151#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 139#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10
152#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5 140#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5
153#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 141#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20
154#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 142#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6
155#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 143#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40
156#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 144#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7
157#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 145#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80
158 146
159/* mmio_reg_read register */ 147/* mmio_reg_read register */
160#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 148#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff
161#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16 149#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16
162#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 150#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000
163 151
164/* rss_ind_entry_update register */ 152/* rss_ind_entry_update register */
165#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff 153#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff
166#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16 154#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16
167#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000 155#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000
168 156
169#endif /*_ENA_REGS_H_ */ 157#endif /*_ENA_REGS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 22:51:21 -0400