diff options
author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2018-02-27 12:12:46 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-03-07 16:28:32 -0500 |
commit | bd9bc355be45dd2295ca746aa05b058be4cf94cc (patch) | |
tree | fefe45a0d1266675bc5e7ab0727eaf05f61c94e7 | |
parent | 9fe8f03bc0227fb573cc3e5b99eb34e19e405ab6 (diff) |
drm/amd/display: Fix takover from VGA mode
HW Engineer's Notes:
During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
VGA_TEST_ENABLE, to leave it in the same state as before.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 |
2 files changed, 18 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index b73db9e78437..ad7131d6f821 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | |||
@@ -236,6 +236,7 @@ | |||
236 | SR(D2VGA_CONTROL), \ | 236 | SR(D2VGA_CONTROL), \ |
237 | SR(D3VGA_CONTROL), \ | 237 | SR(D3VGA_CONTROL), \ |
238 | SR(D4VGA_CONTROL), \ | 238 | SR(D4VGA_CONTROL), \ |
239 | SR(VGA_TEST_CONTROL), \ | ||
239 | SR(DC_IP_REQUEST_CNTL), \ | 240 | SR(DC_IP_REQUEST_CNTL), \ |
240 | BL_REG_LIST() | 241 | BL_REG_LIST() |
241 | 242 | ||
@@ -337,6 +338,7 @@ struct dce_hwseq_registers { | |||
337 | uint32_t D2VGA_CONTROL; | 338 | uint32_t D2VGA_CONTROL; |
338 | uint32_t D3VGA_CONTROL; | 339 | uint32_t D3VGA_CONTROL; |
339 | uint32_t D4VGA_CONTROL; | 340 | uint32_t D4VGA_CONTROL; |
341 | uint32_t VGA_TEST_CONTROL; | ||
340 | /* MMHUB registers. read only. temporary hack */ | 342 | /* MMHUB registers. read only. temporary hack */ |
341 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; | 343 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; |
342 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; | 344 | uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; |
@@ -494,7 +496,9 @@ struct dce_hwseq_registers { | |||
494 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ | 496 | HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ |
495 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ | 497 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ |
496 | HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ | 498 | HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ |
497 | HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) | 499 | HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \ |
500 | HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ | ||
501 | HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) | ||
498 | 502 | ||
499 | #define HWSEQ_REG_FIELD_LIST(type) \ | 503 | #define HWSEQ_REG_FIELD_LIST(type) \ |
500 | type DCFE_CLOCK_ENABLE; \ | 504 | type DCFE_CLOCK_ENABLE; \ |
@@ -583,7 +587,9 @@ struct dce_hwseq_registers { | |||
583 | type DCFCLK_GATE_DIS; \ | 587 | type DCFCLK_GATE_DIS; \ |
584 | type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ | 588 | type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ |
585 | type DENTIST_DPPCLK_WDIVIDER; \ | 589 | type DENTIST_DPPCLK_WDIVIDER; \ |
586 | type DENTIST_DISPCLK_WDIVIDER; | 590 | type DENTIST_DISPCLK_WDIVIDER; \ |
591 | type VGA_TEST_ENABLE; \ | ||
592 | type VGA_TEST_RENDER_START; | ||
587 | 593 | ||
588 | struct dce_hwseq_shift { | 594 | struct dce_hwseq_shift { |
589 | HWSEQ_REG_FIELD_LIST(uint8_t) | 595 | HWSEQ_REG_FIELD_LIST(uint8_t) |
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7b959fa2351e..f07a8a3d5c25 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -242,6 +242,16 @@ static void disable_vga( | |||
242 | REG_WRITE(D2VGA_CONTROL, 0); | 242 | REG_WRITE(D2VGA_CONTROL, 0); |
243 | REG_WRITE(D3VGA_CONTROL, 0); | 243 | REG_WRITE(D3VGA_CONTROL, 0); |
244 | REG_WRITE(D4VGA_CONTROL, 0); | 244 | REG_WRITE(D4VGA_CONTROL, 0); |
245 | |||
246 | /* HW Engineer's Notes: | ||
247 | * During switch from vga->extended, if we set the VGA_TEST_ENABLE and | ||
248 | * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. | ||
249 | * | ||
250 | * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset | ||
251 | * VGA_TEST_ENABLE, to leave it in the same state as before. | ||
252 | */ | ||
253 | REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1); | ||
254 | REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1); | ||
245 | } | 255 | } |
246 | 256 | ||
247 | static void dpp_pg_control( | 257 | static void dpp_pg_control( |