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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:21 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:46 -0400
commitbd70563f015a5204c62a52a87a35c32377940187 (patch)
treeae2382c2e4fdc3ba32dff11b4f993520c9b42e6a
parent14d74acafb15fd3fac16eef89de7643cddd01775 (diff)
drm/nouveau/dma: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/class.h10
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h15
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c138
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/dma/gf110.c)21
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h19
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c (renamed from drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf110.c)30
22 files changed, 162 insertions, 242 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index 1b85ffe629aa..95a64d89547c 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -251,13 +251,13 @@ struct gf100_dma_v0 {
251 __u8 pad03[5]; 251 __u8 pad03[5];
252}; 252};
253 253
254struct gf110_dma_v0 { 254struct gf119_dma_v0 {
255 __u8 version; 255 __u8 version;
256#define GF110_DMA_V0_PAGE_LP 0x00 256#define GF119_DMA_V0_PAGE_LP 0x00
257#define GF110_DMA_V0_PAGE_SP 0x01 257#define GF119_DMA_V0_PAGE_SP 0x01
258 __u8 page; 258 __u8 page;
259#define GF110_DMA_V0_KIND_PITCH 0x00 259#define GF119_DMA_V0_KIND_PITCH 0x00
260#define GF110_DMA_V0_KIND_VM 0xff 260#define GF119_DMA_V0_KIND_VM 0xff
261 __u8 kind; 261 __u8 kind;
262 __u8 pad03[5]; 262 __u8 pad03[5];
263}; 263};
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
index 7439a02bf7c9..114bfb737a81 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
@@ -2,7 +2,6 @@
2#define __NVKM_DMA_H__ 2#define __NVKM_DMA_H__
3#include <core/engine.h> 3#include <core/engine.h>
4struct nvkm_client; 4struct nvkm_client;
5struct nvkm_gpuobj;
6 5
7struct nvkm_dmaobj { 6struct nvkm_dmaobj {
8 const struct nvkm_dmaobj_func *func; 7 const struct nvkm_dmaobj_func *func;
@@ -18,20 +17,16 @@ struct nvkm_dmaobj {
18 u64 handle; /*XXX HANDLE MERGE */ 17 u64 handle; /*XXX HANDLE MERGE */
19}; 18};
20 19
21struct nvkm_dmaobj_func {
22 int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align,
23 struct nvkm_gpuobj **);
24};
25
26struct nvkm_dma { 20struct nvkm_dma {
21 const struct nvkm_dma_func *func;
27 struct nvkm_engine engine; 22 struct nvkm_engine engine;
28}; 23};
29 24
30struct nvkm_dmaobj * 25struct nvkm_dmaobj *
31nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object); 26nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object);
32 27
33extern struct nvkm_oclass *nv04_dmaeng_oclass; 28int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
34extern struct nvkm_oclass *nv50_dmaeng_oclass; 29int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
35extern struct nvkm_oclass *gf100_dmaeng_oclass; 30int gf100_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
36extern struct nvkm_oclass *gf110_dmaeng_oclass; 31int gf119_dma_new(struct nvkm_device *, int, struct nvkm_dma **);
37#endif 32#endif
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 817ce09acb19..57b13602b2c5 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -2339,7 +2339,7 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin
2339 union { 2339 union {
2340 struct nv50_dma_v0 nv50; 2340 struct nv50_dma_v0 nv50;
2341 struct gf100_dma_v0 gf100; 2341 struct gf100_dma_v0 gf100;
2342 struct gf110_dma_v0 gf110; 2342 struct gf119_dma_v0 gf119;
2343 }; 2343 };
2344 } args = {}; 2344 } args = {};
2345 struct nv50_fbdma *fbdma; 2345 struct nv50_fbdma *fbdma;
@@ -2375,9 +2375,9 @@ nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kin
2375 args.gf100.kind = kind; 2375 args.gf100.kind = kind;
2376 size += sizeof(args.gf100); 2376 size += sizeof(args.gf100);
2377 } else { 2377 } else {
2378 args.gf110.page = GF110_DMA_V0_PAGE_LP; 2378 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2379 args.gf110.kind = kind; 2379 args.gf119.kind = kind;
2380 size += sizeof(args.gf110); 2380 size += sizeof(args.gf119);
2381 } 2381 }
2382 2382
2383 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 2383 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index e9ed83563028..fa4a1f00499c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -87,7 +87,7 @@ nv4_chipset = {
87 .mmu = nv04_mmu_new, 87 .mmu = nv04_mmu_new,
88 .timer = nv04_timer_new, 88 .timer = nv04_timer_new,
89// .disp = nv04_disp_new, 89// .disp = nv04_disp_new,
90// .dma = nv04_dma_new, 90 .dma = nv04_dma_new,
91// .fifo = nv04_fifo_new, 91// .fifo = nv04_fifo_new,
92// .gr = nv04_gr_new, 92// .gr = nv04_gr_new,
93// .sw = nv04_sw_new, 93// .sw = nv04_sw_new,
@@ -107,7 +107,7 @@ nv5_chipset = {
107 .mmu = nv04_mmu_new, 107 .mmu = nv04_mmu_new,
108 .timer = nv04_timer_new, 108 .timer = nv04_timer_new,
109// .disp = nv04_disp_new, 109// .disp = nv04_disp_new,
110// .dma = nv04_dma_new, 110 .dma = nv04_dma_new,
111// .fifo = nv04_fifo_new, 111// .fifo = nv04_fifo_new,
112// .gr = nv04_gr_new, 112// .gr = nv04_gr_new,
113// .sw = nv04_sw_new, 113// .sw = nv04_sw_new,
@@ -128,7 +128,7 @@ nv10_chipset = {
128 .mmu = nv04_mmu_new, 128 .mmu = nv04_mmu_new,
129 .timer = nv04_timer_new, 129 .timer = nv04_timer_new,
130// .disp = nv04_disp_new, 130// .disp = nv04_disp_new,
131// .dma = nv04_dma_new, 131 .dma = nv04_dma_new,
132// .gr = nv10_gr_new, 132// .gr = nv10_gr_new,
133}; 133};
134 134
@@ -147,7 +147,7 @@ nv11_chipset = {
147 .mmu = nv04_mmu_new, 147 .mmu = nv04_mmu_new,
148 .timer = nv04_timer_new, 148 .timer = nv04_timer_new,
149// .disp = nv04_disp_new, 149// .disp = nv04_disp_new,
150// .dma = nv04_dma_new, 150 .dma = nv04_dma_new,
151// .fifo = nv10_fifo_new, 151// .fifo = nv10_fifo_new,
152// .gr = nv10_gr_new, 152// .gr = nv10_gr_new,
153// .sw = nv10_sw_new, 153// .sw = nv10_sw_new,
@@ -168,7 +168,7 @@ nv15_chipset = {
168 .mmu = nv04_mmu_new, 168 .mmu = nv04_mmu_new,
169 .timer = nv04_timer_new, 169 .timer = nv04_timer_new,
170// .disp = nv04_disp_new, 170// .disp = nv04_disp_new,
171// .dma = nv04_dma_new, 171 .dma = nv04_dma_new,
172// .fifo = nv10_fifo_new, 172// .fifo = nv10_fifo_new,
173// .gr = nv10_gr_new, 173// .gr = nv10_gr_new,
174// .sw = nv10_sw_new, 174// .sw = nv10_sw_new,
@@ -189,7 +189,7 @@ nv17_chipset = {
189 .mmu = nv04_mmu_new, 189 .mmu = nv04_mmu_new,
190 .timer = nv04_timer_new, 190 .timer = nv04_timer_new,
191// .disp = nv04_disp_new, 191// .disp = nv04_disp_new,
192// .dma = nv04_dma_new, 192 .dma = nv04_dma_new,
193// .fifo = nv17_fifo_new, 193// .fifo = nv17_fifo_new,
194// .gr = nv10_gr_new, 194// .gr = nv10_gr_new,
195// .sw = nv10_sw_new, 195// .sw = nv10_sw_new,
@@ -210,7 +210,7 @@ nv18_chipset = {
210 .mmu = nv04_mmu_new, 210 .mmu = nv04_mmu_new,
211 .timer = nv04_timer_new, 211 .timer = nv04_timer_new,
212// .disp = nv04_disp_new, 212// .disp = nv04_disp_new,
213// .dma = nv04_dma_new, 213 .dma = nv04_dma_new,
214// .fifo = nv17_fifo_new, 214// .fifo = nv17_fifo_new,
215// .gr = nv10_gr_new, 215// .gr = nv10_gr_new,
216// .sw = nv10_sw_new, 216// .sw = nv10_sw_new,
@@ -231,7 +231,7 @@ nv1a_chipset = {
231 .mmu = nv04_mmu_new, 231 .mmu = nv04_mmu_new,
232 .timer = nv04_timer_new, 232 .timer = nv04_timer_new,
233// .disp = nv04_disp_new, 233// .disp = nv04_disp_new,
234// .dma = nv04_dma_new, 234 .dma = nv04_dma_new,
235// .fifo = nv10_fifo_new, 235// .fifo = nv10_fifo_new,
236// .gr = nv10_gr_new, 236// .gr = nv10_gr_new,
237// .sw = nv10_sw_new, 237// .sw = nv10_sw_new,
@@ -252,7 +252,7 @@ nv1f_chipset = {
252 .mmu = nv04_mmu_new, 252 .mmu = nv04_mmu_new,
253 .timer = nv04_timer_new, 253 .timer = nv04_timer_new,
254// .disp = nv04_disp_new, 254// .disp = nv04_disp_new,
255// .dma = nv04_dma_new, 255 .dma = nv04_dma_new,
256// .fifo = nv17_fifo_new, 256// .fifo = nv17_fifo_new,
257// .gr = nv10_gr_new, 257// .gr = nv10_gr_new,
258// .sw = nv10_sw_new, 258// .sw = nv10_sw_new,
@@ -273,7 +273,7 @@ nv20_chipset = {
273 .mmu = nv04_mmu_new, 273 .mmu = nv04_mmu_new,
274 .timer = nv04_timer_new, 274 .timer = nv04_timer_new,
275// .disp = nv04_disp_new, 275// .disp = nv04_disp_new,
276// .dma = nv04_dma_new, 276 .dma = nv04_dma_new,
277// .fifo = nv17_fifo_new, 277// .fifo = nv17_fifo_new,
278// .gr = nv20_gr_new, 278// .gr = nv20_gr_new,
279// .sw = nv10_sw_new, 279// .sw = nv10_sw_new,
@@ -294,7 +294,7 @@ nv25_chipset = {
294 .mmu = nv04_mmu_new, 294 .mmu = nv04_mmu_new,
295 .timer = nv04_timer_new, 295 .timer = nv04_timer_new,
296// .disp = nv04_disp_new, 296// .disp = nv04_disp_new,
297// .dma = nv04_dma_new, 297 .dma = nv04_dma_new,
298// .fifo = nv17_fifo_new, 298// .fifo = nv17_fifo_new,
299// .gr = nv25_gr_new, 299// .gr = nv25_gr_new,
300// .sw = nv10_sw_new, 300// .sw = nv10_sw_new,
@@ -315,7 +315,7 @@ nv28_chipset = {
315 .mmu = nv04_mmu_new, 315 .mmu = nv04_mmu_new,
316 .timer = nv04_timer_new, 316 .timer = nv04_timer_new,
317// .disp = nv04_disp_new, 317// .disp = nv04_disp_new,
318// .dma = nv04_dma_new, 318 .dma = nv04_dma_new,
319// .fifo = nv17_fifo_new, 319// .fifo = nv17_fifo_new,
320// .gr = nv25_gr_new, 320// .gr = nv25_gr_new,
321// .sw = nv10_sw_new, 321// .sw = nv10_sw_new,
@@ -336,7 +336,7 @@ nv2a_chipset = {
336 .mmu = nv04_mmu_new, 336 .mmu = nv04_mmu_new,
337 .timer = nv04_timer_new, 337 .timer = nv04_timer_new,
338// .disp = nv04_disp_new, 338// .disp = nv04_disp_new,
339// .dma = nv04_dma_new, 339 .dma = nv04_dma_new,
340// .fifo = nv17_fifo_new, 340// .fifo = nv17_fifo_new,
341// .gr = nv2a_gr_new, 341// .gr = nv2a_gr_new,
342// .sw = nv10_sw_new, 342// .sw = nv10_sw_new,
@@ -357,7 +357,7 @@ nv30_chipset = {
357 .mmu = nv04_mmu_new, 357 .mmu = nv04_mmu_new,
358 .timer = nv04_timer_new, 358 .timer = nv04_timer_new,
359// .disp = nv04_disp_new, 359// .disp = nv04_disp_new,
360// .dma = nv04_dma_new, 360 .dma = nv04_dma_new,
361// .fifo = nv17_fifo_new, 361// .fifo = nv17_fifo_new,
362// .gr = nv30_gr_new, 362// .gr = nv30_gr_new,
363// .sw = nv10_sw_new, 363// .sw = nv10_sw_new,
@@ -378,7 +378,7 @@ nv31_chipset = {
378 .mmu = nv04_mmu_new, 378 .mmu = nv04_mmu_new,
379 .timer = nv04_timer_new, 379 .timer = nv04_timer_new,
380// .disp = nv04_disp_new, 380// .disp = nv04_disp_new,
381// .dma = nv04_dma_new, 381 .dma = nv04_dma_new,
382// .fifo = nv17_fifo_new, 382// .fifo = nv17_fifo_new,
383// .gr = nv30_gr_new, 383// .gr = nv30_gr_new,
384// .mpeg = nv31_mpeg_new, 384// .mpeg = nv31_mpeg_new,
@@ -400,7 +400,7 @@ nv34_chipset = {
400 .mmu = nv04_mmu_new, 400 .mmu = nv04_mmu_new,
401 .timer = nv04_timer_new, 401 .timer = nv04_timer_new,
402// .disp = nv04_disp_new, 402// .disp = nv04_disp_new,
403// .dma = nv04_dma_new, 403 .dma = nv04_dma_new,
404// .fifo = nv17_fifo_new, 404// .fifo = nv17_fifo_new,
405// .gr = nv34_gr_new, 405// .gr = nv34_gr_new,
406// .mpeg = nv31_mpeg_new, 406// .mpeg = nv31_mpeg_new,
@@ -422,7 +422,7 @@ nv35_chipset = {
422 .mmu = nv04_mmu_new, 422 .mmu = nv04_mmu_new,
423 .timer = nv04_timer_new, 423 .timer = nv04_timer_new,
424// .disp = nv04_disp_new, 424// .disp = nv04_disp_new,
425// .dma = nv04_dma_new, 425 .dma = nv04_dma_new,
426// .fifo = nv17_fifo_new, 426// .fifo = nv17_fifo_new,
427// .gr = nv35_gr_new, 427// .gr = nv35_gr_new,
428// .sw = nv10_sw_new, 428// .sw = nv10_sw_new,
@@ -443,7 +443,7 @@ nv36_chipset = {
443 .mmu = nv04_mmu_new, 443 .mmu = nv04_mmu_new,
444 .timer = nv04_timer_new, 444 .timer = nv04_timer_new,
445// .disp = nv04_disp_new, 445// .disp = nv04_disp_new,
446// .dma = nv04_dma_new, 446 .dma = nv04_dma_new,
447// .fifo = nv17_fifo_new, 447// .fifo = nv17_fifo_new,
448// .gr = nv35_gr_new, 448// .gr = nv35_gr_new,
449// .mpeg = nv31_mpeg_new, 449// .mpeg = nv31_mpeg_new,
@@ -467,7 +467,7 @@ nv40_chipset = {
467 .timer = nv40_timer_new, 467 .timer = nv40_timer_new,
468 .volt = nv40_volt_new, 468 .volt = nv40_volt_new,
469// .disp = nv04_disp_new, 469// .disp = nv04_disp_new,
470// .dma = nv04_dma_new, 470 .dma = nv04_dma_new,
471// .fifo = nv40_fifo_new, 471// .fifo = nv40_fifo_new,
472// .gr = nv40_gr_new, 472// .gr = nv40_gr_new,
473// .mpeg = nv40_mpeg_new, 473// .mpeg = nv40_mpeg_new,
@@ -492,7 +492,7 @@ nv41_chipset = {
492 .timer = nv41_timer_new, 492 .timer = nv41_timer_new,
493 .volt = nv40_volt_new, 493 .volt = nv40_volt_new,
494// .disp = nv04_disp_new, 494// .disp = nv04_disp_new,
495// .dma = nv04_dma_new, 495 .dma = nv04_dma_new,
496// .fifo = nv40_fifo_new, 496// .fifo = nv40_fifo_new,
497// .gr = nv40_gr_new, 497// .gr = nv40_gr_new,
498// .mpeg = nv40_mpeg_new, 498// .mpeg = nv40_mpeg_new,
@@ -517,7 +517,7 @@ nv42_chipset = {
517 .timer = nv41_timer_new, 517 .timer = nv41_timer_new,
518 .volt = nv40_volt_new, 518 .volt = nv40_volt_new,
519// .disp = nv04_disp_new, 519// .disp = nv04_disp_new,
520// .dma = nv04_dma_new, 520 .dma = nv04_dma_new,
521// .fifo = nv40_fifo_new, 521// .fifo = nv40_fifo_new,
522// .gr = nv40_gr_new, 522// .gr = nv40_gr_new,
523// .mpeg = nv40_mpeg_new, 523// .mpeg = nv40_mpeg_new,
@@ -542,7 +542,7 @@ nv43_chipset = {
542 .timer = nv41_timer_new, 542 .timer = nv41_timer_new,
543 .volt = nv40_volt_new, 543 .volt = nv40_volt_new,
544// .disp = nv04_disp_new, 544// .disp = nv04_disp_new,
545// .dma = nv04_dma_new, 545 .dma = nv04_dma_new,
546// .fifo = nv40_fifo_new, 546// .fifo = nv40_fifo_new,
547// .gr = nv40_gr_new, 547// .gr = nv40_gr_new,
548// .mpeg = nv40_mpeg_new, 548// .mpeg = nv40_mpeg_new,
@@ -567,7 +567,7 @@ nv44_chipset = {
567 .timer = nv41_timer_new, 567 .timer = nv41_timer_new,
568 .volt = nv40_volt_new, 568 .volt = nv40_volt_new,
569// .disp = nv04_disp_new, 569// .disp = nv04_disp_new,
570// .dma = nv04_dma_new, 570 .dma = nv04_dma_new,
571// .fifo = nv40_fifo_new, 571// .fifo = nv40_fifo_new,
572// .gr = nv40_gr_new, 572// .gr = nv40_gr_new,
573// .mpeg = nv44_mpeg_new, 573// .mpeg = nv44_mpeg_new,
@@ -592,7 +592,7 @@ nv45_chipset = {
592 .timer = nv41_timer_new, 592 .timer = nv41_timer_new,
593 .volt = nv40_volt_new, 593 .volt = nv40_volt_new,
594// .disp = nv04_disp_new, 594// .disp = nv04_disp_new,
595// .dma = nv04_dma_new, 595 .dma = nv04_dma_new,
596// .fifo = nv40_fifo_new, 596// .fifo = nv40_fifo_new,
597// .gr = nv40_gr_new, 597// .gr = nv40_gr_new,
598// .mpeg = nv44_mpeg_new, 598// .mpeg = nv44_mpeg_new,
@@ -617,7 +617,7 @@ nv46_chipset = {
617 .timer = nv41_timer_new, 617 .timer = nv41_timer_new,
618 .volt = nv40_volt_new, 618 .volt = nv40_volt_new,
619// .disp = nv04_disp_new, 619// .disp = nv04_disp_new,
620// .dma = nv04_dma_new, 620 .dma = nv04_dma_new,
621// .fifo = nv40_fifo_new, 621// .fifo = nv40_fifo_new,
622// .gr = nv40_gr_new, 622// .gr = nv40_gr_new,
623// .mpeg = nv44_mpeg_new, 623// .mpeg = nv44_mpeg_new,
@@ -642,7 +642,7 @@ nv47_chipset = {
642 .timer = nv41_timer_new, 642 .timer = nv41_timer_new,
643 .volt = nv40_volt_new, 643 .volt = nv40_volt_new,
644// .disp = nv04_disp_new, 644// .disp = nv04_disp_new,
645// .dma = nv04_dma_new, 645 .dma = nv04_dma_new,
646// .fifo = nv40_fifo_new, 646// .fifo = nv40_fifo_new,
647// .gr = nv40_gr_new, 647// .gr = nv40_gr_new,
648// .mpeg = nv44_mpeg_new, 648// .mpeg = nv44_mpeg_new,
@@ -667,7 +667,7 @@ nv49_chipset = {
667 .timer = nv41_timer_new, 667 .timer = nv41_timer_new,
668 .volt = nv40_volt_new, 668 .volt = nv40_volt_new,
669// .disp = nv04_disp_new, 669// .disp = nv04_disp_new,
670// .dma = nv04_dma_new, 670 .dma = nv04_dma_new,
671// .fifo = nv40_fifo_new, 671// .fifo = nv40_fifo_new,
672// .gr = nv40_gr_new, 672// .gr = nv40_gr_new,
673// .mpeg = nv44_mpeg_new, 673// .mpeg = nv44_mpeg_new,
@@ -692,7 +692,7 @@ nv4a_chipset = {
692 .timer = nv41_timer_new, 692 .timer = nv41_timer_new,
693 .volt = nv40_volt_new, 693 .volt = nv40_volt_new,
694// .disp = nv04_disp_new, 694// .disp = nv04_disp_new,
695// .dma = nv04_dma_new, 695 .dma = nv04_dma_new,
696// .fifo = nv40_fifo_new, 696// .fifo = nv40_fifo_new,
697// .gr = nv40_gr_new, 697// .gr = nv40_gr_new,
698// .mpeg = nv44_mpeg_new, 698// .mpeg = nv44_mpeg_new,
@@ -717,7 +717,7 @@ nv4b_chipset = {
717 .timer = nv41_timer_new, 717 .timer = nv41_timer_new,
718 .volt = nv40_volt_new, 718 .volt = nv40_volt_new,
719// .disp = nv04_disp_new, 719// .disp = nv04_disp_new,
720// .dma = nv04_dma_new, 720 .dma = nv04_dma_new,
721// .fifo = nv40_fifo_new, 721// .fifo = nv40_fifo_new,
722// .gr = nv40_gr_new, 722// .gr = nv40_gr_new,
723// .mpeg = nv44_mpeg_new, 723// .mpeg = nv44_mpeg_new,
@@ -742,7 +742,7 @@ nv4c_chipset = {
742 .timer = nv41_timer_new, 742 .timer = nv41_timer_new,
743 .volt = nv40_volt_new, 743 .volt = nv40_volt_new,
744// .disp = nv04_disp_new, 744// .disp = nv04_disp_new,
745// .dma = nv04_dma_new, 745 .dma = nv04_dma_new,
746// .fifo = nv40_fifo_new, 746// .fifo = nv40_fifo_new,
747// .gr = nv40_gr_new, 747// .gr = nv40_gr_new,
748// .mpeg = nv44_mpeg_new, 748// .mpeg = nv44_mpeg_new,
@@ -767,7 +767,7 @@ nv4e_chipset = {
767 .timer = nv41_timer_new, 767 .timer = nv41_timer_new,
768 .volt = nv40_volt_new, 768 .volt = nv40_volt_new,
769// .disp = nv04_disp_new, 769// .disp = nv04_disp_new,
770// .dma = nv04_dma_new, 770 .dma = nv04_dma_new,
771// .fifo = nv40_fifo_new, 771// .fifo = nv40_fifo_new,
772// .gr = nv40_gr_new, 772// .gr = nv40_gr_new,
773// .mpeg = nv44_mpeg_new, 773// .mpeg = nv44_mpeg_new,
@@ -795,7 +795,7 @@ nv50_chipset = {
795 .timer = nv41_timer_new, 795 .timer = nv41_timer_new,
796 .volt = nv40_volt_new, 796 .volt = nv40_volt_new,
797// .disp = nv50_disp_new, 797// .disp = nv50_disp_new,
798// .dma = nv50_dma_new, 798 .dma = nv50_dma_new,
799// .fifo = nv50_fifo_new, 799// .fifo = nv50_fifo_new,
800// .gr = nv50_gr_new, 800// .gr = nv50_gr_new,
801// .mpeg = nv50_mpeg_new, 801// .mpeg = nv50_mpeg_new,
@@ -820,7 +820,7 @@ nv63_chipset = {
820 .timer = nv41_timer_new, 820 .timer = nv41_timer_new,
821 .volt = nv40_volt_new, 821 .volt = nv40_volt_new,
822// .disp = nv04_disp_new, 822// .disp = nv04_disp_new,
823// .dma = nv04_dma_new, 823 .dma = nv04_dma_new,
824// .fifo = nv40_fifo_new, 824// .fifo = nv40_fifo_new,
825// .gr = nv40_gr_new, 825// .gr = nv40_gr_new,
826// .mpeg = nv44_mpeg_new, 826// .mpeg = nv44_mpeg_new,
@@ -845,7 +845,7 @@ nv67_chipset = {
845 .timer = nv41_timer_new, 845 .timer = nv41_timer_new,
846 .volt = nv40_volt_new, 846 .volt = nv40_volt_new,
847// .disp = nv04_disp_new, 847// .disp = nv04_disp_new,
848// .dma = nv04_dma_new, 848 .dma = nv04_dma_new,
849// .fifo = nv40_fifo_new, 849// .fifo = nv40_fifo_new,
850// .gr = nv40_gr_new, 850// .gr = nv40_gr_new,
851// .mpeg = nv44_mpeg_new, 851// .mpeg = nv44_mpeg_new,
@@ -870,7 +870,7 @@ nv68_chipset = {
870 .timer = nv41_timer_new, 870 .timer = nv41_timer_new,
871 .volt = nv40_volt_new, 871 .volt = nv40_volt_new,
872// .disp = nv04_disp_new, 872// .disp = nv04_disp_new,
873// .dma = nv04_dma_new, 873 .dma = nv04_dma_new,
874// .fifo = nv40_fifo_new, 874// .fifo = nv40_fifo_new,
875// .gr = nv40_gr_new, 875// .gr = nv40_gr_new,
876// .mpeg = nv44_mpeg_new, 876// .mpeg = nv44_mpeg_new,
@@ -900,7 +900,7 @@ nv84_chipset = {
900 .bsp = g84_bsp_new, 900 .bsp = g84_bsp_new,
901 .cipher = g84_cipher_new, 901 .cipher = g84_cipher_new,
902// .disp = g84_disp_new, 902// .disp = g84_disp_new,
903// .dma = nv50_dma_new, 903 .dma = nv50_dma_new,
904// .fifo = g84_fifo_new, 904// .fifo = g84_fifo_new,
905// .gr = nv50_gr_new, 905// .gr = nv50_gr_new,
906// .mpeg = g84_mpeg_new, 906// .mpeg = g84_mpeg_new,
@@ -931,7 +931,7 @@ nv86_chipset = {
931 .bsp = g84_bsp_new, 931 .bsp = g84_bsp_new,
932 .cipher = g84_cipher_new, 932 .cipher = g84_cipher_new,
933// .disp = g84_disp_new, 933// .disp = g84_disp_new,
934// .dma = nv50_dma_new, 934 .dma = nv50_dma_new,
935// .fifo = g84_fifo_new, 935// .fifo = g84_fifo_new,
936// .gr = nv50_gr_new, 936// .gr = nv50_gr_new,
937// .mpeg = g84_mpeg_new, 937// .mpeg = g84_mpeg_new,
@@ -962,7 +962,7 @@ nv92_chipset = {
962 .bsp = g84_bsp_new, 962 .bsp = g84_bsp_new,
963 .cipher = g84_cipher_new, 963 .cipher = g84_cipher_new,
964// .disp = g84_disp_new, 964// .disp = g84_disp_new,
965// .dma = nv50_dma_new, 965 .dma = nv50_dma_new,
966// .fifo = g84_fifo_new, 966// .fifo = g84_fifo_new,
967// .gr = nv50_gr_new, 967// .gr = nv50_gr_new,
968// .mpeg = g84_mpeg_new, 968// .mpeg = g84_mpeg_new,
@@ -993,7 +993,7 @@ nv94_chipset = {
993 .bsp = g84_bsp_new, 993 .bsp = g84_bsp_new,
994 .cipher = g84_cipher_new, 994 .cipher = g84_cipher_new,
995// .disp = g94_disp_new, 995// .disp = g94_disp_new,
996// .dma = nv50_dma_new, 996 .dma = nv50_dma_new,
997// .fifo = g84_fifo_new, 997// .fifo = g84_fifo_new,
998// .gr = nv50_gr_new, 998// .gr = nv50_gr_new,
999// .mpeg = g84_mpeg_new, 999// .mpeg = g84_mpeg_new,
@@ -1021,7 +1021,7 @@ nv96_chipset = {
1021 .mmu = nv50_mmu_new, 1021 .mmu = nv50_mmu_new,
1022 .bar = g84_bar_new, 1022 .bar = g84_bar_new,
1023 .volt = nv40_volt_new, 1023 .volt = nv40_volt_new,
1024// .dma = nv50_dma_new, 1024 .dma = nv50_dma_new,
1025// .fifo = g84_fifo_new, 1025// .fifo = g84_fifo_new,
1026// .sw = nv50_sw_new, 1026// .sw = nv50_sw_new,
1027// .gr = nv50_gr_new, 1027// .gr = nv50_gr_new,
@@ -1052,7 +1052,7 @@ nv98_chipset = {
1052 .mmu = nv50_mmu_new, 1052 .mmu = nv50_mmu_new,
1053 .bar = g84_bar_new, 1053 .bar = g84_bar_new,
1054 .volt = nv40_volt_new, 1054 .volt = nv40_volt_new,
1055// .dma = nv50_dma_new, 1055 .dma = nv50_dma_new,
1056// .fifo = g84_fifo_new, 1056// .fifo = g84_fifo_new,
1057// .sw = nv50_sw_new, 1057// .sw = nv50_sw_new,
1058// .gr = nv50_gr_new, 1058// .gr = nv50_gr_new,
@@ -1086,7 +1086,7 @@ nva0_chipset = {
1086 .bsp = g84_bsp_new, 1086 .bsp = g84_bsp_new,
1087 .cipher = g84_cipher_new, 1087 .cipher = g84_cipher_new,
1088// .disp = gt200_disp_new, 1088// .disp = gt200_disp_new,
1089// .dma = nv50_dma_new, 1089 .dma = nv50_dma_new,
1090// .fifo = g84_fifo_new, 1090// .fifo = g84_fifo_new,
1091// .gr = nv50_gr_new, 1091// .gr = nv50_gr_new,
1092// .mpeg = g84_mpeg_new, 1092// .mpeg = g84_mpeg_new,
@@ -1117,7 +1117,7 @@ nva3_chipset = {
1117 .volt = nv40_volt_new, 1117 .volt = nv40_volt_new,
1118 .ce[0] = gt215_ce_new, 1118 .ce[0] = gt215_ce_new,
1119// .disp = gt215_disp_new, 1119// .disp = gt215_disp_new,
1120// .dma = nv50_dma_new, 1120 .dma = nv50_dma_new,
1121// .fifo = g84_fifo_new, 1121// .fifo = g84_fifo_new,
1122// .gr = nv50_gr_new, 1122// .gr = nv50_gr_new,
1123// .mpeg = g84_mpeg_new, 1123// .mpeg = g84_mpeg_new,
@@ -1150,7 +1150,7 @@ nva5_chipset = {
1150 .volt = nv40_volt_new, 1150 .volt = nv40_volt_new,
1151 .ce[0] = gt215_ce_new, 1151 .ce[0] = gt215_ce_new,
1152// .disp = gt215_disp_new, 1152// .disp = gt215_disp_new,
1153// .dma = nv50_dma_new, 1153 .dma = nv50_dma_new,
1154// .fifo = g84_fifo_new, 1154// .fifo = g84_fifo_new,
1155// .gr = nv50_gr_new, 1155// .gr = nv50_gr_new,
1156 .mspdec = gt215_mspdec_new, 1156 .mspdec = gt215_mspdec_new,
@@ -1182,7 +1182,7 @@ nva8_chipset = {
1182 .volt = nv40_volt_new, 1182 .volt = nv40_volt_new,
1183 .ce[0] = gt215_ce_new, 1183 .ce[0] = gt215_ce_new,
1184// .disp = gt215_disp_new, 1184// .disp = gt215_disp_new,
1185// .dma = nv50_dma_new, 1185 .dma = nv50_dma_new,
1186// .fifo = g84_fifo_new, 1186// .fifo = g84_fifo_new,
1187// .gr = nv50_gr_new, 1187// .gr = nv50_gr_new,
1188 .mspdec = gt215_mspdec_new, 1188 .mspdec = gt215_mspdec_new,
@@ -1212,7 +1212,7 @@ nvaa_chipset = {
1212 .timer = nv41_timer_new, 1212 .timer = nv41_timer_new,
1213 .volt = nv40_volt_new, 1213 .volt = nv40_volt_new,
1214// .disp = g94_disp_new, 1214// .disp = g94_disp_new,
1215// .dma = nv50_dma_new, 1215 .dma = nv50_dma_new,
1216// .fifo = g84_fifo_new, 1216// .fifo = g84_fifo_new,
1217// .gr = nv50_gr_new, 1217// .gr = nv50_gr_new,
1218 .mspdec = g98_mspdec_new, 1218 .mspdec = g98_mspdec_new,
@@ -1243,7 +1243,7 @@ nvac_chipset = {
1243 .timer = nv41_timer_new, 1243 .timer = nv41_timer_new,
1244 .volt = nv40_volt_new, 1244 .volt = nv40_volt_new,
1245// .disp = g94_disp_new, 1245// .disp = g94_disp_new,
1246// .dma = nv50_dma_new, 1246 .dma = nv50_dma_new,
1247// .fifo = g84_fifo_new, 1247// .fifo = g84_fifo_new,
1248// .gr = nv50_gr_new, 1248// .gr = nv50_gr_new,
1249 .mspdec = g98_mspdec_new, 1249 .mspdec = g98_mspdec_new,
@@ -1276,7 +1276,7 @@ nvaf_chipset = {
1276 .volt = nv40_volt_new, 1276 .volt = nv40_volt_new,
1277 .ce[0] = gt215_ce_new, 1277 .ce[0] = gt215_ce_new,
1278// .disp = gt215_disp_new, 1278// .disp = gt215_disp_new,
1279// .dma = nv50_dma_new, 1279 .dma = nv50_dma_new,
1280// .fifo = g84_fifo_new, 1280// .fifo = g84_fifo_new,
1281// .gr = nv50_gr_new, 1281// .gr = nv50_gr_new,
1282 .mspdec = gt215_mspdec_new, 1282 .mspdec = gt215_mspdec_new,
@@ -1311,7 +1311,7 @@ nvc0_chipset = {
1311 .ce[0] = gf100_ce_new, 1311 .ce[0] = gf100_ce_new,
1312 .ce[1] = gf100_ce_new, 1312 .ce[1] = gf100_ce_new,
1313// .disp = gt215_disp_new, 1313// .disp = gt215_disp_new,
1314// .dma = gf100_dma_new, 1314 .dma = gf100_dma_new,
1315// .fifo = gf100_fifo_new, 1315// .fifo = gf100_fifo_new,
1316// .gr = gf100_gr_new, 1316// .gr = gf100_gr_new,
1317 .mspdec = gf100_mspdec_new, 1317 .mspdec = gf100_mspdec_new,
@@ -1345,7 +1345,7 @@ nvc1_chipset = {
1345 .volt = nv40_volt_new, 1345 .volt = nv40_volt_new,
1346 .ce[0] = gf100_ce_new, 1346 .ce[0] = gf100_ce_new,
1347// .disp = gt215_disp_new, 1347// .disp = gt215_disp_new,
1348// .dma = gf100_dma_new, 1348 .dma = gf100_dma_new,
1349// .fifo = gf100_fifo_new, 1349// .fifo = gf100_fifo_new,
1350// .gr = gf108_gr_new, 1350// .gr = gf108_gr_new,
1351 .mspdec = gf100_mspdec_new, 1351 .mspdec = gf100_mspdec_new,
@@ -1379,7 +1379,7 @@ nvc3_chipset = {
1379 .volt = nv40_volt_new, 1379 .volt = nv40_volt_new,
1380 .ce[0] = gf100_ce_new, 1380 .ce[0] = gf100_ce_new,
1381// .disp = gt215_disp_new, 1381// .disp = gt215_disp_new,
1382// .dma = gf100_dma_new, 1382 .dma = gf100_dma_new,
1383// .fifo = gf100_fifo_new, 1383// .fifo = gf100_fifo_new,
1384// .gr = gf104_gr_new, 1384// .gr = gf104_gr_new,
1385 .mspdec = gf100_mspdec_new, 1385 .mspdec = gf100_mspdec_new,
@@ -1414,7 +1414,7 @@ nvc4_chipset = {
1414 .ce[0] = gf100_ce_new, 1414 .ce[0] = gf100_ce_new,
1415 .ce[1] = gf100_ce_new, 1415 .ce[1] = gf100_ce_new,
1416// .disp = gt215_disp_new, 1416// .disp = gt215_disp_new,
1417// .dma = gf100_dma_new, 1417 .dma = gf100_dma_new,
1418// .fifo = gf100_fifo_new, 1418// .fifo = gf100_fifo_new,
1419// .gr = gf104_gr_new, 1419// .gr = gf104_gr_new,
1420 .mspdec = gf100_mspdec_new, 1420 .mspdec = gf100_mspdec_new,
@@ -1449,7 +1449,7 @@ nvc8_chipset = {
1449 .ce[0] = gf100_ce_new, 1449 .ce[0] = gf100_ce_new,
1450 .ce[1] = gf100_ce_new, 1450 .ce[1] = gf100_ce_new,
1451// .disp = gt215_disp_new, 1451// .disp = gt215_disp_new,
1452// .dma = gf100_dma_new, 1452 .dma = gf100_dma_new,
1453// .fifo = gf100_fifo_new, 1453// .fifo = gf100_fifo_new,
1454// .gr = gf110_gr_new, 1454// .gr = gf110_gr_new,
1455 .mspdec = gf100_mspdec_new, 1455 .mspdec = gf100_mspdec_new,
@@ -1484,7 +1484,7 @@ nvce_chipset = {
1484 .ce[0] = gf100_ce_new, 1484 .ce[0] = gf100_ce_new,
1485 .ce[1] = gf100_ce_new, 1485 .ce[1] = gf100_ce_new,
1486// .disp = gt215_disp_new, 1486// .disp = gt215_disp_new,
1487// .dma = gf100_dma_new, 1487 .dma = gf100_dma_new,
1488// .fifo = gf100_fifo_new, 1488// .fifo = gf100_fifo_new,
1489// .gr = gf104_gr_new, 1489// .gr = gf104_gr_new,
1490 .mspdec = gf100_mspdec_new, 1490 .mspdec = gf100_mspdec_new,
@@ -1518,7 +1518,7 @@ nvcf_chipset = {
1518 .volt = nv40_volt_new, 1518 .volt = nv40_volt_new,
1519 .ce[0] = gf100_ce_new, 1519 .ce[0] = gf100_ce_new,
1520// .disp = gt215_disp_new, 1520// .disp = gt215_disp_new,
1521// .dma = gf100_dma_new, 1521 .dma = gf100_dma_new,
1522// .fifo = gf100_fifo_new, 1522// .fifo = gf100_fifo_new,
1523// .gr = gf104_gr_new, 1523// .gr = gf104_gr_new,
1524 .mspdec = gf100_mspdec_new, 1524 .mspdec = gf100_mspdec_new,
@@ -1550,7 +1550,7 @@ nvd7_chipset = {
1550 .timer = nv41_timer_new, 1550 .timer = nv41_timer_new,
1551 .ce[0] = gf100_ce_new, 1551 .ce[0] = gf100_ce_new,
1552// .disp = gf119_disp_new, 1552// .disp = gf119_disp_new,
1553// .dma = gf119_dma_new, 1553 .dma = gf119_dma_new,
1554// .fifo = gf100_fifo_new, 1554// .fifo = gf100_fifo_new,
1555// .gr = gf117_gr_new, 1555// .gr = gf117_gr_new,
1556 .mspdec = gf100_mspdec_new, 1556 .mspdec = gf100_mspdec_new,
@@ -1584,7 +1584,7 @@ nvd9_chipset = {
1584 .volt = nv40_volt_new, 1584 .volt = nv40_volt_new,
1585 .ce[0] = gf100_ce_new, 1585 .ce[0] = gf100_ce_new,
1586// .disp = gf119_disp_new, 1586// .disp = gf119_disp_new,
1587// .dma = gf119_dma_new, 1587 .dma = gf119_dma_new,
1588// .fifo = gf100_fifo_new, 1588// .fifo = gf100_fifo_new,
1589// .gr = gf119_gr_new, 1589// .gr = gf119_gr_new,
1590 .mspdec = gf100_mspdec_new, 1590 .mspdec = gf100_mspdec_new,
@@ -1620,7 +1620,7 @@ nve4_chipset = {
1620 .ce[1] = gk104_ce_new, 1620 .ce[1] = gk104_ce_new,
1621 .ce[2] = gk104_ce_new, 1621 .ce[2] = gk104_ce_new,
1622// .disp = gk104_disp_new, 1622// .disp = gk104_disp_new,
1623// .dma = gf119_dma_new, 1623 .dma = gf119_dma_new,
1624// .fifo = gk104_fifo_new, 1624// .fifo = gk104_fifo_new,
1625// .gr = gk104_gr_new, 1625// .gr = gk104_gr_new,
1626 .mspdec = gk104_mspdec_new, 1626 .mspdec = gk104_mspdec_new,
@@ -1656,7 +1656,7 @@ nve6_chipset = {
1656 .ce[1] = gk104_ce_new, 1656 .ce[1] = gk104_ce_new,
1657 .ce[2] = gk104_ce_new, 1657 .ce[2] = gk104_ce_new,
1658// .disp = gk104_disp_new, 1658// .disp = gk104_disp_new,
1659// .dma = gf119_dma_new, 1659 .dma = gf119_dma_new,
1660// .fifo = gk104_fifo_new, 1660// .fifo = gk104_fifo_new,
1661// .gr = gk104_gr_new, 1661// .gr = gk104_gr_new,
1662 .mspdec = gk104_mspdec_new, 1662 .mspdec = gk104_mspdec_new,
@@ -1692,7 +1692,7 @@ nve7_chipset = {
1692 .ce[1] = gk104_ce_new, 1692 .ce[1] = gk104_ce_new,
1693 .ce[2] = gk104_ce_new, 1693 .ce[2] = gk104_ce_new,
1694// .disp = gk104_disp_new, 1694// .disp = gk104_disp_new,
1695// .dma = gf119_dma_new, 1695 .dma = gf119_dma_new,
1696// .fifo = gk104_fifo_new, 1696// .fifo = gk104_fifo_new,
1697// .gr = gk104_gr_new, 1697// .gr = gk104_gr_new,
1698 .mspdec = gk104_mspdec_new, 1698 .mspdec = gk104_mspdec_new,
@@ -1719,7 +1719,7 @@ nvea_chipset = {
1719 .timer = gk20a_timer_new, 1719 .timer = gk20a_timer_new,
1720 .volt = gk20a_volt_new, 1720 .volt = gk20a_volt_new,
1721 .ce[2] = gk104_ce_new, 1721 .ce[2] = gk104_ce_new,
1722// .dma = gf119_dma_new, 1722 .dma = gf119_dma_new,
1723// .fifo = gk20a_fifo_new, 1723// .fifo = gk20a_fifo_new,
1724// .gr = gk20a_gr_new, 1724// .gr = gk20a_gr_new,
1725// .pm = gk104_pm_new, 1725// .pm = gk104_pm_new,
@@ -1752,7 +1752,7 @@ nvf0_chipset = {
1752 .ce[1] = gk104_ce_new, 1752 .ce[1] = gk104_ce_new,
1753 .ce[2] = gk104_ce_new, 1753 .ce[2] = gk104_ce_new,
1754// .disp = gk110_disp_new, 1754// .disp = gk110_disp_new,
1755// .dma = gf119_dma_new, 1755 .dma = gf119_dma_new,
1756// .fifo = gk104_fifo_new, 1756// .fifo = gk104_fifo_new,
1757// .gr = gk110_gr_new, 1757// .gr = gk110_gr_new,
1758 .mspdec = gk104_mspdec_new, 1758 .mspdec = gk104_mspdec_new,
@@ -1788,7 +1788,7 @@ nvf1_chipset = {
1788 .ce[1] = gk104_ce_new, 1788 .ce[1] = gk104_ce_new,
1789 .ce[2] = gk104_ce_new, 1789 .ce[2] = gk104_ce_new,
1790// .disp = gk110_disp_new, 1790// .disp = gk110_disp_new,
1791// .dma = gf119_dma_new, 1791 .dma = gf119_dma_new,
1792// .fifo = gk104_fifo_new, 1792// .fifo = gk104_fifo_new,
1793// .gr = gk110b_gr_new, 1793// .gr = gk110b_gr_new,
1794 .mspdec = gk104_mspdec_new, 1794 .mspdec = gk104_mspdec_new,
@@ -1824,7 +1824,7 @@ nv106_chipset = {
1824 .ce[1] = gk104_ce_new, 1824 .ce[1] = gk104_ce_new,
1825 .ce[2] = gk104_ce_new, 1825 .ce[2] = gk104_ce_new,
1826// .disp = gk110_disp_new, 1826// .disp = gk110_disp_new,
1827// .dma = gf119_dma_new, 1827 .dma = gf119_dma_new,
1828// .fifo = gk208_fifo_new, 1828// .fifo = gk208_fifo_new,
1829// .gr = gk208_gr_new, 1829// .gr = gk208_gr_new,
1830 .mspdec = gk104_mspdec_new, 1830 .mspdec = gk104_mspdec_new,
@@ -1859,7 +1859,7 @@ nv108_chipset = {
1859 .ce[1] = gk104_ce_new, 1859 .ce[1] = gk104_ce_new,
1860 .ce[2] = gk104_ce_new, 1860 .ce[2] = gk104_ce_new,
1861// .disp = gk110_disp_new, 1861// .disp = gk110_disp_new,
1862// .dma = gf119_dma_new, 1862 .dma = gf119_dma_new,
1863// .fifo = gk208_fifo_new, 1863// .fifo = gk208_fifo_new,
1864// .gr = gk208_gr_new, 1864// .gr = gk208_gr_new,
1865 .mspdec = gk104_mspdec_new, 1865 .mspdec = gk104_mspdec_new,
@@ -1892,7 +1892,7 @@ nv117_chipset = {
1892 .ce[0] = gk104_ce_new, 1892 .ce[0] = gk104_ce_new,
1893 .ce[2] = gk104_ce_new, 1893 .ce[2] = gk104_ce_new,
1894// .disp = gm107_disp_new, 1894// .disp = gm107_disp_new,
1895// .dma = gf119_dma_new, 1895 .dma = gf119_dma_new,
1896// .fifo = gk208_fifo_new, 1896// .fifo = gk208_fifo_new,
1897// .gr = gm107_gr_new, 1897// .gr = gm107_gr_new,
1898// .sw = gf100_sw_new, 1898// .sw = gf100_sw_new,
@@ -1921,7 +1921,7 @@ nv124_chipset = {
1921 .ce[1] = gm204_ce_new, 1921 .ce[1] = gm204_ce_new,
1922 .ce[2] = gm204_ce_new, 1922 .ce[2] = gm204_ce_new,
1923// .disp = gm204_disp_new, 1923// .disp = gm204_disp_new,
1924// .dma = gf119_dma_new, 1924 .dma = gf119_dma_new,
1925// .fifo = gm204_fifo_new, 1925// .fifo = gm204_fifo_new,
1926// .gr = gm204_gr_new, 1926// .gr = gm204_gr_new,
1927// .sw = gf100_sw_new, 1927// .sw = gf100_sw_new,
@@ -1950,7 +1950,7 @@ nv126_chipset = {
1950 .ce[1] = gm204_ce_new, 1950 .ce[1] = gm204_ce_new,
1951 .ce[2] = gm204_ce_new, 1951 .ce[2] = gm204_ce_new,
1952// .disp = gm204_disp_new, 1952// .disp = gm204_disp_new,
1953// .dma = gf119_dma_new, 1953 .dma = gf119_dma_new,
1954// .fifo = gm204_fifo_new, 1954// .fifo = gm204_fifo_new,
1955// .gr = gm206_gr_new, 1955// .gr = gm206_gr_new,
1956// .sw = gf100_sw_new, 1956// .sw = gf100_sw_new,
@@ -1971,7 +1971,7 @@ nv12b_chipset = {
1971 .mmu = gf100_mmu_new, 1971 .mmu = gf100_mmu_new,
1972 .timer = gk20a_timer_new, 1972 .timer = gk20a_timer_new,
1973 .ce[2] = gm204_ce_new, 1973 .ce[2] = gm204_ce_new,
1974// .dma = gf119_dma_new, 1974 .dma = gf119_dma_new,
1975// .fifo = gm20b_fifo_new, 1975// .fifo = gm20b_fifo_new,
1976// .gr = gm20b_gr_new, 1976// .gr = gm20b_gr_new,
1977// .sw = gf100_sw_new, 1977// .sw = gf100_sw_new,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index 336964a0cd92..3256b3b12e48 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xc0: 30 case 0xc0:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
@@ -36,7 +35,6 @@ gf100_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 35 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
37 break; 36 break;
38 case 0xc4: 37 case 0xc4:
39 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
40 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 38 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
41 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
42 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 40 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
@@ -44,7 +42,6 @@ gf100_identify(struct nvkm_device *device)
44 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 42 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
45 break; 43 break;
46 case 0xc3: 44 case 0xc3:
47 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
48 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 45 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
49 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
50 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 47 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
@@ -52,7 +49,6 @@ gf100_identify(struct nvkm_device *device)
52 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 49 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
53 break; 50 break;
54 case 0xce: 51 case 0xce:
55 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
56 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 52 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
57 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 53 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
58 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 54 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
@@ -60,7 +56,6 @@ gf100_identify(struct nvkm_device *device)
60 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 56 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
61 break; 57 break;
62 case 0xcf: 58 case 0xcf:
63 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
64 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 59 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
65 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 60 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
66 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; 61 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
@@ -68,7 +63,6 @@ gf100_identify(struct nvkm_device *device)
68 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 63 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
69 break; 64 break;
70 case 0xc1: 65 case 0xc1:
71 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
72 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 66 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
73 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 67 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
74 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; 68 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
@@ -76,7 +70,6 @@ gf100_identify(struct nvkm_device *device)
76 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; 70 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
77 break; 71 break;
78 case 0xc8: 72 case 0xc8:
79 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
80 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 73 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
81 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 74 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
82 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; 75 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
@@ -84,7 +77,6 @@ gf100_identify(struct nvkm_device *device)
84 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 77 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
85 break; 78 break;
86 case 0xd9: 79 case 0xd9:
87 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
88 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 80 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
89 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 81 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
90 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; 82 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
@@ -92,7 +84,6 @@ gf100_identify(struct nvkm_device *device)
92 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 84 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
93 break; 85 break;
94 case 0xd7: 86 case 0xd7:
95 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
96 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 87 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
97 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 88 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
98 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; 89 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index 3a9fa9428803..c02474168536 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xe4: 30 case 0xe4:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
@@ -36,7 +35,6 @@ gk104_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 35 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
37 break; 36 break;
38 case 0xe7: 37 case 0xe7:
39 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
40 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 38 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
41 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 39 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
42 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 40 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
@@ -44,7 +42,6 @@ gk104_identify(struct nvkm_device *device)
44 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 42 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
45 break; 43 break;
46 case 0xe6: 44 case 0xe6:
47 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
48 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 45 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
49 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 46 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
50 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; 47 device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
@@ -52,14 +49,12 @@ gk104_identify(struct nvkm_device *device)
52 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 49 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
53 break; 50 break;
54 case 0xea: 51 case 0xea:
55 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
56 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; 52 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
57 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 53 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
58 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; 54 device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass;
59 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 55 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
60 break; 56 break;
61 case 0xf0: 57 case 0xf0:
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 58 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 59 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; 60 device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
@@ -67,7 +62,6 @@ gk104_identify(struct nvkm_device *device)
67 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 62 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
68 break; 63 break;
69 case 0xf1: 64 case 0xf1:
70 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
71 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 65 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
72 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 66 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
73 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; 67 device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
@@ -75,14 +69,12 @@ gk104_identify(struct nvkm_device *device)
75 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 69 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
76 break; 70 break;
77 case 0x106: 71 case 0x106:
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 72 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 73 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; 74 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
82 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass; 75 device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
83 break; 76 break;
84 case 0x108: 77 case 0x108:
85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 78 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 79 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; 80 device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index ec75f91e55cc..825e7cd07983 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
31 31
32#if 0 32#if 0
33#endif 33#endif
34 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
35 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 34 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
36 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 35 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
37 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; 36 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
@@ -48,7 +47,6 @@ gm100_identify(struct nvkm_device *device)
48#endif 47#endif
49#if 0 48#if 0
50#endif 49#endif
51 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
52 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; 50 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
53 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
54 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; 52 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
@@ -63,7 +61,6 @@ gm100_identify(struct nvkm_device *device)
63#endif 61#endif
64#if 0 62#if 0
65#endif 63#endif
66 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
67 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; 64 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 65 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
69 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; 66 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
@@ -73,7 +70,6 @@ gm100_identify(struct nvkm_device *device)
73 break; 70 break;
74 case 0x12b: 71 case 0x12b:
75 72
76 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
77 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; 73 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
78 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 74 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
79 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass; 75 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 1b2ebda82c1f..92c24618d101 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -28,14 +28,12 @@ nv04_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x04: 30 case 0x04:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 34 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
36 break; 35 break;
37 case 0x05: 36 case 0x05:
38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
39 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 37 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
40 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 38 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
41 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; 39 device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index c5ecdddfbce3..17a694d60d7a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -28,54 +28,46 @@ nv10_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x10: 30 case 0x10:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 31 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
33 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 32 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
34 break; 33 break;
35 case 0x15: 34 case 0x15:
36 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
37 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 35 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
38 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 36 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
39 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 37 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
40 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 38 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
41 break; 39 break;
42 case 0x16: 40 case 0x16:
43 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
44 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 41 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
45 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
46 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 43 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
47 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 44 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
48 break; 45 break;
49 case 0x1a: 46 case 0x1a:
50 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
51 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 47 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
52 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 48 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
53 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 49 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
54 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 50 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
55 break; 51 break;
56 case 0x11: 52 case 0x11:
57 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
58 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 53 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
59 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 54 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
60 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 55 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
61 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 56 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
62 break; 57 break;
63 case 0x17: 58 case 0x17:
64 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
65 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 59 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
66 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 60 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
67 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 61 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
68 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 62 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
69 break; 63 break;
70 case 0x1f: 64 case 0x1f:
71 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
72 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 65 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
73 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 66 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
74 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 67 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
75 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 68 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
76 break; 69 break;
77 case 0x18: 70 case 0x18:
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 71 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 72 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 73 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index 104ed4f093b5..6b59530743a1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -28,28 +28,24 @@ nv20_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x20: 30 case 0x20:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 34 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
36 break; 35 break;
37 case 0x25: 36 case 0x25:
38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
39 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 37 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 38 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
41 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 39 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
42 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 40 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
43 break; 41 break;
44 case 0x28: 42 case 0x28:
45 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
46 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 43 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 44 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
48 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; 45 device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
49 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 46 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
50 break; 47 break;
51 case 0x2a: 48 case 0x2a:
52 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
53 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 49 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
54 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
55 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; 51 device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 5ea263c85043..232951b9854e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -28,21 +28,18 @@ nv30_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x30: 30 case 0x30:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 34 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
36 break; 35 break;
37 case 0x35: 36 case 0x35:
38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
39 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 37 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 38 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
41 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 39 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
42 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 40 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
43 break; 41 break;
44 case 0x31: 42 case 0x31:
45 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
46 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 43 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 44 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
48 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; 45 device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
@@ -50,7 +47,6 @@ nv30_identify(struct nvkm_device *device)
50 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 47 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
51 break; 48 break;
52 case 0x36: 49 case 0x36:
53 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
54 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 50 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
55 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 51 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
56 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; 52 device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
@@ -58,7 +54,6 @@ nv30_identify(struct nvkm_device *device)
58 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 54 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
59 break; 55 break;
60 case 0x34: 56 case 0x34:
61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
62 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 57 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
63 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 58 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
64 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; 59 device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 0d6da9716b7b..642000f8b2bb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x40: 30 case 0x40:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -37,7 +36,6 @@ nv40_identify(struct nvkm_device *device)
37 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 36 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
38 break; 37 break;
39 case 0x41: 38 case 0x41:
40 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 39 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
43 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 41 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -46,7 +44,6 @@ nv40_identify(struct nvkm_device *device)
46 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 44 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
47 break; 45 break;
48 case 0x42: 46 case 0x42:
49 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
50 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 47 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
51 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 48 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
52 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 49 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -55,7 +52,6 @@ nv40_identify(struct nvkm_device *device)
55 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 52 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
56 break; 53 break;
57 case 0x43: 54 case 0x43:
58 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
59 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 55 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
60 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 56 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
61 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 57 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -64,7 +60,6 @@ nv40_identify(struct nvkm_device *device)
64 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 60 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
65 break; 61 break;
66 case 0x45: 62 case 0x45:
67 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
68 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
69 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
70 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -73,7 +68,6 @@ nv40_identify(struct nvkm_device *device)
73 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 68 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
74 break; 69 break;
75 case 0x47: 70 case 0x47:
76 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
77 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 71 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
78 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 72 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
79 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 73 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -82,7 +76,6 @@ nv40_identify(struct nvkm_device *device)
82 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 76 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
83 break; 77 break;
84 case 0x49: 78 case 0x49:
85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -91,7 +84,6 @@ nv40_identify(struct nvkm_device *device)
91 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 84 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
92 break; 85 break;
93 case 0x4b: 86 case 0x4b:
94 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
95 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 87 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
96 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 88 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
97 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 89 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -100,7 +92,6 @@ nv40_identify(struct nvkm_device *device)
100 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 92 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
101 break; 93 break;
102 case 0x44: 94 case 0x44:
103 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
104 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 95 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
105 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 96 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
106 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 97 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -109,7 +100,6 @@ nv40_identify(struct nvkm_device *device)
109 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 100 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
110 break; 101 break;
111 case 0x46: 102 case 0x46:
112 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
113 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 103 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
114 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 104 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
115 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 105 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -118,7 +108,6 @@ nv40_identify(struct nvkm_device *device)
118 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 108 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
119 break; 109 break;
120 case 0x4a: 110 case 0x4a:
121 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
122 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 111 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
123 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 112 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
124 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 113 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -127,7 +116,6 @@ nv40_identify(struct nvkm_device *device)
127 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 116 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
128 break; 117 break;
129 case 0x4c: 118 case 0x4c:
130 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
131 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 119 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
132 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 120 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
133 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 121 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -136,7 +124,6 @@ nv40_identify(struct nvkm_device *device)
136 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 124 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
137 break; 125 break;
138 case 0x4e: 126 case 0x4e:
139 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
140 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 127 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
141 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 128 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
142 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 129 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -145,7 +132,6 @@ nv40_identify(struct nvkm_device *device)
145 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 132 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
146 break; 133 break;
147 case 0x63: 134 case 0x63:
148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
149 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 135 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
150 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 136 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
151 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 137 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -154,7 +140,6 @@ nv40_identify(struct nvkm_device *device)
154 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 140 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
155 break; 141 break;
156 case 0x67: 142 case 0x67:
157 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
158 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 143 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
159 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 144 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
160 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 145 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
@@ -163,7 +148,6 @@ nv40_identify(struct nvkm_device *device)
163 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 148 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
164 break; 149 break;
165 case 0x68: 150 case 0x68:
166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
167 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 151 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
168 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 152 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
169 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; 153 device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 087edc8d412c..7e4ef30945e3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x50: 30 case 0x50:
31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
32 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; 31 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
33 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 32 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
34 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 33 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -37,7 +36,6 @@ nv50_identify(struct nvkm_device *device)
37 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; 36 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
38 break; 37 break;
39 case 0x84: 38 case 0x84:
40 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
41 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 39 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
43 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 41 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -46,7 +44,6 @@ nv50_identify(struct nvkm_device *device)
46 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 44 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
47 break; 45 break;
48 case 0x86: 46 case 0x86:
49 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
50 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 47 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
51 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 48 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
52 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 49 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -55,7 +52,6 @@ nv50_identify(struct nvkm_device *device)
55 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 52 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
56 break; 53 break;
57 case 0x92: 54 case 0x92:
58 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
59 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 55 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
60 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 56 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
61 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 57 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -64,7 +60,6 @@ nv50_identify(struct nvkm_device *device)
64 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 60 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
65 break; 61 break;
66 case 0x94: 62 case 0x94:
67 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
68 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
69 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 64 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
70 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 65 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -73,7 +68,6 @@ nv50_identify(struct nvkm_device *device)
73 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 68 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
74 break; 69 break;
75 case 0x96: 70 case 0x96:
76 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
77 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 71 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
78 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 72 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
79 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 73 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -82,7 +76,6 @@ nv50_identify(struct nvkm_device *device)
82 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 76 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
83 break; 77 break;
84 case 0x98: 78 case 0x98:
85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -90,7 +83,6 @@ nv50_identify(struct nvkm_device *device)
90 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 83 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
91 break; 84 break;
92 case 0xa0: 85 case 0xa0:
93 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
94 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 86 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
95 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 87 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
96 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 88 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -99,7 +91,6 @@ nv50_identify(struct nvkm_device *device)
99 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; 91 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
100 break; 92 break;
101 case 0xaa: 93 case 0xaa:
102 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
103 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 94 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
104 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 95 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
105 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 96 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -107,7 +98,6 @@ nv50_identify(struct nvkm_device *device)
107 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 98 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
108 break; 99 break;
109 case 0xac: 100 case 0xac:
110 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
111 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
112 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 102 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
113 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 103 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -115,7 +105,6 @@ nv50_identify(struct nvkm_device *device)
115 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 105 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
116 break; 106 break;
117 case 0xa3: 107 case 0xa3:
118 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
119 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 108 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
120 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 109 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
121 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 110 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -124,7 +113,6 @@ nv50_identify(struct nvkm_device *device)
124 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 113 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
125 break; 114 break;
126 case 0xa5: 115 case 0xa5:
127 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
128 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 116 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
129 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 117 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
130 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 118 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -132,7 +120,6 @@ nv50_identify(struct nvkm_device *device)
132 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 120 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
133 break; 121 break;
134 case 0xa8: 122 case 0xa8:
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 123 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 124 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
@@ -140,7 +127,6 @@ nv50_identify(struct nvkm_device *device)
140 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 127 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
141 break; 128 break;
142 case 0xaf: 129 case 0xaf:
143 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
144 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 130 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
145 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; 131 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
146 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; 132 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild
index bb3a0528b6b5..c4a2ce9b0d71 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild
@@ -2,10 +2,10 @@ nvkm-y += nvkm/engine/dma/base.o
2nvkm-y += nvkm/engine/dma/nv04.o 2nvkm-y += nvkm/engine/dma/nv04.o
3nvkm-y += nvkm/engine/dma/nv50.o 3nvkm-y += nvkm/engine/dma/nv50.o
4nvkm-y += nvkm/engine/dma/gf100.o 4nvkm-y += nvkm/engine/dma/gf100.o
5nvkm-y += nvkm/engine/dma/gf110.o 5nvkm-y += nvkm/engine/dma/gf119.o
6 6
7nvkm-y += nvkm/engine/dma/user.o 7nvkm-y += nvkm/engine/dma/user.o
8nvkm-y += nvkm/engine/dma/usernv04.o 8nvkm-y += nvkm/engine/dma/usernv04.o
9nvkm-y += nvkm/engine/dma/usernv50.o 9nvkm-y += nvkm/engine/dma/usernv50.o
10nvkm-y += nvkm/engine/dma/usergf100.o 10nvkm-y += nvkm/engine/dma/usergf100.o
11nvkm-y += nvkm/engine/dma/usergf110.o 11nvkm-y += nvkm/engine/dma/usergf119.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
index 1a377201949c..9769fc0d5351 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
@@ -52,14 +52,13 @@ nvkm_dma_oclass_new(struct nvkm_device *device,
52 struct nvkm_object **pobject) 52 struct nvkm_object **pobject)
53{ 53{
54 struct nvkm_dma *dma = nvkm_dma(oclass->engine); 54 struct nvkm_dma *dma = nvkm_dma(oclass->engine);
55 struct nvkm_dma_impl *impl = (void *)dma->engine.subdev.object.oclass;
56 struct nvkm_dmaobj *dmaobj = NULL; 55 struct nvkm_dmaobj *dmaobj = NULL;
57 struct nvkm_client *client = oclass->client; 56 struct nvkm_client *client = oclass->client;
58 struct rb_node **ptr = &client->dmaroot.rb_node; 57 struct rb_node **ptr = &client->dmaroot.rb_node;
59 struct rb_node *parent = NULL; 58 struct rb_node *parent = NULL;
60 int ret; 59 int ret;
61 60
62 ret = impl->class_new(dma, oclass, data, size, &dmaobj); 61 ret = dma->func->class_new(dma, oclass, data, size, &dmaobj);
63 if (dmaobj) 62 if (dmaobj)
64 *pobject = &dmaobj->object; 63 *pobject = &dmaobj->object;
65 if (ret) 64 if (ret)
@@ -130,26 +129,29 @@ nvkm_dma_oclass_fifo_get(struct nvkm_oclass *oclass, int index)
130 return count; 129 return count;
131} 130}
132 131
132static void *
133nvkm_dma_dtor(struct nvkm_engine *engine)
134{
135 return nvkm_dma(engine);
136}
137
133static const struct nvkm_engine_func 138static const struct nvkm_engine_func
134nvkm_dma = { 139nvkm_dma = {
140 .dtor = nvkm_dma_dtor,
135 .base.sclass = nvkm_dma_oclass_base_get, 141 .base.sclass = nvkm_dma_oclass_base_get,
136 .fifo.sclass = nvkm_dma_oclass_fifo_get, 142 .fifo.sclass = nvkm_dma_oclass_fifo_get,
137}; 143};
138 144
139int 145int
140_nvkm_dma_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 146nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device,
141 struct nvkm_oclass *oclass, void *data, u32 size, 147 int index, struct nvkm_dma **pdma)
142 struct nvkm_object **pobject)
143{ 148{
144 struct nvkm_dma *dmaeng; 149 struct nvkm_dma *dma;
145 int ret;
146 150
147 ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", 151 if (!(dma = *pdma = kzalloc(sizeof(*dma), GFP_KERNEL)))
148 "dmaobj", &dmaeng); 152 return -ENOMEM;
149 *pobject = nv_object(dmaeng); 153 dma->func = func;
150 if (ret)
151 return ret;
152 154
153 dmaeng->engine.func = &nvkm_dma; 155 return nvkm_engine_ctor(&nvkm_dma, device, index,
154 return 0; 156 0, true, &dma->engine);
155} 157}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
index 81badf09eed8..efec5d322179 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.c
@@ -24,14 +24,13 @@
24#include "priv.h" 24#include "priv.h"
25#include "user.h" 25#include "user.h"
26 26
27struct nvkm_oclass * 27static const struct nvkm_dma_func
28gf100_dmaeng_oclass = &(struct nvkm_dma_impl) { 28gf100_dma = {
29 .base.handle = NV_ENGINE(DMAOBJ, 0xc0),
30 .base.ofuncs = &(struct nvkm_ofuncs) {
31 .ctor = _nvkm_dma_ctor,
32 .dtor = _nvkm_dma_dtor,
33 .init = _nvkm_dma_init,
34 .fini = _nvkm_dma_fini,
35 },
36 .class_new = gf100_dmaobj_new, 29 .class_new = gf100_dmaobj_new,
37}.base; 30};
31
32int
33gf100_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
34{
35 return nvkm_dma_new_(&gf100_dma, device, index, pdma);
36}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c
index 79d869bf9a61..34c766039aed 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.c
@@ -24,14 +24,13 @@
24#include "priv.h" 24#include "priv.h"
25#include "user.h" 25#include "user.h"
26 26
27struct nvkm_oclass * 27static const struct nvkm_dma_func
28gf110_dmaeng_oclass = &(struct nvkm_dma_impl) { 28gf119_dma = {
29 .base.handle = NV_ENGINE(DMAOBJ, 0xd0), 29 .class_new = gf119_dmaobj_new,
30 .base.ofuncs = &(struct nvkm_ofuncs) { 30};
31 .ctor = _nvkm_dma_ctor, 31
32 .dtor = _nvkm_dma_dtor, 32int
33 .init = _nvkm_dma_init, 33gf119_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
34 .fini = _nvkm_dma_fini, 34{
35 }, 35 return nvkm_dma_new_(&gf119_dma, device, index, pdma);
36 .class_new = gf110_dmaobj_new, 36}
37}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
index c116995f8494..30747a0ce488 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.c
@@ -24,14 +24,13 @@
24#include "priv.h" 24#include "priv.h"
25#include "user.h" 25#include "user.h"
26 26
27struct nvkm_oclass * 27static const struct nvkm_dma_func
28nv04_dmaeng_oclass = &(struct nvkm_dma_impl) { 28nv04_dma = {
29 .base.handle = NV_ENGINE(DMAOBJ, 0x04),
30 .base.ofuncs = &(struct nvkm_ofuncs) {
31 .ctor = _nvkm_dma_ctor,
32 .dtor = _nvkm_dma_dtor,
33 .init = _nvkm_dma_init,
34 .fini = _nvkm_dma_fini,
35 },
36 .class_new = nv04_dmaobj_new, 29 .class_new = nv04_dmaobj_new,
37}.base; 30};
31
32int
33nv04_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
34{
35 return nvkm_dma_new_(&nv04_dma, device, index, pdma);
36}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
index b8d87e7d6ed7..77aca7b71c83 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.c
@@ -24,14 +24,13 @@
24#include "priv.h" 24#include "priv.h"
25#include "user.h" 25#include "user.h"
26 26
27struct nvkm_oclass * 27static const struct nvkm_dma_func
28nv50_dmaeng_oclass = &(struct nvkm_dma_impl) { 28nv50_dma = {
29 .base.handle = NV_ENGINE(DMAOBJ, 0x50),
30 .base.ofuncs = &(struct nvkm_ofuncs) {
31 .ctor = _nvkm_dma_ctor,
32 .dtor = _nvkm_dma_dtor,
33 .init = _nvkm_dma_init,
34 .fini = _nvkm_dma_fini,
35 },
36 .class_new = nv50_dmaobj_new, 29 .class_new = nv50_dmaobj_new,
37}.base; 30};
31
32int
33nv50_dma_new(struct nvkm_device *device, int index, struct nvkm_dma **pdma)
34{
35 return nvkm_dma_new_(&nv50_dma, device, index, pdma);
36}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h
index fbff168e6cc8..deb37ee55c0b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h
@@ -3,18 +3,15 @@
3#define nvkm_dma(p) container_of((p), struct nvkm_dma, engine) 3#define nvkm_dma(p) container_of((p), struct nvkm_dma, engine)
4#include <engine/dma.h> 4#include <engine/dma.h>
5 5
6int _nvkm_dma_ctor(struct nvkm_object *, struct nvkm_object *, 6struct nvkm_dmaobj_func {
7 struct nvkm_oclass *, void *, u32, 7 int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *, int align,
8 struct nvkm_object **);
9#define _nvkm_dma_dtor _nvkm_engine_dtor
10#define _nvkm_dma_init _nvkm_engine_init
11#define _nvkm_dma_fini _nvkm_engine_fini
12
13struct nvkm_dma_impl {
14 struct nvkm_oclass base;
15 struct nvkm_oclass *sclass;
16 int (*bind)(struct nvkm_dmaobj *, struct nvkm_gpuobj *,
17 struct nvkm_gpuobj **); 8 struct nvkm_gpuobj **);
9};
10
11int nvkm_dma_new_(const struct nvkm_dma_func *, struct nvkm_device *,
12 int index, struct nvkm_dma **);
13
14struct nvkm_dma_func {
18 int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *, 15 int (*class_new)(struct nvkm_dma *, const struct nvkm_oclass *,
19 void *data, u32 size, struct nvkm_dmaobj **); 16 void *data, u32 size, struct nvkm_dmaobj **);
20}; 17};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h
index f667505a892b..69a7f1034024 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h
@@ -13,6 +13,6 @@ int nv50_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
13 struct nvkm_dmaobj **); 13 struct nvkm_dmaobj **);
14int gf100_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, 14int gf100_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
15 struct nvkm_dmaobj **); 15 struct nvkm_dmaobj **);
16int gf110_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32, 16int gf119_dmaobj_new(struct nvkm_dma *, const struct nvkm_oclass *, void *, u32,
17 struct nvkm_dmaobj **); 17 struct nvkm_dmaobj **);
18#endif 18#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c
index f6bbdffed4e7..0e1af8b4db84 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c
@@ -21,7 +21,7 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#define gf110_dmaobj(p) container_of((p), struct gf110_dmaobj, base) 24#define gf119_dmaobj(p) container_of((p), struct gf119_dmaobj, base)
25#include "user.h" 25#include "user.h"
26 26
27#include <core/client.h> 27#include <core/client.h>
@@ -31,16 +31,16 @@
31#include <nvif/class.h> 31#include <nvif/class.h>
32#include <nvif/unpack.h> 32#include <nvif/unpack.h>
33 33
34struct gf110_dmaobj { 34struct gf119_dmaobj {
35 struct nvkm_dmaobj base; 35 struct nvkm_dmaobj base;
36 u32 flags0; 36 u32 flags0;
37}; 37};
38 38
39static int 39static int
40gf110_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, 40gf119_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
41 int align, struct nvkm_gpuobj **pgpuobj) 41 int align, struct nvkm_gpuobj **pgpuobj)
42{ 42{
43 struct gf110_dmaobj *dmaobj = gf110_dmaobj(base); 43 struct gf119_dmaobj *dmaobj = gf119_dmaobj(base);
44 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; 44 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
45 int ret; 45 int ret;
46 46
@@ -60,19 +60,19 @@ gf110_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
60} 60}
61 61
62static const struct nvkm_dmaobj_func 62static const struct nvkm_dmaobj_func
63gf110_dmaobj_func = { 63gf119_dmaobj_func = {
64 .bind = gf110_dmaobj_bind, 64 .bind = gf119_dmaobj_bind,
65}; 65};
66 66
67int 67int
68gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, 68gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
69 void *data, u32 size, struct nvkm_dmaobj **pdmaobj) 69 void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
70{ 70{
71 union { 71 union {
72 struct gf110_dma_v0 v0; 72 struct gf119_dma_v0 v0;
73 } *args; 73 } *args;
74 struct nvkm_object *parent = oclass->parent; 74 struct nvkm_object *parent = oclass->parent;
75 struct gf110_dmaobj *dmaobj; 75 struct gf119_dmaobj *dmaobj;
76 u32 kind, page; 76 u32 kind, page;
77 int ret; 77 int ret;
78 78
@@ -80,14 +80,14 @@ gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
80 return -ENOMEM; 80 return -ENOMEM;
81 *pdmaobj = &dmaobj->base; 81 *pdmaobj = &dmaobj->base;
82 82
83 ret = nvkm_dmaobj_ctor(&gf110_dmaobj_func, dma, oclass, 83 ret = nvkm_dmaobj_ctor(&gf119_dmaobj_func, dma, oclass,
84 &data, &size, &dmaobj->base); 84 &data, &size, &dmaobj->base);
85 if (ret) 85 if (ret)
86 return ret; 86 return ret;
87 87
88 args = data; 88 args = data;
89 89
90 nvif_ioctl(parent, "create gf110 dma size %d\n", size); 90 nvif_ioctl(parent, "create gf119 dma size %d\n", size);
91 if (nvif_unpack(args->v0, 0, 0, false)) { 91 if (nvif_unpack(args->v0, 0, 0, false)) {
92 nvif_ioctl(parent, 92 nvif_ioctl(parent,
93 "create gf100 dma vers %d page %d kind %02x\n", 93 "create gf100 dma vers %d page %d kind %02x\n",
@@ -97,11 +97,11 @@ gf110_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
97 } else 97 } else
98 if (size == 0) { 98 if (size == 0) {
99 if (dmaobj->base.target != NV_MEM_TARGET_VM) { 99 if (dmaobj->base.target != NV_MEM_TARGET_VM) {
100 kind = GF110_DMA_V0_KIND_PITCH; 100 kind = GF119_DMA_V0_KIND_PITCH;
101 page = GF110_DMA_V0_PAGE_SP; 101 page = GF119_DMA_V0_PAGE_SP;
102 } else { 102 } else {
103 kind = GF110_DMA_V0_KIND_VM; 103 kind = GF119_DMA_V0_KIND_VM;
104 page = GF110_DMA_V0_PAGE_LP; 104 page = GF119_DMA_V0_PAGE_LP;
105 } 105 }
106 } else 106 } else
107 return ret; 107 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 07:42:45 -0400