Merge remote-tracking branch 'pfdo/drm-next' into drm-next

Pull in drm-next for the object find API changes.

Fix the one place the API crashes.

Signed-off-by: Dave Airlie <airlied@redhat.com>

216 files changed, 8658 insertions, 3359 deletions

diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
index 06668bca7ffc..0047b1394c70 100644
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
@@ -68,6 +68,8 @@ Optional properties:
 - adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
   generator. The chip will rely on the sync signals in the DSI data lanes,
   rather than generate its own timings for HDMI output.
+- clocks: from common clock binding: reference to the CEC clock.
+- clock-names: from common clock binding: must be "cec".
 
 Required nodes:
 
@@ -89,6 +91,8 @@ Example
                 reg = <39>;
                 interrupt-parent = <&gpio3>;
                 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+                clocks = <&cec_clock>;
+                clock-names = "cec";
 
                 adi,input-depth = <8>;
                 adi,input-colorspace = "rgb";
diff --git a/Documentation/devicetree/bindings/display/bridge/sii9234.txt b/Documentation/devicetree/bindings/display/bridge/sii9234.txt
new file mode 100644
index 000000000000..88041ba23d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/sii9234.txt
@@ -0,0 +1,49 @@
+Silicon Image SiI9234 HDMI/MHL bridge bindings
+
+Required properties:
+        - compatible : "sil,sii9234".
+        - reg : I2C address for TPI interface, use 0x39
+        - avcc33-supply : MHL/USB Switch Supply Voltage (3.3V)
+        - iovcc18-supply : I/O Supply Voltage (1.8V)
+        - avcc12-supply : TMDS Analog Supply Voltage (1.2V)
+        - cvcc12-supply : Digital Core Supply Voltage (1.2V)
+        - interrupts, interrupt-parent: interrupt specifier of INT pin
+        - reset-gpios: gpio specifier of RESET pin (active low)
+        - video interfaces: Device node can contain two video interface port
+                            nodes for HDMI encoder and connector according to [1].
+                            - port@0 - MHL to HDMI
+                            - port@1 - MHL to connector
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+
+Example:
+        sii9234@39 {
+                compatible = "sil,sii9234";
+                reg = <0x39>;
+                avcc33-supply = <&vcc33mhl>;
+                iovcc18-supply = <&vcc18mhl>;
+                avcc12-supply = <&vsil12>;
+                cvcc12-supply = <&vsil12>;
+                reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
+                interrupt-parent = <&gpf3>;
+                interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                mhl_to_hdmi: endpoint {
+                                        remote-endpoint = <&hdmi_to_mhl>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                mhl_to_connector: endpoint {
+                                        remote-endpoint = <&connector_to_mhl>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt b/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt
new file mode 100644
index 000000000000..e9e19c059260
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt
@@ -0,0 +1,49 @@
+This binding covers the official 7" (800x480) Raspberry Pi touchscreen
+panel.
+
+This DSI panel contains:
+
+- TC358762 DSI->DPI bridge
+- Atmel microcontroller on I2C for power sequencing the DSI bridge and
+  controlling backlight
+- Touchscreen controller on I2C for touch input
+
+and this binding covers the DSI display parts but not its touch input.
+
+Required properties:
+- compatible:   Must be "raspberrypi,7inch-touchscreen-panel"
+- reg:          Must be "45"
+- port:         See panel-common.txt
+
+Example:
+
+dsi1: dsi@7e700000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        <...>
+
+        port {
+                dsi_out_port: endpoint {
+                        remote-endpoint = <&panel_dsi_port>;
+                };
+        };
+};
+
+i2c_dsi: i2c {
+        compatible = "i2c-gpio";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        gpios = <&gpio 28 0
+                 &gpio 29 0>;
+
+        lcd@45 {
+                compatible = "raspberrypi,7inch-touchscreen-panel";
+                reg = <0x45>;
+
+                port {
+                        panel_dsi_port: endpoint {
+                                remote-endpoint = <&dsi_out_port>;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 92441086caba..46df3b78ae9e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -41,14 +41,17 @@ CEC. It is one end of the pipeline.
 Required properties:
   - compatible: value must be one of:
     * allwinner,sun5i-a10s-hdmi
+    * allwinner,sun6i-a31-hdmi
   - reg: base address and size of memory-mapped region
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the HDMI encoder
     * ahb: the HDMI interface clock
     * mod: the HDMI module clock
+    * ddc: the HDMI ddc clock (A31 only)
     * pll-0: the first video PLL
     * pll-1: the second video PLL
   - clock-names: the clock names mentioned above
+  - resets: phandle to the reset control for the HDMI encoder (A31 only)
   - dmas: phandles to the DMA channels used by the HDMI encoder
     * ddc-tx: The channel for DDC transmission
     * ddc-rx: The channel for DDC reception
diff --git a/drivers/dma-buf/reservation.c b/drivers/dma-buf/reservation.c
index dec3a815455d..b44d9d7db347 100644
--- a/drivers/dma-buf/reservation.c
+++ b/drivers/dma-buf/reservation.c
@@ -266,8 +266,7 @@ EXPORT_SYMBOL(reservation_object_add_excl_fence);
 * @dst: the destination reservation object
 * @src: the source reservation object
 *
-* Copy all fences from src to dst. Both src->lock as well as dst-lock must be
-* held.
+* Copy all fences from src to dst. dst-lock must be held.
 */
 int reservation_object_copy_fences(struct reservation_object *dst,
                                    struct reservation_object *src)
@@ -277,33 +276,62 @@ int reservation_object_copy_fences(struct reservation_object *dst,
         size_t size;
         unsigned i;
 
-        src_list = reservation_object_get_list(src);
+        rcu_read_lock();
+        src_list = rcu_dereference(src->fence);
 
+retry:
         if (src_list) {
-                size = offsetof(typeof(*src_list),
-                                shared[src_list->shared_count]);
+                unsigned shared_count = src_list->shared_count;
+
+                size = offsetof(typeof(*src_list), shared[shared_count]);
+                rcu_read_unlock();
+
                 dst_list = kmalloc(size, GFP_KERNEL);
                 if (!dst_list)
                         return -ENOMEM;
 
-                dst_list->shared_count = src_list->shared_count;
-                dst_list->shared_max = src_list->shared_count;
-                for (i = 0; i < src_list->shared_count; ++i)
-                        dst_list->shared[i] =
-                                dma_fence_get(src_list->shared[i]);
+                rcu_read_lock();
+                src_list = rcu_dereference(src->fence);
+                if (!src_list || src_list->shared_count > shared_count) {
+                        kfree(dst_list);
+                        goto retry;
+                }
+
+                dst_list->shared_count = 0;
+                dst_list->shared_max = shared_count;
+                for (i = 0; i < src_list->shared_count; ++i) {
+                        struct dma_fence *fence;
+
+                        fence = rcu_dereference(src_list->shared[i]);
+                        if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+                                     &fence->flags))
+                                continue;
+
+                        if (!dma_fence_get_rcu(fence)) {
+                                kfree(dst_list);
+                                src_list = rcu_dereference(src->fence);
+                                goto retry;
+                        }
+
+                        if (dma_fence_is_signaled(fence)) {
+                                dma_fence_put(fence);
+                                continue;
+                        }
+
+                        dst_list->shared[dst_list->shared_count++] = fence;
+                }
         } else {
                 dst_list = NULL;
         }
 
+        new = dma_fence_get_rcu_safe(&src->fence_excl);
+        rcu_read_unlock();
+
         kfree(dst->staged);
         dst->staged = NULL;
 
         src_list = reservation_object_get_list(dst);
-
         old = reservation_object_get_excl(dst);
-        new = reservation_object_get_excl(src);
-
-        dma_fence_get(new);
 
         preempt_disable();
         write_seqcount_begin(&dst->seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index f51b41f094ef..df9cbc78e168 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -231,7 +231,7 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev,
+                encoder = drm_encoder_find(connector->dev, NULL,
                                         connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
@@ -256,7 +256,7 @@ amdgpu_connector_find_encoder(struct drm_connector *connector,
         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
                 if (connector->encoder_ids[i] == 0)
                         break;
-                encoder = drm_encoder_find(connector->dev,
+                encoder = drm_encoder_find(connector->dev, NULL,
                                         connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
@@ -372,7 +372,7 @@ amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
@@ -1077,7 +1077,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
                         if (connector->encoder_ids[i] == 0)
                                 break;
 
-                        encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                        encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                         if (!encoder)
                                 continue;
 
@@ -1134,7 +1134,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector)
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
@@ -1153,7 +1153,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector)
         /* then check use digitial */
         /* pick the first one */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
@@ -1294,7 +1294,7 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev,
+                encoder = drm_encoder_find(connector->dev, NULL,
                                         connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
@@ -1323,7 +1323,7 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
                 if (connector->encoder_ids[i] == 0)
                         break;
-                encoder = drm_encoder_find(connector->dev,
+                encoder = drm_encoder_find(connector->dev, NULL,
                                         connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index b9ee9073cb0d..a8829af120c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -288,7 +288,7 @@ dce_virtual_encoder(struct drm_connector *connector)
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
@@ -298,7 +298,7 @@ dce_virtual_encoder(struct drm_connector *connector)
 
         /* pick the first one */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e98bb639268d..8cc228ebdc9a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2638,7 +2638,7 @@ static struct drm_encoder *best_encoder(struct drm_connector *connector)
 
         /* pick the encoder ids */
         if (enc_id) {
-                obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
+                obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
                 if (!obj) {
                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
                         return NULL;
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 6f3849ec0c1d..9555a3542022 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -713,7 +713,7 @@ static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connect
         int enc_id = connector->encoder_ids[0];
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c b/drivers/gpu/drm/bochs/bochs_kms.c
index 6a91e62da2f4..a24a18fbd65a 100644
--- a/drivers/gpu/drm/bochs/bochs_kms.c
+++ b/drivers/gpu/drm/bochs/bochs_kms.c
@@ -213,7 +213,7 @@ bochs_connector_best_encoder(struct drm_connector *connector)
         int enc_id = connector->encoder_ids[0];
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index adf9ae0e0b7c..3b99d5a06c16 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -71,7 +71,7 @@ config DRM_PARADE_PS8622
 
 config DRM_SIL_SII8620
         tristate "Silicon Image SII8620 HDMI/MHL bridge"
-        depends on OF
+        depends on OF && RC_CORE
         select DRM_KMS_HELPER
         help
           Silicon Image SII8620 HDMI/MHL bridge chip driver.
@@ -84,6 +84,14 @@ config DRM_SII902X
         ---help---
           Silicon Image sii902x bridge chip driver.
 
+config DRM_SII9234
+        tristate "Silicon Image SII9234 HDMI/MHL bridge"
+        depends on OF
+        ---help---
+          Say Y here if you want support for the MHL interface.
+          It is an I2C driver, that detects connection of MHL bridge
+          and starts encapsulation of HDMI signal.
+
 config DRM_TOSHIBA_TC358767
         tristate "Toshiba TC358767 eDP bridge"
         depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index defcf1e7ca1c..e3d5eb031f18 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
 obj-$(CONFIG_DRM_SII902X) += sii902x.o
+obj-$(CONFIG_DRM_SII9234) += sii9234.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
 obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
diff --git a/drivers/gpu/drm/bridge/adv7511/Kconfig b/drivers/gpu/drm/bridge/adv7511/Kconfig
index 2fed567f9943..592b9d2ec034 100644
--- a/drivers/gpu/drm/bridge/adv7511/Kconfig
+++ b/drivers/gpu/drm/bridge/adv7511/Kconfig
@@ -21,3 +21,11 @@ config DRM_I2C_ADV7533
         default y
         help
           Support for the Analog Devices ADV7533 DSI to HDMI encoder.
+
+config DRM_I2C_ADV7511_CEC
+        bool "ADV7511/33 HDMI CEC driver"
+        depends on DRM_I2C_ADV7511
+        select CEC_CORE
+        default y
+        help
+          When selected the HDMI transmitter will support the CEC feature.
diff --git a/drivers/gpu/drm/bridge/adv7511/Makefile b/drivers/gpu/drm/bridge/adv7511/Makefile
index 5ba675534f6e..5bb384938a71 100644
--- a/drivers/gpu/drm/bridge/adv7511/Makefile
+++ b/drivers/gpu/drm/bridge/adv7511/Makefile
@@ -1,4 +1,5 @@
 adv7511-y := adv7511_drv.o
 adv7511-$(CONFIG_DRM_I2C_ADV7511_AUDIO) += adv7511_audio.o
+adv7511-$(CONFIG_DRM_I2C_ADV7511_CEC) += adv7511_cec.o
 adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
 obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 12ef2d8ee110..b4efcbabf7f7 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -195,6 +195,25 @@
 #define ADV7511_PACKET_GM(x)        ADV7511_PACKET(5, x)
 #define ADV7511_PACKET_SPARE(x)     ADV7511_PACKET(6, x)
 
+#define ADV7511_REG_CEC_TX_FRAME_HDR    0x00
+#define ADV7511_REG_CEC_TX_FRAME_DATA0  0x01
+#define ADV7511_REG_CEC_TX_FRAME_LEN    0x10
+#define ADV7511_REG_CEC_TX_ENABLE       0x11
+#define ADV7511_REG_CEC_TX_RETRY        0x12
+#define ADV7511_REG_CEC_TX_LOW_DRV_CNT  0x14
+#define ADV7511_REG_CEC_RX_FRAME_HDR    0x15
+#define ADV7511_REG_CEC_RX_FRAME_DATA0  0x16
+#define ADV7511_REG_CEC_RX_FRAME_LEN    0x25
+#define ADV7511_REG_CEC_RX_ENABLE       0x26
+#define ADV7511_REG_CEC_RX_BUFFERS      0x4a
+#define ADV7511_REG_CEC_LOG_ADDR_MASK   0x4b
+#define ADV7511_REG_CEC_LOG_ADDR_0_1    0x4c
+#define ADV7511_REG_CEC_LOG_ADDR_2      0x4d
+#define ADV7511_REG_CEC_CLK_DIV         0x4e
+#define ADV7511_REG_CEC_SOFT_RESET      0x50
+
+#define ADV7533_REG_CEC_OFFSET          0x70
+
 enum adv7511_input_clock {
         ADV7511_INPUT_CLOCK_1X,
         ADV7511_INPUT_CLOCK_2X,
@@ -297,6 +316,8 @@ enum adv7511_type {
         ADV7533,
 };
 
+#define ADV7511_MAX_ADDRS 3
+
 struct adv7511 {
         struct i2c_client *i2c_main;
         struct i2c_client *i2c_edid;
@@ -341,15 +362,27 @@ struct adv7511 {
 
         enum adv7511_type type;
         struct platform_device *audio_pdev;
+
+        struct cec_adapter *cec_adap;
+        u8   cec_addr[ADV7511_MAX_ADDRS];
+        u8   cec_valid_addrs;
+        bool cec_enabled_adap;
+        struct clk *cec_clk;
+        u32 cec_clk_freq;
 };
 
+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
+                     unsigned int offset);
+void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
+#endif
+
 #ifdef CONFIG_DRM_I2C_ADV7533
 void adv7533_dsi_power_on(struct adv7511 *adv);
 void adv7533_dsi_power_off(struct adv7511 *adv);
 void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
 int adv7533_patch_registers(struct adv7511 *adv);
-void adv7533_uninit_cec(struct adv7511 *adv);
-int adv7533_init_cec(struct adv7511 *adv);
+int adv7533_patch_cec_registers(struct adv7511 *adv);
 int adv7533_attach_dsi(struct adv7511 *adv);
 void adv7533_detach_dsi(struct adv7511 *adv);
 int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
@@ -372,11 +405,7 @@ static inline int adv7533_patch_registers(struct adv7511 *adv)
         return -ENODEV;
 }
 
-static inline void adv7533_uninit_cec(struct adv7511 *adv)
-{
-}
-
-static inline int adv7533_init_cec(struct adv7511 *adv)
+static inline int adv7533_patch_cec_registers(struct adv7511 *adv)
 {
         return -ENODEV;
 }
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
new file mode 100644
index 000000000000..b33d730e4d73
--- /dev/null
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
@@ -0,0 +1,337 @@
+/*
+ * adv7511_cec.c - Analog Devices ADV7511/33 cec driver
+ *
+ * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include <media/cec.h>
+
+#include "adv7511.h"
+
+#define ADV7511_INT1_CEC_MASK \
+        (ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \
+         ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1)
+
+static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_status)
+{
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                        ADV7533_REG_CEC_OFFSET : 0;
+        unsigned int val;
+
+        if (regmap_read(adv7511->regmap_cec,
+                        ADV7511_REG_CEC_TX_ENABLE + offset, &val))
+                return;
+
+        if ((val & 0x01) == 0)
+                return;
+
+        if (tx_raw_status & ADV7511_INT1_CEC_TX_ARBIT_LOST) {
+                cec_transmit_attempt_done(adv7511->cec_adap,
+                                          CEC_TX_STATUS_ARB_LOST);
+                return;
+        }
+        if (tx_raw_status & ADV7511_INT1_CEC_TX_RETRY_TIMEOUT) {
+                u8 status;
+                u8 err_cnt = 0;
+                u8 nack_cnt = 0;
+                u8 low_drive_cnt = 0;
+                unsigned int cnt;
+
+                /*
+                 * We set this status bit since this hardware performs
+                 * retransmissions.
+                 */
+                status = CEC_TX_STATUS_MAX_RETRIES;
+                if (regmap_read(adv7511->regmap_cec,
+                            ADV7511_REG_CEC_TX_LOW_DRV_CNT + offset, &cnt)) {
+                        err_cnt = 1;
+                        status |= CEC_TX_STATUS_ERROR;
+                } else {
+                        nack_cnt = cnt & 0xf;
+                        if (nack_cnt)
+                                status |= CEC_TX_STATUS_NACK;
+                        low_drive_cnt = cnt >> 4;
+                        if (low_drive_cnt)
+                                status |= CEC_TX_STATUS_LOW_DRIVE;
+                }
+                cec_transmit_done(adv7511->cec_adap, status,
+                                  0, nack_cnt, low_drive_cnt, err_cnt);
+                return;
+        }
+        if (tx_raw_status & ADV7511_INT1_CEC_TX_READY) {
+                cec_transmit_attempt_done(adv7511->cec_adap, CEC_TX_STATUS_OK);
+                return;
+        }
+}
+
+void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1)
+{
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                        ADV7533_REG_CEC_OFFSET : 0;
+        const u32 irq_tx_mask = ADV7511_INT1_CEC_TX_READY |
+                                ADV7511_INT1_CEC_TX_ARBIT_LOST |
+                                ADV7511_INT1_CEC_TX_RETRY_TIMEOUT;
+        struct cec_msg msg = {};
+        unsigned int len;
+        unsigned int val;
+        u8 i;
+
+        if (irq1 & irq_tx_mask)
+                adv_cec_tx_raw_status(adv7511, irq1);
+
+        if (!(irq1 & ADV7511_INT1_CEC_RX_READY1))
+                return;
+
+        if (regmap_read(adv7511->regmap_cec,
+                        ADV7511_REG_CEC_RX_FRAME_LEN + offset, &len))
+                return;
+
+        msg.len = len & 0x1f;
+
+        if (msg.len > 16)
+                msg.len = 16;
+
+        if (!msg.len)
+                return;
+
+        for (i = 0; i < msg.len; i++) {
+                regmap_read(adv7511->regmap_cec,
+                            i + ADV7511_REG_CEC_RX_FRAME_HDR + offset, &val);
+                msg.msg[i] = val;
+        }
+
+        /* toggle to re-enable rx 1 */
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_RX_BUFFERS + offset, 1);
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
+        cec_received_msg(adv7511->cec_adap, &msg);
+}
+
+static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
+{
+        struct adv7511 *adv7511 = cec_get_drvdata(adap);
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                        ADV7533_REG_CEC_OFFSET : 0;
+
+        if (adv7511->i2c_cec == NULL)
+                return -EIO;
+
+        if (!adv7511->cec_enabled_adap && enable) {
+                /* power up cec section */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_CLK_DIV + offset,
+                                   0x03, 0x01);
+                /* legacy mode and clear all rx buffers */
+                regmap_write(adv7511->regmap_cec,
+                             ADV7511_REG_CEC_RX_BUFFERS + offset, 0x07);
+                regmap_write(adv7511->regmap_cec,
+                             ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
+                /* initially disable tx */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_TX_ENABLE + offset, 1, 0);
+                /* enabled irqs: */
+                /* tx: ready */
+                /* tx: arbitration lost */
+                /* tx: retry timeout */
+                /* rx: ready 1 */
+                regmap_update_bits(adv7511->regmap,
+                                   ADV7511_REG_INT_ENABLE(1), 0x3f,
+                                   ADV7511_INT1_CEC_MASK);
+        } else if (adv7511->cec_enabled_adap && !enable) {
+                regmap_update_bits(adv7511->regmap,
+                                   ADV7511_REG_INT_ENABLE(1), 0x3f, 0);
+                /* disable address mask 1-3 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
+                                   0x70, 0x00);
+                /* power down cec section */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_CLK_DIV + offset,
+                                   0x03, 0x00);
+                adv7511->cec_valid_addrs = 0;
+        }
+        adv7511->cec_enabled_adap = enable;
+        return 0;
+}
+
+static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
+{
+        struct adv7511 *adv7511 = cec_get_drvdata(adap);
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                        ADV7533_REG_CEC_OFFSET : 0;
+        unsigned int i, free_idx = ADV7511_MAX_ADDRS;
+
+        if (!adv7511->cec_enabled_adap)
+                return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
+
+        if (addr == CEC_LOG_ADDR_INVALID) {
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
+                                   0x70, 0);
+                adv7511->cec_valid_addrs = 0;
+                return 0;
+        }
+
+        for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
+                bool is_valid = adv7511->cec_valid_addrs & (1 << i);
+
+                if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
+                        free_idx = i;
+                if (is_valid && adv7511->cec_addr[i] == addr)
+                        return 0;
+        }
+        if (i == ADV7511_MAX_ADDRS) {
+                i = free_idx;
+                if (i == ADV7511_MAX_ADDRS)
+                        return -ENXIO;
+        }
+        adv7511->cec_addr[i] = addr;
+        adv7511->cec_valid_addrs |= 1 << i;
+
+        switch (i) {
+        case 0:
+                /* enable address mask 0 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
+                                   0x10, 0x10);
+                /* set address for mask 0 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
+                                   0x0f, addr);
+                break;
+        case 1:
+                /* enable address mask 1 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
+                                   0x20, 0x20);
+                /* set address for mask 1 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
+                                   0xf0, addr << 4);
+                break;
+        case 2:
+                /* enable address mask 2 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
+                                   0x40, 0x40);
+                /* set address for mask 1 */
+                regmap_update_bits(adv7511->regmap_cec,
+                                   ADV7511_REG_CEC_LOG_ADDR_2 + offset,
+                                   0x0f, addr);
+                break;
+        }
+        return 0;
+}
+
+static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+                                     u32 signal_free_time, struct cec_msg *msg)
+{
+        struct adv7511 *adv7511 = cec_get_drvdata(adap);
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                        ADV7533_REG_CEC_OFFSET : 0;
+        u8 len = msg->len;
+        unsigned int i;
+
+        /*
+         * The number of retries is the number of attempts - 1, but retry
+         * at least once. It's not clear if a value of 0 is allowed, so
+         * let's do at least one retry.
+         */
+        regmap_update_bits(adv7511->regmap_cec,
+                           ADV7511_REG_CEC_TX_RETRY + offset,
+                           0x70, max(1, attempts - 1) << 4);
+
+        /* blocking, clear cec tx irq status */
+        regmap_update_bits(adv7511->regmap, ADV7511_REG_INT(1), 0x38, 0x38);
+
+        /* write data */
+        for (i = 0; i < len; i++)
+                regmap_write(adv7511->regmap_cec,
+                             i + ADV7511_REG_CEC_TX_FRAME_HDR + offset,
+                             msg->msg[i]);
+
+        /* set length (data + header) */
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_TX_FRAME_LEN + offset, len);
+        /* start transmit, enable tx */
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_TX_ENABLE + offset, 0x01);
+        return 0;
+}
+
+static const struct cec_adap_ops adv7511_cec_adap_ops = {
+        .adap_enable = adv7511_cec_adap_enable,
+        .adap_log_addr = adv7511_cec_adap_log_addr,
+        .adap_transmit = adv7511_cec_adap_transmit,
+};
+
+static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
+{
+        adv7511->cec_clk = devm_clk_get(dev, "cec");
+        if (IS_ERR(adv7511->cec_clk)) {
+                int ret = PTR_ERR(adv7511->cec_clk);
+
+                adv7511->cec_clk = NULL;
+                return ret;
+        }
+        clk_prepare_enable(adv7511->cec_clk);
+        adv7511->cec_clk_freq = clk_get_rate(adv7511->cec_clk);
+        return 0;
+}
+
+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
+                     unsigned int offset)
+{
+        int ret = adv7511_cec_parse_dt(dev, adv7511);
+
+        if (ret)
+                return ret;
+
+        adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
+                adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
+        if (IS_ERR(adv7511->cec_adap))
+                return PTR_ERR(adv7511->cec_adap);
+
+        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
+        /* cec soft reset */
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_SOFT_RESET + offset, 0x01);
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_SOFT_RESET + offset, 0x00);
+
+        /* legacy mode */
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_RX_BUFFERS + offset, 0x00);
+
+        regmap_write(adv7511->regmap_cec,
+                     ADV7511_REG_CEC_CLK_DIV + offset,
+                     ((adv7511->cec_clk_freq / 750000) - 1) << 2);
+
+        ret = cec_register_adapter(adv7511->cec_adap, dev);
+        if (ret) {
+                cec_delete_adapter(adv7511->cec_adap);
+                adv7511->cec_adap = NULL;
+        }
+        return ret;
+}
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index bd7dbae1119e..31ca883bda83 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -11,12 +11,15 @@
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_edid.h>
 
+#include <media/cec.h>
+
 #include "adv7511.h"
 
 /* ADI recommended values for proper operation. */
@@ -336,8 +339,10 @@ static void __adv7511_power_on(struct adv7511 *adv7511)
                  */
                 regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
                              ADV7511_INT0_EDID_READY | ADV7511_INT0_HPD);
-                regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
-                             ADV7511_INT1_DDC_ERROR);
+                regmap_update_bits(adv7511->regmap,
+                                   ADV7511_REG_INT_ENABLE(1),
+                                   ADV7511_INT1_DDC_ERROR,
+                                   ADV7511_INT1_DDC_ERROR);
         }
 
         /*
@@ -373,6 +378,9 @@ static void __adv7511_power_off(struct adv7511 *adv7511)
         regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
                            ADV7511_POWER_POWER_DOWN,
                            ADV7511_POWER_POWER_DOWN);
+        regmap_update_bits(adv7511->regmap,
+                           ADV7511_REG_INT_ENABLE(1),
+                           ADV7511_INT1_DDC_ERROR, 0);
         regcache_mark_dirty(adv7511->regmap);
 }
 
@@ -423,6 +431,8 @@ static void adv7511_hpd_work(struct work_struct *work)
 
         if (adv7511->connector.status != status) {
                 adv7511->connector.status = status;
+                if (status == connector_status_disconnected)
+                        cec_phys_addr_invalidate(adv7511->cec_adap);
                 drm_kms_helper_hotplug_event(adv7511->connector.dev);
         }
 }
@@ -453,6 +463,10 @@ static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd)
                         wake_up_all(&adv7511->wq);
         }
 
+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
+        adv7511_cec_irq_process(adv7511, irq1);
+#endif
+
         return 0;
 }
 
@@ -595,6 +609,8 @@ static int adv7511_get_modes(struct adv7511 *adv7511,
 
         kfree(edid);
 
+        cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
+
         return count;
 }
 
@@ -919,6 +935,65 @@ static void adv7511_uninit_regulators(struct adv7511 *adv)
         regulator_bulk_disable(adv->num_supplies, adv->supplies);
 }
 
+static bool adv7511_cec_register_volatile(struct device *dev, unsigned int reg)
+{
+        struct i2c_client *i2c = to_i2c_client(dev);
+        struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
+
+        if (adv7511->type == ADV7533)
+                reg -= ADV7533_REG_CEC_OFFSET;
+
+        switch (reg) {
+        case ADV7511_REG_CEC_RX_FRAME_HDR:
+        case ADV7511_REG_CEC_RX_FRAME_DATA0...
+                ADV7511_REG_CEC_RX_FRAME_DATA0 + 14:
+        case ADV7511_REG_CEC_RX_FRAME_LEN:
+        case ADV7511_REG_CEC_RX_BUFFERS:
+        case ADV7511_REG_CEC_TX_LOW_DRV_CNT:
+                return true;
+        }
+
+        return false;
+}
+
+static const struct regmap_config adv7511_cec_regmap_config = {
+        .reg_bits = 8,
+        .val_bits = 8,
+
+        .max_register = 0xff,
+        .cache_type = REGCACHE_RBTREE,
+        .volatile_reg = adv7511_cec_register_volatile,
+};
+
+static int adv7511_init_cec_regmap(struct adv7511 *adv)
+{
+        int ret;
+
+        adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
+                                     adv->i2c_main->addr - 1);
+        if (!adv->i2c_cec)
+                return -ENOMEM;
+        i2c_set_clientdata(adv->i2c_cec, adv);
+
+        adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
+                                        &adv7511_cec_regmap_config);
+        if (IS_ERR(adv->regmap_cec)) {
+                ret = PTR_ERR(adv->regmap_cec);
+                goto err;
+        }
+
+        if (adv->type == ADV7533) {
+                ret = adv7533_patch_cec_registers(adv);
+                if (ret)
+                        goto err;
+        }
+
+        return 0;
+err:
+        i2c_unregister_device(adv->i2c_cec);
+        return ret;
+}
+
 static int adv7511_parse_dt(struct device_node *np,
                             struct adv7511_link_config *config)
 {
@@ -1009,6 +1084,7 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
         struct device *dev = &i2c->dev;
         unsigned int main_i2c_addr = i2c->addr << 1;
         unsigned int edid_i2c_addr = main_i2c_addr + 4;
+        unsigned int offset;
         unsigned int val;
         int ret;
 
@@ -1092,11 +1168,9 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
                 goto uninit_regulators;
         }
 
-        if (adv7511->type == ADV7533) {
-                ret = adv7533_init_cec(adv7511);
-                if (ret)
-                        goto err_i2c_unregister_edid;
-        }
+        ret = adv7511_init_cec_regmap(adv7511);
+        if (ret)
+                goto err_i2c_unregister_edid;
 
         INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
 
@@ -1111,10 +1185,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
                         goto err_unregister_cec;
         }
 
-        /* CEC is unused for now */
-        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
-                     ADV7511_CEC_CTRL_POWER_DOWN);
-
         adv7511_power_off(adv7511);
 
         i2c_set_clientdata(i2c, adv7511);
@@ -1129,10 +1199,23 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
 
         adv7511_audio_init(dev, adv7511);
 
+        offset = adv7511->type == ADV7533 ? ADV7533_REG_CEC_OFFSET : 0;
+
+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
+        ret = adv7511_cec_init(dev, adv7511, offset);
+        if (ret)
+                goto err_unregister_cec;
+#else
+        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
+                     ADV7511_CEC_CTRL_POWER_DOWN);
+#endif
+
         return 0;
 
 err_unregister_cec:
-        adv7533_uninit_cec(adv7511);
+        i2c_unregister_device(adv7511->i2c_cec);
+        if (adv7511->cec_clk)
+                clk_disable_unprepare(adv7511->cec_clk);
 err_i2c_unregister_edid:
         i2c_unregister_device(adv7511->i2c_edid);
 uninit_regulators:
@@ -1145,10 +1228,11 @@ static int adv7511_remove(struct i2c_client *i2c)
 {
         struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
 
-        if (adv7511->type == ADV7533) {
+        if (adv7511->type == ADV7533)
                 adv7533_detach_dsi(adv7511);
-                adv7533_uninit_cec(adv7511);
-        }
+        i2c_unregister_device(adv7511->i2c_cec);
+        if (adv7511->cec_clk)
+                clk_disable_unprepare(adv7511->cec_clk);
 
         adv7511_uninit_regulators(adv7511);
 
@@ -1156,6 +1240,8 @@ static int adv7511_remove(struct i2c_client *i2c)
 
         adv7511_audio_exit(adv7511);
 
+        cec_unregister_adapter(adv7511->cec_adap);
+
         i2c_unregister_device(adv7511->i2c_edid);
 
         return 0;
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c b/drivers/gpu/drm/bridge/adv7511/adv7533.c
index ac804f81e2f6..185b6d842166 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7533.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
@@ -32,14 +32,6 @@ static const struct reg_sequence adv7533_cec_fixed_registers[] = {
         { 0x05, 0xc8 },
 };
 
-static const struct regmap_config adv7533_cec_regmap_config = {
-        .reg_bits = 8,
-        .val_bits = 8,
-
-        .max_register = 0xff,
-        .cache_type = REGCACHE_RBTREE,
-};
-
 static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
 {
         struct mipi_dsi_device *dsi = adv->dsi;
@@ -145,37 +137,11 @@ int adv7533_patch_registers(struct adv7511 *adv)
                                      ARRAY_SIZE(adv7533_fixed_registers));
 }
 
-void adv7533_uninit_cec(struct adv7511 *adv)
-{
-        i2c_unregister_device(adv->i2c_cec);
-}
-
-int adv7533_init_cec(struct adv7511 *adv)
+int adv7533_patch_cec_registers(struct adv7511 *adv)
 {
-        int ret;
-
-        adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
-                                     adv->i2c_main->addr - 1);
-        if (!adv->i2c_cec)
-                return -ENOMEM;
-
-        adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
-                                        &adv7533_cec_regmap_config);
-        if (IS_ERR(adv->regmap_cec)) {
-                ret = PTR_ERR(adv->regmap_cec);
-                goto err;
-        }
-
-        ret = regmap_register_patch(adv->regmap_cec,
+        return regmap_register_patch(adv->regmap_cec,
                                     adv7533_cec_fixed_registers,
                                     ARRAY_SIZE(adv7533_cec_fixed_registers));
-        if (ret)
-                goto err;
-
-        return 0;
-err:
-        adv7533_uninit_cec(adv);
-        return ret;
 }
 
 int adv7533_attach_dsi(struct adv7511 *adv)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index e0cca19b4044..6d99d4a3beb3 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -188,7 +188,15 @@ EXPORT_SYMBOL(drm_panel_bridge_add);
  */
 void drm_panel_bridge_remove(struct drm_bridge *bridge)
 {
-        struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+        struct panel_bridge *panel_bridge;
+
+        if (!bridge)
+                return;
+
+        if (bridge->funcs != &panel_bridge_bridge_funcs)
+                return;
+
+        panel_bridge = drm_bridge_to_panel_bridge(bridge);
 
         drm_bridge_remove(bridge);
         devm_kfree(panel_bridge->panel->dev, bridge);
diff --git a/drivers/gpu/drm/bridge/sii9234.c b/drivers/gpu/drm/bridge/sii9234.c
new file mode 100644
index 000000000000..c77000626c22
--- /dev/null
+++ b/drivers/gpu/drm/bridge/sii9234.c
@@ -0,0 +1,994 @@
+/*
+ * Copyright (C) 2017 Samsung Electronics
+ *
+ * Authors:
+ *    Tomasz Stanislawski <t.stanislaws@samsung.com>
+ *    Maciej Purski <m.purski@samsung.com>
+ *
+ * Based on sii9234 driver created by:
+ *    Adam Hampson <ahampson@sta.samsung.com>
+ *    Erik Gilling <konkers@android.com>
+ *    Shankar Bandal <shankar.b@samsung.com>
+ *    Dharam Kumar <dharam.kr@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program
+ *
+ */
+#include <drm/bridge/mhl.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define CBUS_DEVCAP_OFFSET              0x80
+
+#define SII9234_MHL_VERSION             0x11
+#define SII9234_SCRATCHPAD_SIZE         0x10
+#define SII9234_INT_STAT_SIZE           0x33
+
+#define BIT_TMDS_CCTRL_TMDS_OE          BIT(4)
+#define MHL_HPD_OUT_OVR_EN              BIT(4)
+#define MHL_HPD_OUT_OVR_VAL             BIT(5)
+#define MHL_INIT_TIMEOUT                0x0C
+
+/* MHL Tx registers and bits */
+#define MHL_TX_SRST                     0x05
+#define MHL_TX_SYSSTAT_REG              0x09
+#define MHL_TX_INTR1_REG                0x71
+#define MHL_TX_INTR4_REG                0x74
+#define MHL_TX_INTR1_ENABLE_REG         0x75
+#define MHL_TX_INTR4_ENABLE_REG         0x78
+#define MHL_TX_INT_CTRL_REG             0x79
+#define MHL_TX_TMDS_CCTRL               0x80
+#define MHL_TX_DISC_CTRL1_REG           0x90
+#define MHL_TX_DISC_CTRL2_REG           0x91
+#define MHL_TX_DISC_CTRL3_REG           0x92
+#define MHL_TX_DISC_CTRL4_REG           0x93
+#define MHL_TX_DISC_CTRL5_REG           0x94
+#define MHL_TX_DISC_CTRL6_REG           0x95
+#define MHL_TX_DISC_CTRL7_REG           0x96
+#define MHL_TX_DISC_CTRL8_REG           0x97
+#define MHL_TX_STAT2_REG                0x99
+#define MHL_TX_MHLTX_CTL1_REG           0xA0
+#define MHL_TX_MHLTX_CTL2_REG           0xA1
+#define MHL_TX_MHLTX_CTL4_REG           0xA3
+#define MHL_TX_MHLTX_CTL6_REG           0xA5
+#define MHL_TX_MHLTX_CTL7_REG           0xA6
+
+#define RSEN_STATUS                     BIT(2)
+#define HPD_CHANGE_INT                  BIT(6)
+#define RSEN_CHANGE_INT                 BIT(5)
+#define RGND_READY_INT                  BIT(6)
+#define VBUS_LOW_INT                    BIT(5)
+#define CBUS_LKOUT_INT                  BIT(4)
+#define MHL_DISC_FAIL_INT               BIT(3)
+#define MHL_EST_INT                     BIT(2)
+#define HPD_CHANGE_INT_MASK             BIT(6)
+#define RSEN_CHANGE_INT_MASK            BIT(5)
+
+#define RGND_READY_MASK                 BIT(6)
+#define CBUS_LKOUT_MASK                 BIT(4)
+#define MHL_DISC_FAIL_MASK              BIT(3)
+#define MHL_EST_MASK                    BIT(2)
+
+#define SKIP_GND                        BIT(6)
+
+#define ATT_THRESH_SHIFT                0x04
+#define ATT_THRESH_MASK                 (0x03 << ATT_THRESH_SHIFT)
+#define USB_D_OEN                       BIT(3)
+#define DEGLITCH_TIME_MASK              0x07
+#define DEGLITCH_TIME_2MS               0
+#define DEGLITCH_TIME_4MS               1
+#define DEGLITCH_TIME_8MS               2
+#define DEGLITCH_TIME_16MS              3
+#define DEGLITCH_TIME_40MS              4
+#define DEGLITCH_TIME_50MS              5
+#define DEGLITCH_TIME_60MS              6
+#define DEGLITCH_TIME_128MS             7
+
+#define USB_D_OVR                       BIT(7)
+#define USB_ID_OVR                      BIT(6)
+#define DVRFLT_SEL                      BIT(5)
+#define BLOCK_RGND_INT                  BIT(4)
+#define SKIP_DEG                        BIT(3)
+#define CI2CA_POL                       BIT(2)
+#define CI2CA_WKUP                      BIT(1)
+#define SINGLE_ATT                      BIT(0)
+
+#define USB_D_ODN                       BIT(5)
+#define VBUS_CHECK                      BIT(2)
+#define RGND_INTP_MASK                  0x03
+#define RGND_INTP_OPEN                  0
+#define RGND_INTP_2K                    1
+#define RGND_INTP_1K                    2
+#define RGND_INTP_SHORT                 3
+
+/* HDMI registers */
+#define HDMI_RX_TMDS0_CCTRL1_REG        0x10
+#define HDMI_RX_TMDS_CLK_EN_REG         0x11
+#define HDMI_RX_TMDS_CH_EN_REG          0x12
+#define HDMI_RX_PLL_CALREFSEL_REG       0x17
+#define HDMI_RX_PLL_VCOCAL_REG          0x1A
+#define HDMI_RX_EQ_DATA0_REG            0x22
+#define HDMI_RX_EQ_DATA1_REG            0x23
+#define HDMI_RX_EQ_DATA2_REG            0x24
+#define HDMI_RX_EQ_DATA3_REG            0x25
+#define HDMI_RX_EQ_DATA4_REG            0x26
+#define HDMI_RX_TMDS_ZONE_CTRL_REG      0x4C
+#define HDMI_RX_TMDS_MODE_CTRL_REG      0x4D
+
+/* CBUS registers */
+#define CBUS_INT_STATUS_1_REG           0x08
+#define CBUS_INTR1_ENABLE_REG           0x09
+#define CBUS_MSC_REQ_ABORT_REASON_REG   0x0D
+#define CBUS_INT_STATUS_2_REG           0x1E
+#define CBUS_INTR2_ENABLE_REG           0x1F
+#define CBUS_LINK_CONTROL_2_REG         0x31
+#define CBUS_MHL_STATUS_REG_0           0xB0
+#define CBUS_MHL_STATUS_REG_1           0xB1
+
+#define BIT_CBUS_RESET                  BIT(3)
+#define SET_HPD_DOWNSTREAM              BIT(6)
+
+/* TPI registers */
+#define TPI_DPD_REG                     0x3D
+
+/* Timeouts in msec */
+#define T_SRC_VBUS_CBUS_TO_STABLE       200
+#define T_SRC_CBUS_FLOAT                100
+#define T_SRC_CBUS_DEGLITCH             2
+#define T_SRC_RXSENSE_DEGLITCH          110
+
+#define MHL1_MAX_CLK                    75000 /* in kHz */
+
+#define I2C_TPI_ADDR                    0x3D
+#define I2C_HDMI_ADDR                   0x49
+#define I2C_CBUS_ADDR                   0x64
+
+enum sii9234_state {
+        ST_OFF,
+        ST_D3,
+        ST_RGND_INIT,
+        ST_RGND_1K,
+        ST_RSEN_HIGH,
+        ST_MHL_ESTABLISHED,
+        ST_FAILURE_DISCOVERY,
+        ST_FAILURE,
+};
+
+struct sii9234 {
+        struct i2c_client *client[4];
+        struct drm_bridge bridge;
+        struct device *dev;
+        struct gpio_desc *gpio_reset;
+        int i2c_error;
+        struct regulator_bulk_data supplies[4];
+
+        struct mutex lock; /* Protects fields below and device registers */
+        enum sii9234_state state;
+};
+
+enum sii9234_client_id {
+        I2C_MHL,
+        I2C_TPI,
+        I2C_HDMI,
+        I2C_CBUS,
+};
+
+static const char * const sii9234_client_name[] = {
+        [I2C_MHL] = "MHL",
+        [I2C_TPI] = "TPI",
+        [I2C_HDMI] = "HDMI",
+        [I2C_CBUS] = "CBUS",
+};
+
+static int sii9234_writeb(struct sii9234 *ctx, int id, int offset,
+                          int value)
+{
+        int ret;
+        struct i2c_client *client = ctx->client[id];
+
+        if (ctx->i2c_error)
+                return ctx->i2c_error;
+
+        ret = i2c_smbus_write_byte_data(client, offset, value);
+        if (ret < 0)
+                dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n",
+                        sii9234_client_name[id], offset, value);
+        ctx->i2c_error = ret;
+
+        return ret;
+}
+
+static int sii9234_writebm(struct sii9234 *ctx, int id, int offset,
+                           int value, int mask)
+{
+        int ret;
+        struct i2c_client *client = ctx->client[id];
+
+        if (ctx->i2c_error)
+                return ctx->i2c_error;
+
+        ret = i2c_smbus_write_byte(client, offset);
+        if (ret < 0) {
+                dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
+                        sii9234_client_name[id], offset, value);
+                ctx->i2c_error = ret;
+                return ret;
+        }
+
+        ret = i2c_smbus_read_byte(client);
+        if (ret < 0) {
+                dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
+                        sii9234_client_name[id], offset, value);
+                ctx->i2c_error = ret;
+                return ret;
+        }
+
+        value = (value & mask) | (ret & ~mask);
+
+        ret = i2c_smbus_write_byte_data(client, offset, value);
+        if (ret < 0) {
+                dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
+                        sii9234_client_name[id], offset, value);
+                ctx->i2c_error = ret;
+        }
+
+        return ret;
+}
+
+static int sii9234_readb(struct sii9234 *ctx, int id, int offset)
+{
+        int ret;
+        struct i2c_client *client = ctx->client[id];
+
+        if (ctx->i2c_error)
+                return ctx->i2c_error;
+
+        ret = i2c_smbus_write_byte(client, offset);
+        if (ret < 0) {
+                dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
+                        sii9234_client_name[id], offset);
+                ctx->i2c_error = ret;
+                return ret;
+        }
+
+        ret = i2c_smbus_read_byte(client);
+        if (ret < 0) {
+                dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
+                        sii9234_client_name[id], offset);
+                ctx->i2c_error = ret;
+        }
+
+        return ret;
+}
+
+static int sii9234_clear_error(struct sii9234 *ctx)
+{
+        int ret = ctx->i2c_error;
+
+        ctx->i2c_error = 0;
+
+        return ret;
+}
+
+#define mhl_tx_writeb(sii9234, offset, value) \
+        sii9234_writeb(sii9234, I2C_MHL, offset, value)
+#define mhl_tx_writebm(sii9234, offset, value, mask) \
+        sii9234_writebm(sii9234, I2C_MHL, offset, value, mask)
+#define mhl_tx_readb(sii9234, offset) \
+        sii9234_readb(sii9234, I2C_MHL, offset)
+#define cbus_writeb(sii9234, offset, value) \
+        sii9234_writeb(sii9234, I2C_CBUS, offset, value)
+#define cbus_writebm(sii9234, offset, value, mask) \
+        sii9234_writebm(sii9234, I2C_CBUS, offset, value, mask)
+#define cbus_readb(sii9234, offset) \
+        sii9234_readb(sii9234, I2C_CBUS, offset)
+#define hdmi_writeb(sii9234, offset, value) \
+        sii9234_writeb(sii9234, I2C_HDMI, offset, value)
+#define hdmi_writebm(sii9234, offset, value, mask) \
+        sii9234_writebm(sii9234, I2C_HDMI, offset, value, mask)
+#define hdmi_readb(sii9234, offset) \
+        sii9234_readb(sii9234, I2C_HDMI, offset)
+#define tpi_writeb(sii9234, offset, value) \
+        sii9234_writeb(sii9234, I2C_TPI, offset, value)
+#define tpi_writebm(sii9234, offset, value, mask) \
+        sii9234_writebm(sii9234, I2C_TPI, offset, value, mask)
+#define tpi_readb(sii9234, offset) \
+        sii9234_readb(sii9234, I2C_TPI, offset)
+
+static u8 sii9234_tmds_control(struct sii9234 *ctx, bool enable)
+{
+        mhl_tx_writebm(ctx, MHL_TX_TMDS_CCTRL, enable ? ~0 : 0,
+                       BIT_TMDS_CCTRL_TMDS_OE);
+        mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, enable ? ~0 : 0,
+                       MHL_HPD_OUT_OVR_EN | MHL_HPD_OUT_OVR_VAL);
+        return sii9234_clear_error(ctx);
+}
+
+static int sii9234_cbus_reset(struct sii9234 *ctx)
+{
+        int i;
+
+        mhl_tx_writebm(ctx, MHL_TX_SRST, ~0, BIT_CBUS_RESET);
+        msleep(T_SRC_CBUS_DEGLITCH);
+        mhl_tx_writebm(ctx, MHL_TX_SRST, 0, BIT_CBUS_RESET);
+
+        for (i = 0; i < 4; i++) {
+                /*
+                 * Enable WRITE_STAT interrupt for writes to all
+                 * 4 MSC Status registers.
+                 */
+                cbus_writeb(ctx, 0xE0 + i, 0xF2);
+                /*
+                 * Enable SET_INT interrupt for writes to all
+                 * 4 MSC Interrupt registers.
+                 */
+                cbus_writeb(ctx, 0xF0 + i, 0xF2);
+        }
+
+        return sii9234_clear_error(ctx);
+}
+
+/* Require to chek mhl imformation of samsung in cbus_init_register */
+static int sii9234_cbus_init(struct sii9234 *ctx)
+{
+        cbus_writeb(ctx, 0x07, 0xF2);
+        cbus_writeb(ctx, 0x40, 0x03);
+        cbus_writeb(ctx, 0x42, 0x06);
+        cbus_writeb(ctx, 0x36, 0x0C);
+        cbus_writeb(ctx, 0x3D, 0xFD);
+        cbus_writeb(ctx, 0x1C, 0x01);
+        cbus_writeb(ctx, 0x1D, 0x0F);
+        cbus_writeb(ctx, 0x44, 0x02);
+        /* Setup our devcap */
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,
+                    SII9234_MHL_VERSION);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,
+                    MHL_DCAP_CAT_SOURCE);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,
+                    MHL_DCAP_VID_LINK_RGB444 | MHL_DCAP_VID_LINK_YCBCR444);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,
+                    MHL_DCAP_VT_GRAPHICS);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,
+                    MHL_DCAP_LD_GUI);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,
+                    MHL_DCAP_FEATURE_RCP_SUPPORT | MHL_DCAP_FEATURE_RAP_SUPPORT
+                        | MHL_DCAP_FEATURE_SP_SUPPORT);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,
+                    SII9234_SCRATCHPAD_SIZE);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,
+                    SII9234_INT_STAT_SIZE);
+        cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);
+        cbus_writebm(ctx, 0x31, 0x0C, 0x0C);
+        cbus_writeb(ctx, 0x30, 0x01);
+        cbus_writebm(ctx, 0x3C, 0x30, 0x38);
+        cbus_writebm(ctx, 0x22, 0x0D, 0x0F);
+        cbus_writebm(ctx, 0x2E, 0x15, 0x15);
+        cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0);
+        cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0);
+
+        return sii9234_clear_error(ctx);
+}
+
+static void force_usb_id_switch_open(struct sii9234 *ctx)
+{
+        /* Disable CBUS discovery */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0, 0x01);
+        /* Force USB ID switch to open */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
+        /* Force upstream HPD to 0 when not in MHL mode. */
+        mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x30);
+}
+
+static void release_usb_id_switch_open(struct sii9234 *ctx)
+{
+        msleep(T_SRC_CBUS_FLOAT);
+        /* Clear USB ID switch to open */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR);
+        /* Enable CBUS discovery */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 0x01);
+}
+
+static int sii9234_power_init(struct sii9234 *ctx)
+{
+        /* Force the SiI9234 into the D0 state. */
+        tpi_writeb(ctx, TPI_DPD_REG, 0x3F);
+        /* Enable TxPLL Clock */
+        hdmi_writeb(ctx, HDMI_RX_TMDS_CLK_EN_REG, 0x01);
+        /* Enable Tx Clock Path & Equalizer */
+        hdmi_writeb(ctx, HDMI_RX_TMDS_CH_EN_REG, 0x15);
+        /* Power Up TMDS */
+        mhl_tx_writeb(ctx, 0x08, 0x35);
+        return sii9234_clear_error(ctx);
+}
+
+static int sii9234_hdmi_init(struct sii9234 *ctx)
+{
+        hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
+        hdmi_writeb(ctx, HDMI_RX_PLL_CALREFSEL_REG, 0x03);
+        hdmi_writeb(ctx, HDMI_RX_PLL_VCOCAL_REG, 0x20);
+        hdmi_writeb(ctx, HDMI_RX_EQ_DATA0_REG, 0x8A);
+        hdmi_writeb(ctx, HDMI_RX_EQ_DATA1_REG, 0x6A);
+        hdmi_writeb(ctx, HDMI_RX_EQ_DATA2_REG, 0xAA);
+        hdmi_writeb(ctx, HDMI_RX_EQ_DATA3_REG, 0xCA);
+        hdmi_writeb(ctx, HDMI_RX_EQ_DATA4_REG, 0xEA);
+        hdmi_writeb(ctx, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0);
+        hdmi_writeb(ctx, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00);
+        mhl_tx_writeb(ctx, MHL_TX_TMDS_CCTRL, 0x34);
+        hdmi_writeb(ctx, 0x45, 0x44);
+        hdmi_writeb(ctx, 0x31, 0x0A);
+        hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
+
+        return sii9234_clear_error(ctx);
+}
+
+static int sii9234_mhl_tx_ctl_int(struct sii9234 *ctx)
+{
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0xD0);
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL2_REG, 0xFC);
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL4_REG, 0xEB);
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL7_REG, 0x0C);
+
+        return sii9234_clear_error(ctx);
+}
+
+static int sii9234_reset(struct sii9234 *ctx)
+{
+        int ret;
+
+        sii9234_clear_error(ctx);
+
+        ret = sii9234_power_init(ctx);
+        if (ret < 0)
+                return ret;
+        ret = sii9234_cbus_reset(ctx);
+        if (ret < 0)
+                return ret;
+        ret = sii9234_hdmi_init(ctx);
+        if (ret < 0)
+                return ret;
+        ret = sii9234_mhl_tx_ctl_int(ctx);
+        if (ret < 0)
+                return ret;
+
+        /* Enable HDCP Compliance safety */
+        mhl_tx_writeb(ctx, 0x2B, 0x01);
+        /* CBUS discovery cycle time for each drive and float = 150us */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0x04, 0x06);
+        /* Clear bit 6 (reg_skip_rgnd) */
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved */
+                      | 2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS);
+        /*
+         * Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel
+         * 1.8V CBUS VTH & GND threshold
+         * to meet CTS 3.3.7.2 spec
+         */
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
+        cbus_writebm(ctx, CBUS_LINK_CONTROL_2_REG, ~0, MHL_INIT_TIMEOUT);
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL6_REG, 0xA0);
+        /* RGND & single discovery attempt (RGND blocking) */
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |
+                      DVRFLT_SEL | SINGLE_ATT);
+        /* Use VBUS path of discovery state machine */
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL8_REG, 0);
+        /* 0x92[3] sets the CBUS / ID switch */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
+        /*
+         * To allow RGND engine to operate correctly.
+         * When moving the chip from D2 to D0 (power up, init regs)
+         * the values should be
+         * 94[1:0] = 01  reg_cbusmhl_pup_sel[1:0] should be set for 5k
+         * 93[7:6] = 10  reg_cbusdisc_pup_sel[1:0] should be
+         * set for 10k (default)
+         * 93[5:4] = 00  reg_cbusidle_pup_sel[1:0] = open (default)
+         */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
+        /*
+         * Change from CC to 8C to match 5K
+         * to meet CTS 3.3.72 spec
+         */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
+        /* Configure the interrupt as active high */
+        mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x06);
+
+        msleep(25);
+
+        /* Release usb_id switch */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0,  USB_ID_OVR);
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL1_REG, 0x27);
+
+        ret = sii9234_clear_error(ctx);
+        if (ret < 0)
+                return ret;
+        ret = sii9234_cbus_init(ctx);
+        if (ret < 0)
+                return ret;
+
+        /* Enable Auto soft reset on SCDT = 0 */
+        mhl_tx_writeb(ctx, 0x05, 0x04);
+        /* HDMI Transcode mode enable */
+        mhl_tx_writeb(ctx, 0x0D, 0x1C);
+        mhl_tx_writeb(ctx, MHL_TX_INTR4_ENABLE_REG,
+                      RGND_READY_MASK | CBUS_LKOUT_MASK
+                        | MHL_DISC_FAIL_MASK | MHL_EST_MASK);
+        mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 0x60);
+
+        /* This point is very important before measure RGND impedance */
+        force_usb_id_switch_open(ctx);
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, 0, 0xF0);
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL5_REG, 0, 0x03);
+        release_usb_id_switch_open(ctx);
+
+        /* Force upstream HPD to 0 when not in MHL mode */
+        mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 1 << 5);
+        mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, ~0, 1 << 4);
+
+        return sii9234_clear_error(ctx);
+}
+
+static int sii9234_goto_d3(struct sii9234 *ctx)
+{
+        int ret;
+
+        dev_dbg(ctx->dev, "sii9234: detection started d3\n");
+
+        ret = sii9234_reset(ctx);
+        if (ret < 0)
+                goto exit;
+
+        hdmi_writeb(ctx, 0x01, 0x03);
+        tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
+        /* I2C above is expected to fail because power goes down */
+        sii9234_clear_error(ctx);
+
+        ctx->state = ST_D3;
+
+        return 0;
+ exit:
+        dev_err(ctx->dev, "%s failed\n", __func__);
+        return -1;
+}
+
+static int sii9234_hw_on(struct sii9234 *ctx)
+{
+        return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+}
+
+static void sii9234_hw_off(struct sii9234 *ctx)
+{
+        gpiod_set_value(ctx->gpio_reset, 1);
+        msleep(20);
+        regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+}
+
+static void sii9234_hw_reset(struct sii9234 *ctx)
+{
+        gpiod_set_value(ctx->gpio_reset, 1);
+        msleep(20);
+        gpiod_set_value(ctx->gpio_reset, 0);
+}
+
+static void sii9234_cable_in(struct sii9234 *ctx)
+{
+        int ret;
+
+        mutex_lock(&ctx->lock);
+        if (ctx->state != ST_OFF)
+                goto unlock;
+        ret = sii9234_hw_on(ctx);
+        if (ret < 0)
+                goto unlock;
+
+        sii9234_hw_reset(ctx);
+        sii9234_goto_d3(ctx);
+        /* To avoid irq storm, when hw is in meta state */
+        enable_irq(to_i2c_client(ctx->dev)->irq);
+
+unlock:
+        mutex_unlock(&ctx->lock);
+}
+
+static void sii9234_cable_out(struct sii9234 *ctx)
+{
+        mutex_lock(&ctx->lock);
+
+        if (ctx->state == ST_OFF)
+                goto unlock;
+
+        disable_irq(to_i2c_client(ctx->dev)->irq);
+        tpi_writeb(ctx, TPI_DPD_REG, 0);
+        /* Turn on&off hpd festure for only QCT HDMI */
+        sii9234_hw_off(ctx);
+
+        ctx->state = ST_OFF;
+
+unlock:
+        mutex_unlock(&ctx->lock);
+}
+
+static enum sii9234_state sii9234_rgnd_ready_irq(struct sii9234 *ctx)
+{
+        int value;
+
+        if (ctx->state == ST_D3) {
+                int ret;
+
+                dev_dbg(ctx->dev, "RGND_READY_INT\n");
+                sii9234_hw_reset(ctx);
+
+                ret = sii9234_reset(ctx);
+                if (ret < 0) {
+                        dev_err(ctx->dev, "sii9234_reset() failed\n");
+                        return ST_FAILURE;
+                }
+
+                return ST_RGND_INIT;
+        }
+
+        /* Got interrupt in inappropriate state */
+        if (ctx->state != ST_RGND_INIT)
+                return ST_FAILURE;
+
+        value = mhl_tx_readb(ctx, MHL_TX_STAT2_REG);
+        if (sii9234_clear_error(ctx))
+                return ST_FAILURE;
+
+        if ((value & RGND_INTP_MASK) != RGND_INTP_1K) {
+                dev_warn(ctx->dev, "RGND is not 1k\n");
+                return ST_RGND_INIT;
+        }
+        dev_dbg(ctx->dev, "RGND 1K!!\n");
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
+        mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, 0x05);
+        if (sii9234_clear_error(ctx))
+                return ST_FAILURE;
+
+        msleep(T_SRC_VBUS_CBUS_TO_STABLE);
+        return ST_RGND_1K;
+}
+
+static enum sii9234_state sii9234_mhl_established(struct sii9234 *ctx)
+{
+        dev_dbg(ctx->dev, "mhl est interrupt\n");
+
+        /* Discovery override */
+        mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0x10);
+        /* Increase DDC translation layer timer (byte mode) */
+        cbus_writeb(ctx, 0x07, 0x32);
+        cbus_writebm(ctx, 0x44, ~0, 1 << 1);
+        /* Keep the discovery enabled. Need RGND interrupt */
+        mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 1);
+        mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG,
+                      RSEN_CHANGE_INT_MASK | HPD_CHANGE_INT_MASK);
+
+        if (sii9234_clear_error(ctx))
+                return ST_FAILURE;
+
+        return ST_MHL_ESTABLISHED;
+}
+
+static enum sii9234_state sii9234_hpd_change(struct sii9234 *ctx)
+{
+        int value;
+
+        value = cbus_readb(ctx, CBUS_MSC_REQ_ABORT_REASON_REG);
+        if (sii9234_clear_error(ctx))
+                return ST_FAILURE;
+
+        if (value & SET_HPD_DOWNSTREAM) {
+                /* Downstream HPD High, Enable TMDS */
+                sii9234_tmds_control(ctx, true);
+        } else {
+                /* Downstream HPD Low, Disable TMDS */
+                sii9234_tmds_control(ctx, false);
+        }
+
+        return ctx->state;
+}
+
+static enum sii9234_state sii9234_rsen_change(struct sii9234 *ctx)
+{
+        int value;
+
+        /* Work_around code to handle wrong interrupt */
+        if (ctx->state != ST_RGND_1K) {
+                dev_err(ctx->dev, "RSEN_HIGH without RGND_1K\n");
+                return ST_FAILURE;
+        }
+        value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
+        if (value < 0)
+                return ST_FAILURE;
+
+        if (value & RSEN_STATUS) {
+                dev_dbg(ctx->dev, "MHL cable connected.. RSEN High\n");
+                return ST_RSEN_HIGH;
+        }
+        dev_dbg(ctx->dev, "RSEN lost\n");
+        /*
+         * Once RSEN loss is confirmed,we need to check
+         * based on cable status and chip power status,whether
+         * it is SINK Loss(HDMI cable not connected, TV Off)
+         * or MHL cable disconnection
+         * TODO: Define the below mhl_disconnection()
+         */
+        msleep(T_SRC_RXSENSE_DEGLITCH);
+        value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
+        if (value < 0)
+                return ST_FAILURE;
+        dev_dbg(ctx->dev, "sys_stat: %x\n", value);
+
+        if (value & RSEN_STATUS) {
+                dev_dbg(ctx->dev, "RSEN recovery\n");
+                return ST_RSEN_HIGH;
+        }
+        dev_dbg(ctx->dev, "RSEN Really LOW\n");
+        /* To meet CTS 3.3.22.2 spec */
+        sii9234_tmds_control(ctx, false);
+        force_usb_id_switch_open(ctx);
+        release_usb_id_switch_open(ctx);
+
+        return ST_FAILURE;
+}
+
+static irqreturn_t sii9234_irq_thread(int irq, void *data)
+{
+        struct sii9234 *ctx = data;
+        int intr1, intr4;
+        int intr1_en, intr4_en;
+        int cbus_intr1, cbus_intr2;
+
+        dev_dbg(ctx->dev, "%s\n", __func__);
+
+        mutex_lock(&ctx->lock);
+
+        intr1 = mhl_tx_readb(ctx, MHL_TX_INTR1_REG);
+        intr4 = mhl_tx_readb(ctx, MHL_TX_INTR4_REG);
+        intr1_en = mhl_tx_readb(ctx, MHL_TX_INTR1_ENABLE_REG);
+        intr4_en = mhl_tx_readb(ctx, MHL_TX_INTR4_ENABLE_REG);
+        cbus_intr1 = cbus_readb(ctx, CBUS_INT_STATUS_1_REG);
+        cbus_intr2 = cbus_readb(ctx, CBUS_INT_STATUS_2_REG);
+
+        if (sii9234_clear_error(ctx))
+                goto done;
+
+        dev_dbg(ctx->dev, "irq %02x/%02x %02x/%02x %02x/%02x\n",
+                intr1, intr1_en, intr4, intr4_en, cbus_intr1, cbus_intr2);
+
+        if (intr4 & RGND_READY_INT)
+                ctx->state = sii9234_rgnd_ready_irq(ctx);
+        if (intr1 & RSEN_CHANGE_INT)
+                ctx->state = sii9234_rsen_change(ctx);
+        if (intr4 & MHL_EST_INT)
+                ctx->state = sii9234_mhl_established(ctx);
+        if (intr1 & HPD_CHANGE_INT)
+                ctx->state = sii9234_hpd_change(ctx);
+        if (intr4 & CBUS_LKOUT_INT)
+                ctx->state = ST_FAILURE;
+        if (intr4 & MHL_DISC_FAIL_INT)
+                ctx->state = ST_FAILURE_DISCOVERY;
+
+ done:
+        /* Clean interrupt status and pending flags */
+        mhl_tx_writeb(ctx, MHL_TX_INTR1_REG, intr1);
+        mhl_tx_writeb(ctx, MHL_TX_INTR4_REG, intr4);
+        cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF);
+        cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF);
+        cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1);
+        cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);
+
+        sii9234_clear_error(ctx);
+
+        if (ctx->state == ST_FAILURE) {
+                dev_dbg(ctx->dev, "try to reset after failure\n");
+                sii9234_hw_reset(ctx);
+                sii9234_goto_d3(ctx);
+        }
+
+        if (ctx->state == ST_FAILURE_DISCOVERY) {
+                dev_err(ctx->dev, "discovery failed, no power for MHL?\n");
+                tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
+                ctx->state = ST_D3;
+        }
+
+        mutex_unlock(&ctx->lock);
+
+        return IRQ_HANDLED;
+}
+
+static int sii9234_init_resources(struct sii9234 *ctx,
+                                  struct i2c_client *client)
+{
+        struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+        int ret;
+
+        if (!ctx->dev->of_node) {
+                dev_err(ctx->dev, "not DT device\n");
+                return -ENODEV;
+        }
+
+        ctx->gpio_reset = devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_LOW);
+        if (IS_ERR(ctx->gpio_reset)) {
+                dev_err(ctx->dev, "failed to get reset gpio from DT\n");
+                return PTR_ERR(ctx->gpio_reset);
+        }
+
+        ctx->supplies[0].supply = "avcc12";
+        ctx->supplies[1].supply = "avcc33";
+        ctx->supplies[2].supply = "iovcc18";
+        ctx->supplies[3].supply = "cvcc12";
+        ret = devm_regulator_bulk_get(ctx->dev, 4, ctx->supplies);
+        if (ret) {
+                dev_err(ctx->dev, "regulator_bulk failed\n");
+                return ret;
+        }
+
+        ctx->client[I2C_MHL] = client;
+
+        ctx->client[I2C_TPI] = i2c_new_dummy(adapter, I2C_TPI_ADDR);
+        if (!ctx->client[I2C_TPI]) {
+                dev_err(ctx->dev, "failed to create TPI client\n");
+                return -ENODEV;
+        }
+
+        ctx->client[I2C_HDMI] = i2c_new_dummy(adapter, I2C_HDMI_ADDR);
+        if (!ctx->client[I2C_HDMI]) {
+                dev_err(ctx->dev, "failed to create HDMI RX client\n");
+                goto fail_tpi;
+        }
+
+        ctx->client[I2C_CBUS] = i2c_new_dummy(adapter, I2C_CBUS_ADDR);
+        if (!ctx->client[I2C_CBUS]) {
+                dev_err(ctx->dev, "failed to create CBUS client\n");
+                goto fail_hdmi;
+        }
+
+        return 0;
+
+fail_hdmi:
+        i2c_unregister_device(ctx->client[I2C_HDMI]);
+fail_tpi:
+        i2c_unregister_device(ctx->client[I2C_TPI]);
+
+        return -ENODEV;
+}
+
+static void sii9234_deinit_resources(struct sii9234 *ctx)
+{
+        i2c_unregister_device(ctx->client[I2C_CBUS]);
+        i2c_unregister_device(ctx->client[I2C_HDMI]);
+        i2c_unregister_device(ctx->client[I2C_TPI]);
+}
+
+static inline struct sii9234 *bridge_to_sii9234(struct drm_bridge *bridge)
+{
+        return container_of(bridge, struct sii9234, bridge);
+}
+
+static enum drm_mode_status sii9234_mode_valid(struct drm_bridge *bridge,
+                                         const struct drm_display_mode *mode)
+{
+        if (mode->clock > MHL1_MAX_CLK)
+                return MODE_CLOCK_HIGH;
+
+        return MODE_OK;
+}
+
+static const struct drm_bridge_funcs sii9234_bridge_funcs = {
+        .mode_valid = sii9234_mode_valid,
+};
+
+static int sii9234_probe(struct i2c_client *client,
+                         const struct i2c_device_id *id)
+{
+        struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+        struct sii9234 *ctx;
+        struct device *dev = &client->dev;
+        int ret;
+
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+        if (!ctx)
+                return -ENOMEM;
+
+        ctx->dev = dev;
+        mutex_init(&ctx->lock);
+
+        if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+                dev_err(dev, "I2C adapter lacks SMBUS feature\n");
+                return -EIO;
+        }
+
+        if (!client->irq) {
+                dev_err(dev, "no irq provided\n");
+                return -EINVAL;
+        }
+
+        irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
+        ret = devm_request_threaded_irq(dev, client->irq, NULL,
+                                        sii9234_irq_thread,
+                                        IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+                                        "sii9234", ctx);
+        if (ret < 0) {
+                dev_err(dev, "failed to install IRQ handler\n");
+                return ret;
+        }
+
+        ret = sii9234_init_resources(ctx, client);
+        if (ret < 0)
+                return ret;
+
+        i2c_set_clientdata(client, ctx);
+
+        ctx->bridge.funcs = &sii9234_bridge_funcs;
+        ctx->bridge.of_node = dev->of_node;
+        drm_bridge_add(&ctx->bridge);
+
+        sii9234_cable_in(ctx);
+
+        return 0;
+}
+
+static int sii9234_remove(struct i2c_client *client)
+{
+        struct sii9234 *ctx = i2c_get_clientdata(client);
+
+        sii9234_cable_out(ctx);
+        drm_bridge_remove(&ctx->bridge);
+        sii9234_deinit_resources(ctx);
+
+        return 0;
+}
+
+static const struct of_device_id sii9234_dt_match[] = {
+        { .compatible = "sil,sii9234" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, sii9234_dt_match);
+
+static const struct i2c_device_id sii9234_id[] = {
+        { "SII9234", 0 },
+        { },
+};
+MODULE_DEVICE_TABLE(i2c, sii9234_id);
+
+static struct i2c_driver sii9234_driver = {
+        .driver = {
+                .name   = "sii9234",
+                .of_match_table = sii9234_dt_match,
+        },
+        .probe = sii9234_probe,
+        .remove = sii9234_remove,
+        .id_table = sii9234_id,
+};
+
+module_i2c_driver(sii9234_driver);
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 5131bfb94f06..b7eb704d0a8a 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -28,6 +28,8 @@
 #include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 
+#include <media/rc-core.h>
+
 #include "sil-sii8620.h"
 
 #define SII8620_BURST_BUF_LEN 288
@@ -58,6 +60,7 @@ enum sii8620_mt_state {
 struct sii8620 {
         struct drm_bridge bridge;
         struct device *dev;
+        struct rc_dev *rc_dev;
         struct clk *clk_xtal;
         struct gpio_desc *gpio_reset;
         struct gpio_desc *gpio_int;
@@ -431,6 +434,16 @@ static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
         sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
 }
 
+static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code)
+{
+        sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code);
+}
+
+static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code)
+{
+        sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code);
+}
+
 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
                                         struct sii8620_mt_msg *msg)
 {
@@ -1753,6 +1766,25 @@ static void sii8620_send_features(struct sii8620 *ctx)
         sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
 }
 
+static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode)
+{
+        bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK);
+
+        scancode &= MHL_RCP_KEY_ID_MASK;
+
+        if (!ctx->rc_dev) {
+                dev_dbg(ctx->dev, "RCP input device not initialized\n");
+                return false;
+        }
+
+        if (pressed)
+                rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0);
+        else
+                rc_keyup(ctx->rc_dev);
+
+        return true;
+}
+
 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
 {
         u8 ints[MHL_INT_SIZE];
@@ -1804,19 +1836,25 @@ static void sii8620_msc_mt_done(struct sii8620 *ctx)
 
 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
 {
-        struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
+        struct sii8620_mt_msg *msg;
         u8 buf[2];
 
-        if (!msg)
-                return;
-
         sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
 
         switch (buf[0]) {
         case MHL_MSC_MSG_RAPK:
+                msg = sii8620_msc_msg_first(ctx);
+                if (!msg)
+                        return;
                 msg->ret = buf[1];
                 ctx->mt_state = MT_STATE_DONE;
                 break;
+        case MHL_MSC_MSG_RCP:
+                if (!sii8620_rcp_consume(ctx, buf[1]))
+                        sii8620_mt_rcpe(ctx,
+                                        MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE);
+                sii8620_mt_rcpk(ctx, buf[1]);
+                break;
         default:
                 dev_err(ctx->dev, "%s message type %d,%d not supported",
                         __func__, buf[0], buf[1]);
@@ -2102,11 +2140,57 @@ static void sii8620_cable_in(struct sii8620 *ctx)
         enable_irq(to_i2c_client(ctx->dev)->irq);
 }
 
+static void sii8620_init_rcp_input_dev(struct sii8620 *ctx)
+{
+        struct rc_dev *rc_dev;
+        int ret;
+
+        rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE);
+        if (!rc_dev) {
+                dev_err(ctx->dev, "Failed to allocate RC device\n");
+                ctx->error = -ENOMEM;
+                return;
+        }
+
+        rc_dev->input_phys = "sii8620/input0";
+        rc_dev->input_id.bustype = BUS_VIRTUAL;
+        rc_dev->map_name = RC_MAP_CEC;
+        rc_dev->allowed_protocols = RC_PROTO_BIT_CEC;
+        rc_dev->driver_name = "sii8620";
+        rc_dev->device_name = "sii8620";
+
+        ret = rc_register_device(rc_dev);
+
+        if (ret) {
+                dev_err(ctx->dev, "Failed to register RC device\n");
+                ctx->error = ret;
+                rc_free_device(ctx->rc_dev);
+                return;
+        }
+        ctx->rc_dev = rc_dev;
+}
+
 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
 {
         return container_of(bridge, struct sii8620, bridge);
 }
 
+static int sii8620_attach(struct drm_bridge *bridge)
+{
+        struct sii8620 *ctx = bridge_to_sii8620(bridge);
+
+        sii8620_init_rcp_input_dev(ctx);
+
+        return sii8620_clear_error(ctx);
+}
+
+static void sii8620_detach(struct drm_bridge *bridge)
+{
+        struct sii8620 *ctx = bridge_to_sii8620(bridge);
+
+        rc_unregister_device(ctx->rc_dev);
+}
+
 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
                                const struct drm_display_mode *mode,
                                struct drm_display_mode *adjusted_mode)
@@ -2151,6 +2235,8 @@ end:
 }
 
 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
+        .attach = sii8620_attach,
+        .detach = sii8620_detach,
         .mode_fixup = sii8620_mode_fixup,
 };
 
@@ -2217,8 +2303,8 @@ static int sii8620_remove(struct i2c_client *client)
         struct sii8620 *ctx = i2c_get_clientdata(client);
 
         disable_irq(to_i2c_client(ctx->dev)->irq);
-        drm_bridge_remove(&ctx->bridge);
         sii8620_hw_off(ctx);
+        drm_bridge_remove(&ctx->bridge);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f4f633a0dffa..d9cca4fd66ec 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -221,7 +221,6 @@ struct dw_mipi_dsi {
         struct drm_bridge bridge;
         struct mipi_dsi_host dsi_host;
         struct drm_bridge *panel_bridge;
-        bool is_panel_bridge;
         struct device *dev;
         void __iomem *base;
 
@@ -297,7 +296,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
                 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
                 if (IS_ERR(bridge))
                         return PTR_ERR(bridge);
-                dsi->is_panel_bridge = true;
         }
 
         dsi->panel_bridge = bridge;
@@ -312,8 +310,7 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 {
         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 
-        if (dsi->is_panel_bridge)
-                drm_panel_bridge_remove(dsi->panel_bridge);
+        drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
 
         drm_bridge_remove(&dsi->bridge);
 
diff --git a/drivers/gpu/drm/cirrus/cirrus_mode.c b/drivers/gpu/drm/cirrus/cirrus_mode.c
index a4c4a465b385..cd23b1b28259 100644
--- a/drivers/gpu/drm/cirrus/cirrus_mode.c
+++ b/drivers/gpu/drm/cirrus/cirrus_mode.c
@@ -457,7 +457,7 @@ static struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
         int enc_id = connector->encoder_ids[0];
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 366c56fe5f58..562494873ca5 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -182,9 +182,6 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
         for (i = 0; i < state->num_private_objs; i++) {
                 struct drm_private_obj *obj = state->private_objs[i].ptr;
 
-                if (!obj)
-                        continue;
-
                 obj->funcs->atomic_destroy_state(obj,
                                                  state->private_objs[i].state);
                 state->private_objs[i].ptr = NULL;
@@ -718,7 +715,7 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
         struct drm_mode_config *config = &dev->mode_config;
 
         if (property == config->prop_fb_id) {
-                struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, val);
+                struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, NULL, val);
                 drm_atomic_set_fb_for_plane(state, fb);
                 if (fb)
                         drm_framebuffer_put(fb);
@@ -734,7 +731,7 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
                         return -EINVAL;
 
         } else if (property == config->prop_crtc_id) {
-                struct drm_crtc *crtc = drm_crtc_find(dev, val);
+                struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
                 return drm_atomic_set_crtc_for_plane(state, crtc);
         } else if (property == config->prop_crtc_x) {
                 state->crtc_x = U642I64(val);
@@ -1149,7 +1146,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector,
         struct drm_mode_config *config = &dev->mode_config;
 
         if (property == config->prop_crtc_id) {
-                struct drm_crtc *crtc = drm_crtc_find(dev, val);
+                struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
                 return drm_atomic_set_crtc_for_connector(state, crtc);
         } else if (property == config->dpms_property) {
                 /* setting DPMS property requires special handling, which
@@ -2259,7 +2256,7 @@ retry:
                         goto out;
                 }
 
-                obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_ANY);
+                obj = drm_mode_object_find(dev, file_priv, obj_id, DRM_MODE_OBJECT_ANY);
                 if (!obj) {
                         ret = -ENOENT;
                         goto out;
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 01c34bc5b5b0..ae56d91433ff 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1704,7 +1704,7 @@ crtc_or_fake_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
  * drm_atomic_helper_commit_cleanup_done().
  *
  * This is all implemented by in drm_atomic_helper_commit(), giving drivers a
- * complete and esay-to-use default implementation of the atomic_commit() hook.
+ * complete and easy-to-use default implementation of the atomic_commit() hook.
  *
  * The tracking of asynchronously executed and still pending commits is done
  * using the core structure &drm_crtc_commit.
@@ -1819,7 +1819,7 @@ EXPORT_SYMBOL(drm_atomic_helper_setup_commit);
  * This function waits for all preceeding commits that touch the same CRTC as
  * @old_state to both be committed to the hardware (as signalled by
  * drm_atomic_helper_commit_hw_done) and executed by the hardware (as signalled
- * by calling drm_crtc_vblank_send_event() on the &drm_crtc_state.event).
+ * by calling drm_crtc_send_vblank_event() on the &drm_crtc_state.event).
  *
  * This is part of the atomic helper support for nonblocking commits, see
  * drm_atomic_helper_setup_commit() for an overview.
@@ -3052,6 +3052,7 @@ out:
                 drm_modeset_backoff(&ctx);
         }
 
+        drm_atomic_state_put(state);
         drm_modeset_drop_locks(&ctx);
         drm_modeset_acquire_fini(&ctx);
 
@@ -3206,7 +3207,7 @@ struct drm_encoder *
 drm_atomic_helper_best_encoder(struct drm_connector *connector)
 {
         WARN_ON(connector->encoder_ids[1]);
-        return drm_encoder_find(connector->dev, connector->encoder_ids[0]);
+        return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
 }
 EXPORT_SYMBOL(drm_atomic_helper_best_encoder);
 
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index fe0982708e95..0d002b045bd2 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -230,7 +230,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
         if (!crtc)
                 return -ENOENT;
 
@@ -308,7 +308,7 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
         if (!crtc)
                 return -ENOENT;
 
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index d8ca526ca4ee..704fc8934616 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1310,7 +1310,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
 
         memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo));
 
-        connector = drm_connector_lookup(dev, out_resp->connector_id);
+        connector = drm_connector_lookup(dev, file_priv, out_resp->connector_id);
         if (!connector)
                 return -ENOENT;
 
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 68b4e976d5e0..f0556e654116 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -402,7 +402,7 @@ int drm_mode_getcrtc(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        crtc = drm_crtc_find(dev, crtc_resp->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, crtc_resp->crtc_id);
         if (!crtc)
                 return -ENOENT;
 
@@ -569,7 +569,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
         if (crtc_req->x & 0xffff0000 || crtc_req->y & 0xffff0000)
                 return -ERANGE;
 
-        crtc = drm_crtc_find(dev, crtc_req->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, crtc_req->crtc_id);
         if (!crtc) {
                 DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id);
                 return -ENOENT;
@@ -595,7 +595,7 @@ retry:
                         /* Make refcounting symmetric with the lookup path. */
                         drm_framebuffer_get(fb);
                 } else {
-                        fb = drm_framebuffer_lookup(dev, crtc_req->fb_id);
+                        fb = drm_framebuffer_lookup(dev, file_priv, crtc_req->fb_id);
                         if (!fb) {
                                 DRM_DEBUG_KMS("Unknown FB ID%d\n",
                                                 crtc_req->fb_id);
@@ -680,7 +680,7 @@ retry:
                                 goto out;
                         }
 
-                        connector = drm_connector_lookup(dev, out_id);
+                        connector = drm_connector_lookup(dev, file_priv, out_id);
                         if (!connector) {
                                 DRM_DEBUG_KMS("Connector id %d unknown\n",
                                                 out_id);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index eab36a460638..5a84c3bc915d 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -562,12 +562,12 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set,
          * Allocate space for the backup of all (non-pointer) encoder and
          * connector data.
          */
-        save_encoder_crtcs = kzalloc(dev->mode_config.num_encoder *
+        save_encoder_crtcs = kcalloc(dev->mode_config.num_encoder,
                                 sizeof(struct drm_crtc *), GFP_KERNEL);
         if (!save_encoder_crtcs)
                 return -ENOMEM;
 
-        save_connector_encoders = kzalloc(dev->mode_config.num_connector *
+        save_connector_encoders = kcalloc(dev->mode_config.num_connector,
                                 sizeof(struct drm_encoder *), GFP_KERNEL);
         if (!save_connector_encoders) {
                 kfree(save_encoder_crtcs);
diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h
index a43582076b20..9ebb8841778c 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -106,6 +106,7 @@ int drm_mode_object_add(struct drm_device *dev, struct drm_mode_object *obj,
 void drm_mode_object_register(struct drm_device *dev,
                               struct drm_mode_object *obj);
 struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
+                                               struct drm_file *file_priv,
                                                uint32_t id, uint32_t type);
 void drm_mode_object_unregister(struct drm_device *dev,
                                 struct drm_mode_object *object);
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 08af8d6b844b..b3d68964b407 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 u8 drm_dp_link_rate_to_bw_code(int link_rate)
 {
         switch (link_rate) {
-        case 162000:
         default:
+                WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
+                     DP_LINK_BW_1_62);
+        case 162000:
                 return DP_LINK_BW_1_62;
         case 270000:
                 return DP_LINK_BW_2_7;
@@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
 int drm_dp_bw_code_to_link_rate(u8 link_bw)
 {
         switch (link_bw) {
-        case DP_LINK_BW_1_62:
         default:
+                WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
+        case DP_LINK_BW_1_62:
                 return 162000;
         case DP_LINK_BW_2_7:
                 return 270000;
diff --git a/drivers/gpu/drm/drm_encoder.c b/drivers/gpu/drm/drm_encoder.c
index 0708779840d2..43f644844b83 100644
--- a/drivers/gpu/drm/drm_encoder.c
+++ b/drivers/gpu/drm/drm_encoder.c
@@ -220,7 +220,7 @@ int drm_mode_getencoder(struct drm_device *dev, void *data,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        encoder = drm_encoder_find(dev, enc_resp->encoder_id);
+        encoder = drm_encoder_find(dev, file_priv, enc_resp->encoder_id);
         if (!encoder)
                 return -ENOENT;
 
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 6a31d13f2f81..116d1f1337c7 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2266,7 +2266,7 @@ static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
         if (modes[n] == NULL)
                 return best_score;
 
-        crtcs = kzalloc(fb_helper->connector_count *
+        crtcs = kcalloc(fb_helper->connector_count,
                         sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
         if (!crtcs)
                 return best_score;
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index af279844d7ce..2affe53f3fda 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -381,7 +381,7 @@ int drm_mode_rmfb(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        fb = drm_framebuffer_lookup(dev, *id);
+        fb = drm_framebuffer_lookup(dev, file_priv, *id);
         if (!fb)
                 return -ENOENT;
 
@@ -450,7 +450,7 @@ int drm_mode_getfb(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        fb = drm_framebuffer_lookup(dev, r->fb_id);
+        fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
         if (!fb)
                 return -ENOENT;
 
@@ -515,7 +515,7 @@ int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        fb = drm_framebuffer_lookup(dev, r->fb_id);
+        fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
         if (!fb)
                 return -ENOENT;
 
@@ -688,12 +688,13 @@ EXPORT_SYMBOL(drm_framebuffer_init);
  * again, using drm_framebuffer_put().
  */
 struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev,
+                                               struct drm_file *file_priv,
                                                uint32_t id)
 {
         struct drm_mode_object *obj;
         struct drm_framebuffer *fb = NULL;
 
-        obj = __drm_mode_object_find(dev, id, DRM_MODE_OBJECT_FB);
+        obj = __drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_FB);
         if (obj)
                 fb = obj_to_fb(obj);
         return fb;
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
index fc7e995541c9..aa8cb9bfa499 100644
--- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
+++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
@@ -27,19 +27,24 @@
  * DOC: overview
  *
  * This library provides helpers for drivers that don't subclass
- * &drm_framebuffer and and use &drm_gem_object for their backing storage.
+ * &drm_framebuffer and use &drm_gem_object for their backing storage.
  *
  * Drivers without additional needs to validate framebuffers can simply use
- * drm_gem_fb_create() and everything is wired up automatically. But all
- * parts can be used individually.
+ * drm_gem_fb_create() and everything is wired up automatically. Other drivers
+ * can use all parts independently.
  */
 
 /**
- * drm_gem_fb_get_obj() - Get GEM object for framebuffer
- * @fb: The framebuffer
- * @plane: Which plane
+ * drm_gem_fb_get_obj() - Get GEM object backing the framebuffer
+ * @fb: Framebuffer
+ * @plane: Plane index
  *
- * Returns the GEM object for given framebuffer.
+ * No additional reference is taken beyond the one that the &drm_frambuffer
+ * already holds.
+ *
+ * Returns:
+ * Pointer to &drm_gem_object for the given framebuffer and plane index or NULL
+ * if it does not exist.
  */
 struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb,
                                           unsigned int plane)
@@ -82,7 +87,7 @@ drm_gem_fb_alloc(struct drm_device *dev,
 
 /**
  * drm_gem_fb_destroy - Free GEM backed framebuffer
- * @fb: DRM framebuffer
+ * @fb: Framebuffer
  *
  * Frees a GEM backed framebuffer with its backing buffer(s) and the structure
  * itself. Drivers can use this as their &drm_framebuffer_funcs->destroy
@@ -102,12 +107,13 @@ EXPORT_SYMBOL(drm_gem_fb_destroy);
 
 /**
  * drm_gem_fb_create_handle - Create handle for GEM backed framebuffer
- * @fb: DRM framebuffer
- * @file: drm file
- * @handle: handle created
+ * @fb: Framebuffer
+ * @file: DRM file to register the handle for
+ * @handle: Pointer to return the created handle
  *
+ * This function creates a handle for the GEM object backing the framebuffer.
  * Drivers can use this as their &drm_framebuffer_funcs->create_handle
- * callback.
+ * callback. The GETFB IOCTL calls into this callback.
  *
  * Returns:
  * 0 on success or a negative error code on failure.
@@ -120,18 +126,21 @@ int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file,
 EXPORT_SYMBOL(drm_gem_fb_create_handle);
 
 /**
- * drm_gem_fb_create_with_funcs() - helper function for the
+ * drm_gem_fb_create_with_funcs() - Helper function for the
  *                                  &drm_mode_config_funcs.fb_create
  *                                  callback
  * @dev: DRM device
- * @file: drm file for the ioctl call
- * @mode_cmd: metadata from the userspace fb creation request
+ * @file: DRM file that holds the GEM handle(s) backing the framebuffer
+ * @mode_cmd: Metadata from the userspace framebuffer creation request
  * @funcs: vtable to be used for the new framebuffer object
  *
  * This can be used to set &drm_framebuffer_funcs for drivers that need the
  * &drm_framebuffer_funcs.dirty callback. Use drm_gem_fb_create() if you don't
  * need to change &drm_framebuffer_funcs.
  * The function does buffer size validation.
+ *
+ * Returns:
+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
  */
 struct drm_framebuffer *
 drm_gem_fb_create_with_funcs(struct drm_device *dev, struct drm_file *file,
@@ -192,15 +201,26 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs = {
 };
 
 /**
- * drm_gem_fb_create() - &drm_mode_config_funcs.fb_create callback function
+ * drm_gem_fb_create() - Helper function for the
+ *                       &drm_mode_config_funcs.fb_create callback
  * @dev: DRM device
- * @file: drm file for the ioctl call
- * @mode_cmd: metadata from the userspace fb creation request
+ * @file: DRM file that holds the GEM handle(s) backing the framebuffer
+ * @mode_cmd: Metadata from the userspace framebuffer creation request
+ *
+ * This function creates a new framebuffer object described by
+ * &drm_mode_fb_cmd2. This description includes handles for the buffer(s)
+ * backing the framebuffer.
  *
  * If your hardware has special alignment or pitch requirements these should be
  * checked before calling this function. The function does buffer size
  * validation. Use drm_gem_fb_create_with_funcs() if you need to set
  * &drm_framebuffer_funcs.dirty.
+ *
+ * Drivers can use this as their &drm_mode_config_funcs.fb_create callback.
+ * The ADDFB2 IOCTL calls into this callback.
+ *
+ * Returns:
+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
  */
 struct drm_framebuffer *
 drm_gem_fb_create(struct drm_device *dev, struct drm_file *file,
@@ -212,15 +232,15 @@ drm_gem_fb_create(struct drm_device *dev, struct drm_file *file,
 EXPORT_SYMBOL_GPL(drm_gem_fb_create);
 
 /**
- * drm_gem_fb_prepare_fb() - Prepare gem framebuffer
- * @plane: Which plane
- * @state: Plane state attach fence to
+ * drm_gem_fb_prepare_fb() - Prepare a GEM backed framebuffer
+ * @plane: Plane
+ * @state: Plane state the fence will be attached to
  *
- * This can be used as the &drm_plane_helper_funcs.prepare_fb hook.
- *
- * This function checks if the plane FB has an dma-buf attached, extracts
- * the exclusive fence and attaches it to plane state for the atomic helper
- * to wait on.
+ * This function prepares a GEM backed framebuffer for scanout by checking if
+ * the plane framebuffer has a DMA-BUF attached. If it does, it extracts the
+ * exclusive fence and attaches it to the plane state for the atomic helper to
+ * wait on. This function can be used as the &drm_plane_helper_funcs.prepare_fb
+ * callback.
  *
  * There is no need for &drm_plane_helper_funcs.cleanup_fb hook for simple
  * gem based framebuffer drivers which have their buffers always pinned in
@@ -246,17 +266,19 @@ int drm_gem_fb_prepare_fb(struct drm_plane *plane,
 EXPORT_SYMBOL_GPL(drm_gem_fb_prepare_fb);
 
 /**
- * drm_gem_fbdev_fb_create - Create a drm_framebuffer for fbdev emulation
+ * drm_gem_fbdev_fb_create - Create a GEM backed &drm_framebuffer for fbdev
+ *                           emulation
  * @dev: DRM device
  * @sizes: fbdev size description
- * @pitch_align: optional pitch alignment
+ * @pitch_align: Optional pitch alignment
  * @obj: GEM object backing the framebuffer
  * @funcs: vtable to be used for the new framebuffer object
  *
- * This function creates a framebuffer for use with fbdev emulation.
+ * This function creates a framebuffer from a &drm_fb_helper_surface_size
+ * description for use in the &drm_fb_helper_funcs.fb_probe callback.
  *
  * Returns:
- * Pointer to a drm_framebuffer on success or an error pointer on failure.
+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
  */
 struct drm_framebuffer *
 drm_gem_fbdev_fb_create(struct drm_device *dev,
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index fbc3f308fa19..edd921adcf33 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -55,7 +55,6 @@ int drm_clients_info(struct seq_file *m, void* data);
 int drm_gem_name_info(struct seq_file *m, void *data);
 
 /* drm_vblank.c */
-extern unsigned int drm_timestamp_monotonic;
 void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe);
 void drm_vblank_cleanup(struct drm_device *dev);
 
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index a9ae6dd2d593..a78f03155466 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -235,7 +235,7 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
         /* Only some caps make sense with UMS/render-only drivers. */
         switch (req->capability) {
         case DRM_CAP_TIMESTAMP_MONOTONIC:
-                req->value = drm_timestamp_monotonic;
+                req->value = 1;
                 return 0;
         case DRM_CAP_PRIME:
                 req->value |= dev->driver->prime_fd_to_handle ? DRM_PRIME_CAP_IMPORT : 0;
diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c
index 7a1ea91d3343..240a05d91a53 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -105,6 +105,7 @@ void drm_mode_object_unregister(struct drm_device *dev,
 }
 
 struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
+                                               struct drm_file *file_priv,
                                                uint32_t id, uint32_t type)
 {
         struct drm_mode_object *obj = NULL;
@@ -127,7 +128,7 @@ struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
 
 /**
  * drm_mode_object_find - look up a drm object with static lifetime
- * @dev: drm device
+ * @file_priv: drm file
  * @id: id of the mode object
  * @type: type of the mode object
  *
@@ -136,11 +137,12 @@ struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
  * by callind drm_mode_object_put().
  */
 struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
+                struct drm_file *file_priv,
                 uint32_t id, uint32_t type)
 {
         struct drm_mode_object *obj = NULL;
 
-        obj = __drm_mode_object_find(dev, id, type);
+        obj = __drm_mode_object_find(dev, file_priv, id, type);
         return obj;
 }
 EXPORT_SYMBOL(drm_mode_object_find);
@@ -359,7 +361,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data,
 
         drm_modeset_lock_all(dev);
 
-        obj = drm_mode_object_find(dev, arg->obj_id, arg->obj_type);
+        obj = drm_mode_object_find(dev, file_priv, arg->obj_id, arg->obj_type);
         if (!obj) {
                 ret = -ENOENT;
                 goto out;
@@ -481,7 +483,7 @@ int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        arg_obj = drm_mode_object_find(dev, arg->obj_id, arg->obj_type);
+        arg_obj = drm_mode_object_find(dev, file_priv, arg->obj_id, arg->obj_type);
         if (!arg_obj)
                 return -ENOENT;
 
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 72cba9805edc..6af02c7b5da3 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -513,7 +513,7 @@ int drm_mode_getplane(struct drm_device *dev, void *data,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        plane = drm_plane_find(dev, plane_resp->plane_id);
+        plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);
         if (!plane)
                 return -ENOENT;
 
@@ -703,7 +703,7 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
          * First, find the plane, crtc, and fb objects.  If not available,
          * we don't bother to call the driver.
          */
-        plane = drm_plane_find(dev, plane_req->plane_id);
+        plane = drm_plane_find(dev, file_priv, plane_req->plane_id);
         if (!plane) {
                 DRM_DEBUG_KMS("Unknown plane ID %d\n",
                               plane_req->plane_id);
@@ -711,14 +711,14 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
         }
 
         if (plane_req->fb_id) {
-                fb = drm_framebuffer_lookup(dev, plane_req->fb_id);
+                fb = drm_framebuffer_lookup(dev, file_priv, plane_req->fb_id);
                 if (!fb) {
                         DRM_DEBUG_KMS("Unknown framebuffer ID %d\n",
                                       plane_req->fb_id);
                         return -ENOENT;
                 }
 
-                crtc = drm_crtc_find(dev, plane_req->crtc_id);
+                crtc = drm_crtc_find(dev, file_priv, plane_req->crtc_id);
                 if (!crtc) {
                         drm_framebuffer_put(fb);
                         DRM_DEBUG_KMS("Unknown crtc ID %d\n",
@@ -829,7 +829,7 @@ static int drm_mode_cursor_common(struct drm_device *dev,
         if (!req->flags || (~DRM_MODE_CURSOR_FLAGS & req->flags))
                 return -EINVAL;
 
-        crtc = drm_crtc_find(dev, req->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, req->crtc_id);
         if (!crtc) {
                 DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id);
                 return -ENOENT;
@@ -944,7 +944,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
         if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
                 return -EINVAL;
 
-        crtc = drm_crtc_find(dev, page_flip->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, page_flip->crtc_id);
         if (!crtc)
                 return -ENOENT;
 
@@ -1005,7 +1005,7 @@ retry:
                 goto out;
         }
 
-        fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
+        fb = drm_framebuffer_lookup(dev, file_priv, page_flip->fb_id);
         if (!fb) {
                 ret = -ENOENT;
                 goto out;
diff --git a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
index 06aee1741e96..759ed93f4ba8 100644
--- a/drivers/gpu/drm/drm_plane_helper.c
+++ b/drivers/gpu/drm/drm_plane_helper.c
@@ -354,7 +354,7 @@ int drm_primary_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
         /* Find current connectors for CRTC */
         num_connectors = get_connectors_for_crtc(crtc, NULL, 0);
         BUG_ON(num_connectors == 0);
-        connector_list = kzalloc(num_connectors * sizeof(*connector_list),
+        connector_list = kcalloc(num_connectors, sizeof(*connector_list),
                                  GFP_KERNEL);
         if (!connector_list)
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index 5840aabbf24e..6dc2dde5b672 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -99,7 +99,7 @@ drm_mode_validate_pipeline(struct drm_display_mode *mode,
 
         /* Step 2: Validate against encoders and crtcs */
         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
-                struct drm_encoder *encoder = drm_encoder_find(dev, ids[i]);
+                struct drm_encoder *encoder = drm_encoder_find(dev, NULL, ids[i]);
                 struct drm_crtc *crtc;
 
                 if (!encoder)
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
index bc5128203056..bae50e6b819d 100644
--- a/drivers/gpu/drm/drm_property.c
+++ b/drivers/gpu/drm/drm_property.c
@@ -450,7 +450,7 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev,
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 return -EINVAL;
 
-        property = drm_property_find(dev, out_resp->prop_id);
+        property = drm_property_find(dev, file_priv, out_resp->prop_id);
         if (!property)
                 return -ENOENT;
 
@@ -634,7 +634,7 @@ struct drm_property_blob *drm_property_lookup_blob(struct drm_device *dev,
         struct drm_mode_object *obj;
         struct drm_property_blob *blob = NULL;
 
-        obj = __drm_mode_object_find(dev, id, DRM_MODE_OBJECT_BLOB);
+        obj = __drm_mode_object_find(dev, NULL, id, DRM_MODE_OBJECT_BLOB);
         if (obj)
                 blob = obj_to_blob(obj);
         return blob;
@@ -897,7 +897,7 @@ bool drm_property_change_valid_get(struct drm_property *property,
                 if (value == 0)
                         return true;
 
-                *ref = __drm_mode_object_find(property->dev, value,
+                *ref = __drm_mode_object_find(property->dev, NULL, value,
                                               property->values[0]);
                 return *ref != NULL;
         }
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 80b6151da9ae..f776fc1cc543 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -845,7 +845,8 @@ static int drm_syncobj_array_wait(struct drm_device *dev,
 }
 
 static int drm_syncobj_array_find(struct drm_file *file_private,
-                                  void *user_handles, uint32_t count_handles,
+                                  void __user *user_handles,
+                                  uint32_t count_handles,
                                   struct drm_syncobj ***syncobjs_out)
 {
         uint32_t i, *handles;
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 70f2b9593edc..3af6c20ba03b 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -78,28 +78,20 @@
 
 static bool
 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
-                          struct timeval *tvblank, bool in_vblank_irq);
+                          ktime_t *tvblank, bool in_vblank_irq);
 
 static unsigned int drm_timestamp_precision = 20;  /* Default to 20 usecs. */
 
-/*
- * Default to use monotonic timestamps for wait-for-vblank and page-flip
- * complete events.
- */
-unsigned int drm_timestamp_monotonic = 1;
-
 static int drm_vblank_offdelay = 5000;    /* Default to 5000 msecs. */
 
 module_param_named(vblankoffdelay, drm_vblank_offdelay, int, 0600);
 module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600);
-module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
 MODULE_PARM_DESC(vblankoffdelay, "Delay until vblank irq auto-disable [msecs] (0: never disable, <0: disable immediately)");
 MODULE_PARM_DESC(timestamp_precision_usec, "Max. error on timestamps [usecs]");
-MODULE_PARM_DESC(timestamp_monotonic, "Use monotonic timestamps");
 
 static void store_vblank(struct drm_device *dev, unsigned int pipe,
                          u32 vblank_count_inc,
-                         struct timeval *t_vblank, u32 last)
+                         ktime_t t_vblank, u32 last)
 {
         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
 
@@ -108,7 +100,7 @@ static void store_vblank(struct drm_device *dev, unsigned int pipe,
         vblank->last = last;
 
         write_seqlock(&vblank->seqlock);
-        vblank->time = *t_vblank;
+        vblank->time = t_vblank;
         vblank->count += vblank_count_inc;
         write_sequnlock(&vblank->seqlock);
 }
@@ -151,7 +143,7 @@ static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe
 {
         u32 cur_vblank;
         bool rc;
-        struct timeval t_vblank;
+        ktime_t t_vblank;
         int count = DRM_TIMESTAMP_MAXRETRIES;
 
         spin_lock(&dev->vblank_time_lock);
@@ -171,13 +163,13 @@ static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe
          * interrupt and assign 0 for now, to mark the vblanktimestamp as invalid.
          */
         if (!rc)
-                t_vblank = (struct timeval) {0, 0};
+                t_vblank = 0;
 
         /*
          * +1 to make sure user will never see the same
          * vblank counter value before and after a modeset
          */
-        store_vblank(dev, pipe, 1, &t_vblank, cur_vblank);
+        store_vblank(dev, pipe, 1, t_vblank, cur_vblank);
 
         spin_unlock(&dev->vblank_time_lock);
 }
@@ -200,7 +192,7 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,
         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
         u32 cur_vblank, diff;
         bool rc;
-        struct timeval t_vblank;
+        ktime_t t_vblank;
         int count = DRM_TIMESTAMP_MAXRETRIES;
         int framedur_ns = vblank->framedur_ns;
 
@@ -225,11 +217,7 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,
                 /* trust the hw counter when it's around */
                 diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
         } else if (rc && framedur_ns) {
-                const struct timeval *t_old;
-                u64 diff_ns;
-
-                t_old = &vblank->time;
-                diff_ns = timeval_to_ns(&t_vblank) - timeval_to_ns(t_old);
+                u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
 
                 /*
                  * Figure out how many vblanks we've missed based
@@ -278,9 +266,9 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,
          * for now, to mark the vblanktimestamp as invalid.
          */
         if (!rc && !in_vblank_irq)
-                t_vblank = (struct timeval) {0, 0};
+                t_vblank = 0;
 
-        store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
+        store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
 }
 
 static u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
@@ -556,7 +544,7 @@ EXPORT_SYMBOL(drm_calc_timestamping_constants);
  * @pipe: index of CRTC whose vblank timestamp to retrieve
  * @max_error: Desired maximum allowable error in timestamps (nanosecs)
  *             On return contains true maximum error of timestamp
- * @vblank_time: Pointer to struct timeval which should receive the timestamp
+ * @vblank_time: Pointer to time which should receive the timestamp
  * @in_vblank_irq:
  *     True when called from drm_crtc_handle_vblank().  Some drivers
  *     need to apply some workarounds for gpu-specific vblank irq quirks
@@ -584,10 +572,10 @@ EXPORT_SYMBOL(drm_calc_timestamping_constants);
 bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
                                            unsigned int pipe,
                                            int *max_error,
-                                           struct timeval *vblank_time,
+                                           ktime_t *vblank_time,
                                            bool in_vblank_irq)
 {
-        struct timeval tv_etime;
+        struct timespec64 ts_etime, ts_vblank_time;
         ktime_t stime, etime;
         bool vbl_status;
         struct drm_crtc *crtc;
@@ -676,41 +664,31 @@ bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
         delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos),
                            mode->crtc_clock);
 
-        if (!drm_timestamp_monotonic)
-                etime = ktime_mono_to_real(etime);
-
         /* save this only for debugging purposes */
-        tv_etime = ktime_to_timeval(etime);
+        ts_etime = ktime_to_timespec64(etime);
+        ts_vblank_time = ktime_to_timespec64(*vblank_time);
         /* Subtract time delta from raw timestamp to get final
          * vblank_time timestamp for end of vblank.
          */
         etime = ktime_sub_ns(etime, delta_ns);
-        *vblank_time = ktime_to_timeval(etime);
+        *vblank_time = etime;
 
-        DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n",
+        DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %lld.%06ld -> %lld.%06ld [e %d us, %d rep]\n",
                       pipe, hpos, vpos,
-                      (long)tv_etime.tv_sec, (long)tv_etime.tv_usec,
-                      (long)vblank_time->tv_sec, (long)vblank_time->tv_usec,
-                      duration_ns/1000, i);
+                      (u64)ts_etime.tv_sec, ts_etime.tv_nsec / 1000,
+                      (u64)ts_vblank_time.tv_sec, ts_vblank_time.tv_nsec / 1000,
+                      duration_ns / 1000, i);
 
         return true;
 }
 EXPORT_SYMBOL(drm_calc_vbltimestamp_from_scanoutpos);
 
-static struct timeval get_drm_timestamp(void)
-{
-        ktime_t now;
-
-        now = drm_timestamp_monotonic ? ktime_get() : ktime_get_real();
-        return ktime_to_timeval(now);
-}
-
 /**
  * drm_get_last_vbltimestamp - retrieve raw timestamp for the most recent
  *                             vblank interval
  * @dev: DRM device
  * @pipe: index of CRTC whose vblank timestamp to retrieve
- * @tvblank: Pointer to target struct timeval which should receive the timestamp
+ * @tvblank: Pointer to target time which should receive the timestamp
  * @in_vblank_irq:
  *     True when called from drm_crtc_handle_vblank().  Some drivers
  *     need to apply some workarounds for gpu-specific vblank irq quirks
@@ -728,7 +706,7 @@ static struct timeval get_drm_timestamp(void)
  */
 static bool
 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
-                          struct timeval *tvblank, bool in_vblank_irq)
+                          ktime_t *tvblank, bool in_vblank_irq)
 {
         bool ret = false;
 
@@ -744,7 +722,7 @@ drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
          * Return current monotonic/gettimeofday timestamp as best estimate.
          */
         if (!ret)
-                *tvblank = get_drm_timestamp();
+                *tvblank = ktime_get();
 
         return ret;
 }
@@ -769,14 +747,14 @@ u32 drm_crtc_vblank_count(struct drm_crtc *crtc)
 EXPORT_SYMBOL(drm_crtc_vblank_count);
 
 static u32 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,
-                                     struct timeval *vblanktime)
+                                     ktime_t *vblanktime)
 {
         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
         u32 vblank_count;
         unsigned int seq;
 
         if (WARN_ON(pipe >= dev->num_crtcs)) {
-                *vblanktime = (struct timeval) { 0 };
+                *vblanktime = 0;
                 return 0;
         }
 
@@ -793,7 +771,7 @@ static u32 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,
  * drm_crtc_vblank_count_and_time - retrieve "cooked" vblank counter value
  *     and the system timestamp corresponding to that vblank counter value
  * @crtc: which counter to retrieve
- * @vblanktime: Pointer to struct timeval to receive the vblank timestamp.
+ * @vblanktime: Pointer to time to receive the vblank timestamp.
  *
  * Fetches the "cooked" vblank count value that represents the number of
  * vblank events since the system was booted, including lost events due to
@@ -801,7 +779,7 @@ static u32 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,
  * of the vblank interval that corresponds to the current vblank counter value.
  */
 u32 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
-                                   struct timeval *vblanktime)
+                                   ktime_t *vblanktime)
 {
         return drm_vblank_count_and_time(crtc->dev, drm_crtc_index(crtc),
                                          vblanktime);
@@ -810,11 +788,18 @@ EXPORT_SYMBOL(drm_crtc_vblank_count_and_time);
 
 static void send_vblank_event(struct drm_device *dev,
                 struct drm_pending_vblank_event *e,
-                unsigned long seq, struct timeval *now)
+                unsigned long seq, ktime_t now)
 {
+        struct timespec64 tv = ktime_to_timespec64(now);
+
         e->event.sequence = seq;
-        e->event.tv_sec = now->tv_sec;
-        e->event.tv_usec = now->tv_usec;
+        /*
+         * e->event is a user space structure, with hardcoded unsigned
+         * 32-bit seconds/microseconds. This is safe as we always use
+         * monotonic timestamps since linux-4.15
+         */
+        e->event.tv_sec = tv.tv_sec;
+        e->event.tv_usec = tv.tv_nsec / 1000;
 
         trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe,
                                          e->event.sequence);
@@ -869,7 +854,7 @@ void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
         assert_spin_locked(&dev->event_lock);
 
         e->pipe = pipe;
-        e->event.sequence = drm_vblank_count(dev, pipe);
+        e->event.sequence = drm_crtc_accurate_vblank_count(crtc) + 1;
         e->event.crtc_id = crtc->base.id;
         list_add_tail(&e->base.link, &dev->vblank_event_list);
 }
@@ -891,18 +876,18 @@ void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
 {
         struct drm_device *dev = crtc->dev;
         unsigned int seq, pipe = drm_crtc_index(crtc);
-        struct timeval now;
+        ktime_t now;
 
         if (dev->num_crtcs > 0) {
                 seq = drm_vblank_count_and_time(dev, pipe, &now);
         } else {
                 seq = 0;
 
-                now = get_drm_timestamp();
+                now = ktime_get();
         }
         e->pipe = pipe;
         e->event.crtc_id = crtc->base.id;
-        send_vblank_event(dev, e, seq, &now);
+        send_vblank_event(dev, e, seq, now);
 }
 EXPORT_SYMBOL(drm_crtc_send_vblank_event);
 
@@ -1100,7 +1085,8 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc)
         unsigned int pipe = drm_crtc_index(crtc);
         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
         struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
+
+        ktime_t now;
         unsigned long irqflags;
         unsigned int seq;
 
@@ -1141,7 +1127,7 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc)
                           e->event.sequence, seq);
                 list_del(&e->base.link);
                 drm_vblank_put(dev, pipe);
-                send_vblank_event(dev, e, seq, &now);
+                send_vblank_event(dev, e, seq, now);
         }
         spin_unlock_irqrestore(&dev->event_lock, irqflags);
 
@@ -1321,7 +1307,7 @@ static int drm_queue_vblank_event(struct drm_device *dev, unsigned int pipe,
 {
         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
         struct drm_pending_vblank_event *e;
-        struct timeval now;
+        ktime_t now;
         unsigned long flags;
         unsigned int seq;
         int ret;
@@ -1367,7 +1353,7 @@ static int drm_queue_vblank_event(struct drm_device *dev, unsigned int pipe,
         e->event.sequence = vblwait->request.sequence;
         if (vblank_passed(seq, vblwait->request.sequence)) {
                 drm_vblank_put(dev, pipe);
-                send_vblank_event(dev, e, seq, &now);
+                send_vblank_event(dev, e, seq, now);
                 vblwait->reply.sequence = seq;
         } else {
                 /* drm_handle_vblank_events will call drm_vblank_put */
@@ -1398,6 +1384,23 @@ static bool drm_wait_vblank_is_query(union drm_wait_vblank *vblwait)
                                           _DRM_VBLANK_NEXTONMISS));
 }
 
+static void drm_wait_vblank_reply(struct drm_device *dev, unsigned int pipe,
+                                  struct drm_wait_vblank_reply *reply)
+{
+        ktime_t now;
+        struct timespec64 ts;
+
+        /*
+         * drm_wait_vblank_reply is a UAPI structure that uses 'long'
+         * to store the seconds. This is safe as we always use monotonic
+         * timestamps since linux-4.15.
+         */
+        reply->sequence = drm_vblank_count_and_time(dev, pipe, &now);
+        ts = ktime_to_timespec64(now);
+        reply->tval_sec = (u32)ts.tv_sec;
+        reply->tval_usec = ts.tv_nsec / 1000;
+}
+
 int drm_wait_vblank_ioctl(struct drm_device *dev, void *data,
                           struct drm_file *file_priv)
 {
@@ -1439,12 +1442,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void *data,
         if (dev->vblank_disable_immediate &&
             drm_wait_vblank_is_query(vblwait) &&
             READ_ONCE(vblank->enabled)) {
-                struct timeval now;
-
-                vblwait->reply.sequence =
-                        drm_vblank_count_and_time(dev, pipe, &now);
-                vblwait->reply.tval_sec = now.tv_sec;
-                vblwait->reply.tval_usec = now.tv_usec;
+                drm_wait_vblank_reply(dev, pipe, &vblwait->reply);
                 return 0;
         }
 
@@ -1487,11 +1485,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void *data,
         }
 
         if (ret != -EINTR) {
-                struct timeval now;
-
-                vblwait->reply.sequence = drm_vblank_count_and_time(dev, pipe, &now);
-                vblwait->reply.tval_sec = now.tv_sec;
-                vblwait->reply.tval_usec = now.tv_usec;
+                drm_wait_vblank_reply(dev, pipe, &vblwait->reply);
 
                 DRM_DEBUG("crtc %d returning %u to client\n",
                           pipe, vblwait->reply.sequence);
@@ -1507,7 +1501,7 @@ done:
 static void drm_handle_vblank_events(struct drm_device *dev, unsigned int pipe)
 {
         struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
+        ktime_t now;
         unsigned int seq;
 
         assert_spin_locked(&dev->event_lock);
@@ -1525,7 +1519,7 @@ static void drm_handle_vblank_events(struct drm_device *dev, unsigned int pipe)
 
                 list_del(&e->base.link);
                 drm_vblank_put(dev, pipe);
-                send_vblank_event(dev, e, seq, &now);
+                send_vblank_event(dev, e, seq, now);
         }
 
         trace_drm_vblank_event(pipe, seq);
diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig
index 38b477b5fbf9..a29b8f59eb15 100644
--- a/drivers/gpu/drm/etnaviv/Kconfig
+++ b/drivers/gpu/drm/etnaviv/Kconfig
@@ -7,8 +7,6 @@ config DRM_ETNAVIV
         select SHMEM
         select SYNC_FILE
         select TMPFS
-        select IOMMU_API
-        select IOMMU_SUPPORT
         select WANT_DEV_COREDUMP
         select CMA if HAVE_DMA_CONTIGUOUS
         select DMA_CMA if HAVE_DMA_CONTIGUOUS
diff --git a/drivers/gpu/drm/etnaviv/Makefile b/drivers/gpu/drm/etnaviv/Makefile
index 4f76c992043f..15c3bfa89a79 100644
--- a/drivers/gpu/drm/etnaviv/Makefile
+++ b/drivers/gpu/drm/etnaviv/Makefile
@@ -10,6 +10,7 @@ etnaviv-y := \
         etnaviv_gpu.o \
         etnaviv_iommu_v2.o \
         etnaviv_iommu.o \
-        etnaviv_mmu.o
+        etnaviv_mmu.o \
+        etnaviv_perfmon.o
 
 obj-$(CONFIG_DRM_ETNAVIV)       += etnaviv.o
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
index ed9588f36bc9..9e7098e3207f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -250,6 +250,42 @@ void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
         }
 }
 
+/* Append a 'sync point' to the ring buffer. */
+void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
+{
+        struct etnaviv_cmdbuf *buffer = gpu->buffer;
+        unsigned int waitlink_offset = buffer->user_size - 16;
+        u32 dwords, target;
+
+        /*
+         * We need at most 3 dwords in the return target:
+         * 1 event + 1 end + 1 wait + 1 link.
+         */
+        dwords = 4;
+        target = etnaviv_buffer_reserve(gpu, buffer, dwords);
+
+        /* Signal sync point event */
+        CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
+                       VIVS_GL_EVENT_FROM_PE);
+
+        /* Stop the FE to 'pause' the GPU */
+        CMD_END(buffer);
+
+        /* Append waitlink */
+        CMD_WAIT(buffer);
+        CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +
+                            buffer->user_size - 4);
+
+        /*
+         * Kick off the 'sync point' command by replacing the previous
+         * WAIT with a link to the address in the ring buffer.
+         */
+        etnaviv_buffer_replace_wait(buffer, waitlink_offset,
+                                    VIV_FE_LINK_HEADER_OP_LINK |
+                                    VIV_FE_LINK_HEADER_PREFETCH(dwords),
+                                    target);
+}
+
 /* Append a command buffer to the ring buffer. */
 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
         struct etnaviv_cmdbuf *cmdbuf)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c b/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c
index 633e0f07cbac..66ac79558bbd 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c
@@ -19,6 +19,7 @@
 #include "etnaviv_cmdbuf.h"
 #include "etnaviv_gpu.h"
 #include "etnaviv_mmu.h"
+#include "etnaviv_perfmon.h"
 
 #define SUBALLOC_SIZE           SZ_256K
 #define SUBALLOC_GRANULE        SZ_4K
@@ -87,9 +88,10 @@ void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc)
 
 struct etnaviv_cmdbuf *
 etnaviv_cmdbuf_new(struct etnaviv_cmdbuf_suballoc *suballoc, u32 size,
-                   size_t nr_bos)
+                   size_t nr_bos, size_t nr_pmrs)
 {
         struct etnaviv_cmdbuf *cmdbuf;
+        struct etnaviv_perfmon_request *pmrs;
         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]),
                                  sizeof(*cmdbuf));
         int granule_offs, order, ret;
@@ -98,6 +100,12 @@ etnaviv_cmdbuf_new(struct etnaviv_cmdbuf_suballoc *suballoc, u32 size,
         if (!cmdbuf)
                 return NULL;
 
+        sz = sizeof(*pmrs) * nr_pmrs;
+        pmrs = kzalloc(sz, GFP_KERNEL);
+        if (!pmrs)
+                goto out_free_cmdbuf;
+
+        cmdbuf->pmrs = pmrs;
         cmdbuf->suballoc = suballoc;
         cmdbuf->size = size;
 
@@ -124,6 +132,10 @@ retry:
         cmdbuf->vaddr = suballoc->vaddr + cmdbuf->suballoc_offset;
 
         return cmdbuf;
+
+out_free_cmdbuf:
+        kfree(cmdbuf);
+        return NULL;
 }
 
 void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
@@ -139,6 +151,7 @@ void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
         suballoc->free_space = 1;
         mutex_unlock(&suballoc->lock);
         wake_up_all(&suballoc->free_event);
+        kfree(cmdbuf->pmrs);
         kfree(cmdbuf);
 }
 
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h b/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h
index 80d78076c679..b6348b9f2a9d 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h
@@ -21,6 +21,7 @@
 
 struct etnaviv_gpu;
 struct etnaviv_cmdbuf_suballoc;
+struct etnaviv_perfmon_request;
 
 struct etnaviv_cmdbuf {
         /* suballocator this cmdbuf is allocated from */
@@ -38,6 +39,9 @@ struct etnaviv_cmdbuf {
         u32 exec_state;
         /* per GPU in-flight list */
         struct list_head node;
+        /* perfmon requests */
+        unsigned int nr_pmrs;
+        struct etnaviv_perfmon_request *pmrs;
         /* BOs attached to this command buffer */
         unsigned int nr_bos;
         struct etnaviv_vram_mapping *bo_map[0];
@@ -49,7 +53,7 @@ void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc);
 
 struct etnaviv_cmdbuf *
 etnaviv_cmdbuf_new(struct etnaviv_cmdbuf_suballoc *suballoc, u32 size,
-                   size_t nr_bos);
+                   size_t nr_bos, size_t nr_pmrs);
 void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);
 
 u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 2cb4773823c2..3fadb8d45e51 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -23,6 +23,7 @@
 #include "etnaviv_gpu.h"
 #include "etnaviv_gem.h"
 #include "etnaviv_mmu.h"
+#include "etnaviv_perfmon.h"
 
 #ifdef CONFIG_DRM_ETNAVIV_REGISTER_LOGGING
 static bool reglog;
@@ -451,6 +452,40 @@ static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data,
         return ret;
 }
 
+static int etnaviv_ioctl_pm_query_dom(struct drm_device *dev, void *data,
+        struct drm_file *file)
+{
+        struct etnaviv_drm_private *priv = dev->dev_private;
+        struct drm_etnaviv_pm_domain *args = data;
+        struct etnaviv_gpu *gpu;
+
+        if (args->pipe >= ETNA_MAX_PIPES)
+                return -EINVAL;
+
+        gpu = priv->gpu[args->pipe];
+        if (!gpu)
+                return -ENXIO;
+
+        return etnaviv_pm_query_dom(gpu, args);
+}
+
+static int etnaviv_ioctl_pm_query_sig(struct drm_device *dev, void *data,
+        struct drm_file *file)
+{
+        struct etnaviv_drm_private *priv = dev->dev_private;
+        struct drm_etnaviv_pm_signal *args = data;
+        struct etnaviv_gpu *gpu;
+
+        if (args->pipe >= ETNA_MAX_PIPES)
+                return -EINVAL;
+
+        gpu = priv->gpu[args->pipe];
+        if (!gpu)
+                return -ENXIO;
+
+        return etnaviv_pm_query_sig(gpu, args);
+}
+
 static const struct drm_ioctl_desc etnaviv_ioctls[] = {
 #define ETNA_IOCTL(n, func, flags) \
         DRM_IOCTL_DEF_DRV(ETNAVIV_##n, etnaviv_ioctl_##func, flags)
@@ -463,6 +498,8 @@ static const struct drm_ioctl_desc etnaviv_ioctls[] = {
         ETNA_IOCTL(WAIT_FENCE,   wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
         ETNA_IOCTL(GEM_USERPTR,  gem_userptr,  DRM_AUTH|DRM_RENDER_ALLOW),
         ETNA_IOCTL(GEM_WAIT,     gem_wait,     DRM_AUTH|DRM_RENDER_ALLOW),
+        ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_AUTH|DRM_RENDER_ALLOW),
+        ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 
 static const struct vm_operations_struct vm_ops = {
@@ -513,7 +550,7 @@ static struct drm_driver etnaviv_drm_driver = {
         .desc               = "etnaviv DRM",
         .date               = "20151214",
         .major              = 1,
-        .minor              = 1,
+        .minor              = 2,
 };
 
 /*
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index 058389f93b69..d249acb6da08 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -26,7 +26,6 @@
 #include <linux/pm_runtime.h>
 #include <linux/slab.h>
 #include <linux/list.h>
-#include <linux/iommu.h>
 #include <linux/types.h>
 #include <linux/sizes.h>
 
@@ -92,15 +91,12 @@ int etnaviv_gem_cpu_fini(struct drm_gem_object *obj);
 void etnaviv_gem_free_object(struct drm_gem_object *obj);
 int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file,
                 u32 size, u32 flags, u32 *handle);
-struct drm_gem_object *etnaviv_gem_new_locked(struct drm_device *dev,
-                u32 size, u32 flags);
-struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
-                u32 size, u32 flags);
 int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file,
         uintptr_t ptr, u32 size, u32 flags, u32 *handle);
 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
+void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
         struct etnaviv_cmdbuf *cmdbuf);
 void etnaviv_validate_init(void);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index 57881167ccd2..5884ab623e0a 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@ -704,25 +704,6 @@ int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file,
         return ret;
 }
 
-struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
-                u32 size, u32 flags)
-{
-        struct drm_gem_object *obj;
-        int ret;
-
-        obj = __etnaviv_gem_new(dev, size, flags);
-        if (IS_ERR(obj))
-                return obj;
-
-        ret = etnaviv_gem_obj_add(dev, obj);
-        if (ret < 0) {
-                drm_gem_object_put_unlocked(obj);
-                return ERR_PTR(ret);
-        }
-
-        return obj;
-}
-
 int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags,
         struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
         struct etnaviv_gem_object **res)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
index 46dfe0737f43..ff911541a190 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
@@ -21,6 +21,7 @@
 #include "etnaviv_drv.h"
 #include "etnaviv_gpu.h"
 #include "etnaviv_gem.h"
+#include "etnaviv_perfmon.h"
 
 /*
  * Cmdstream submission:
@@ -283,6 +284,54 @@ static int submit_reloc(struct etnaviv_gem_submit *submit, void *stream,
         return 0;
 }
 
+static int submit_perfmon_validate(struct etnaviv_gem_submit *submit,
+                struct etnaviv_cmdbuf *cmdbuf,
+                const struct drm_etnaviv_gem_submit_pmr *pmrs,
+                u32 nr_pms)
+{
+        u32 i;
+
+        for (i = 0; i < nr_pms; i++) {
+                const struct drm_etnaviv_gem_submit_pmr *r = pmrs + i;
+                struct etnaviv_gem_submit_bo *bo;
+                int ret;
+
+                ret = submit_bo(submit, r->read_idx, &bo);
+                if (ret)
+                        return ret;
+
+                /* at offset 0 a sequence number gets stored used for userspace sync */
+                if (r->read_offset == 0) {
+                        DRM_ERROR("perfmon request: offset is 0");
+                        return -EINVAL;
+                }
+
+                if (r->read_offset >= bo->obj->base.size - sizeof(u32)) {
+                        DRM_ERROR("perfmon request: offset %u outside object", i);
+                        return -EINVAL;
+                }
+
+                if (r->flags & ~(ETNA_PM_PROCESS_PRE | ETNA_PM_PROCESS_POST)) {
+                        DRM_ERROR("perfmon request: flags are not valid");
+                        return -EINVAL;
+                }
+
+                if (etnaviv_pm_req_validate(r, cmdbuf->exec_state)) {
+                        DRM_ERROR("perfmon request: domain or signal not valid");
+                        return -EINVAL;
+                }
+
+                cmdbuf->pmrs[i].flags = r->flags;
+                cmdbuf->pmrs[i].domain = r->domain;
+                cmdbuf->pmrs[i].signal = r->signal;
+                cmdbuf->pmrs[i].sequence = r->sequence;
+                cmdbuf->pmrs[i].offset = r->read_offset;
+                cmdbuf->pmrs[i].bo_vma = etnaviv_gem_vmap(&bo->obj->base);
+        }
+
+        return 0;
+}
+
 static void submit_cleanup(struct etnaviv_gem_submit *submit)
 {
         unsigned i;
@@ -306,6 +355,7 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
         struct etnaviv_drm_private *priv = dev->dev_private;
         struct drm_etnaviv_gem_submit *args = data;
         struct drm_etnaviv_gem_submit_reloc *relocs;
+        struct drm_etnaviv_gem_submit_pmr *pmrs;
         struct drm_etnaviv_gem_submit_bo *bos;
         struct etnaviv_gem_submit *submit;
         struct etnaviv_cmdbuf *cmdbuf;
@@ -347,11 +397,12 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
          */
         bos = kvmalloc_array(args->nr_bos, sizeof(*bos), GFP_KERNEL);
         relocs = kvmalloc_array(args->nr_relocs, sizeof(*relocs), GFP_KERNEL);
+        pmrs = kvmalloc_array(args->nr_pmrs, sizeof(*pmrs), GFP_KERNEL);
         stream = kvmalloc_array(1, args->stream_size, GFP_KERNEL);
         cmdbuf = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc,
                                     ALIGN(args->stream_size, 8) + 8,
-                                    args->nr_bos);
-        if (!bos || !relocs || !stream || !cmdbuf) {
+                                    args->nr_bos, args->nr_pmrs);
+        if (!bos || !relocs || !pmrs || !stream || !cmdbuf) {
                 ret = -ENOMEM;
                 goto err_submit_cmds;
         }
@@ -373,6 +424,14 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
                 goto err_submit_cmds;
         }
 
+        ret = copy_from_user(pmrs, u64_to_user_ptr(args->pmrs),
+                             args->nr_pmrs * sizeof(*pmrs));
+        if (ret) {
+                ret = -EFAULT;
+                goto err_submit_cmds;
+        }
+        cmdbuf->nr_pmrs = args->nr_pmrs;
+
         ret = copy_from_user(stream, u64_to_user_ptr(args->stream),
                              args->stream_size);
         if (ret) {
@@ -441,6 +500,10 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
         if (ret)
                 goto out;
 
+        ret = submit_perfmon_validate(submit, cmdbuf, pmrs, args->nr_pmrs);
+        if (ret)
+                goto out;
+
         memcpy(cmdbuf->vaddr, stream, args->stream_size);
         cmdbuf->user_size = ALIGN(args->stream_size, 8);
 
@@ -496,6 +559,8 @@ err_submit_cmds:
                 kvfree(bos);
         if (relocs)
                 kvfree(relocs);
+        if (pmrs)
+                kvfree(pmrs);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index fc9a6a83dfc7..8197e1d6ed11 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -25,6 +25,7 @@
 #include "etnaviv_gpu.h"
 #include "etnaviv_gem.h"
 #include "etnaviv_mmu.h"
+#include "etnaviv_perfmon.h"
 #include "common.xml.h"
 #include "state.xml.h"
 #include "state_hi.xml.h"
@@ -420,9 +421,10 @@ static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
                              gpu->base_rate_shader >> gpu->freq_scale);
         } else {
                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
-                u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
-                            VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+                u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 
+                clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
+                clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
                 etnaviv_gpu_load_clock(gpu, clock);
         }
 }
@@ -433,24 +435,14 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
         unsigned long timeout;
         bool failed = true;
 
-        /* TODO
-         *
-         * - clock gating
-         * - puls eater
-         * - what about VG?
-         */
-
         /* We hope that the GPU resets in under one second */
         timeout = jiffies + msecs_to_jiffies(1000);
 
         while (time_is_after_jiffies(timeout)) {
                 /* enable clock */
-                etnaviv_gpu_update_clock(gpu);
-
-                control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
-
-                /* Wait for stable clock.  Vivante's code waited for 1ms */
-                usleep_range(1000, 10000);
+                unsigned int fscale = 1 << (6 - gpu->freq_scale);
+                control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
+                etnaviv_gpu_load_clock(gpu, control);
 
                 /* isolate the GPU. */
                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
@@ -461,7 +453,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 
                 /* wait for reset. */
-                msleep(1);
+                usleep_range(10, 20);
 
                 /* reset soft reset bit. */
                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
@@ -490,6 +482,10 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
                         continue;
                 }
 
+                /* disable debug registers, as they are not normally needed */
+                control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+                gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
+
                 failed = false;
                 break;
         }
@@ -721,7 +717,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
         }
 
         /* Create buffer: */
-        gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0);
+        gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0, 0);
         if (!gpu->buffer) {
                 ret = -ENOMEM;
                 dev_err(gpu->dev, "could not create command buffer\n");
@@ -739,10 +735,9 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
         /* Setup event management */
         spin_lock_init(&gpu->event_spinlock);
         init_completion(&gpu->event_free);
-        for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-                gpu->event[i].used = false;
+        bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
+        for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
                 complete(&gpu->event_free);
-        }
 
         /* Now program the hardware */
         mutex_lock(&gpu->lock);
@@ -926,7 +921,7 @@ static void recover_worker(struct work_struct *work)
         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
                                                recover_work);
         unsigned long flags;
-        unsigned int i;
+        unsigned int i = 0;
 
         dev_err(gpu->dev, "hangcheck recover!\n");
 
@@ -945,14 +940,12 @@ static void recover_worker(struct work_struct *work)
 
         /* complete all events, the GPU won't do it after the reset */
         spin_lock_irqsave(&gpu->event_spinlock, flags);
-        for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-                if (!gpu->event[i].used)
-                        continue;
+        for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
                 dma_fence_signal(gpu->event[i].fence);
                 gpu->event[i].fence = NULL;
-                gpu->event[i].used = false;
                 complete(&gpu->event_free);
         }
+        bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
         gpu->completed_fence = gpu->active_fence;
 
@@ -1140,30 +1133,45 @@ int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
  * event management:
  */
 
-static unsigned int event_alloc(struct etnaviv_gpu *gpu)
+static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
+        unsigned int *events)
 {
-        unsigned long ret, flags;
-        unsigned int i, event = ~0U;
+        unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
+        unsigned i, acquired = 0;
 
-        ret = wait_for_completion_timeout(&gpu->event_free,
-                                          msecs_to_jiffies(10 * 10000));
-        if (!ret)
-                dev_err(gpu->dev, "wait_for_completion_timeout failed");
+        for (i = 0; i < nr_events; i++) {
+                unsigned long ret;
 
-        spin_lock_irqsave(&gpu->event_spinlock, flags);
+                ret = wait_for_completion_timeout(&gpu->event_free, timeout);
 
-        /* find first free event */
-        for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
-                if (gpu->event[i].used == false) {
-                        gpu->event[i].used = true;
-                        event = i;
-                        break;
+                if (!ret) {
+                        dev_err(gpu->dev, "wait_for_completion_timeout failed");
+                        goto out;
                 }
+
+                acquired++;
+                timeout = ret;
+        }
+
+        spin_lock_irqsave(&gpu->event_spinlock, flags);
+
+        for (i = 0; i < nr_events; i++) {
+                int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
+
+                events[i] = event;
+                memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
+                set_bit(event, gpu->event_bitmap);
         }
 
         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 
-        return event;
+        return 0;
+
+out:
+        for (i = 0; i < acquired; i++)
+                complete(&gpu->event_free);
+
+        return -EBUSY;
 }
 
 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
@@ -1172,12 +1180,12 @@ static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
 
         spin_lock_irqsave(&gpu->event_spinlock, flags);
 
-        if (gpu->event[event].used == false) {
+        if (!test_bit(event, gpu->event_bitmap)) {
                 dev_warn(gpu->dev, "event %u is already marked as free",
                          event);
                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
         } else {
-                gpu->event[event].used = false;
+                clear_bit(event, gpu->event_bitmap);
                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 
                 complete(&gpu->event_free);
@@ -1311,12 +1319,71 @@ void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
         pm_runtime_put_autosuspend(gpu->dev);
 }
 
+static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
+        struct etnaviv_event *event, unsigned int flags)
+{
+        const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
+        unsigned int i;
+
+        for (i = 0; i < cmdbuf->nr_pmrs; i++) {
+                const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
+
+                if (pmr->flags == flags)
+                        etnaviv_perfmon_process(gpu, pmr);
+        }
+}
+
+static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
+        struct etnaviv_event *event)
+{
+        u32 val;
+
+        /* disable clock gating */
+        val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
+        val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
+        gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
+
+        /* enable debug register */
+        val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+        val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+        gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+
+        sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
+}
+
+static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
+        struct etnaviv_event *event)
+{
+        const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
+        unsigned int i;
+        u32 val;
+
+        sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
+
+        for (i = 0; i < cmdbuf->nr_pmrs; i++) {
+                const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
+
+                *pmr->bo_vma = pmr->sequence;
+        }
+
+        /* disable debug register */
+        val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+        val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+        gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+
+        /* enable clock gating */
+        val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
+        val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
+        gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
+}
+
+
 /* add bo's to gpu's ring, and kick gpu: */
 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
 {
         struct dma_fence *fence;
-        unsigned int event, i;
+        unsigned int i, nr_events = 1, event[3];
         int ret;
 
         ret = etnaviv_gpu_pm_get_sync(gpu);
@@ -1332,10 +1399,19 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
          *
          */
 
-        event = event_alloc(gpu);
-        if (unlikely(event == ~0U)) {
-                DRM_ERROR("no free event\n");
-                ret = -EBUSY;
+        /*
+         * if there are performance monitor requests we need to have
+         * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
+         *   requests.
+         * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
+         *   and update the sequence number for userspace.
+         */
+        if (cmdbuf->nr_pmrs)
+                nr_events = 3;
+
+        ret = event_alloc(gpu, nr_events, event);
+        if (ret) {
+                DRM_ERROR("no free events\n");
                 goto out_pm_put;
         }
 
@@ -1343,12 +1419,14 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
 
         fence = etnaviv_gpu_fence_alloc(gpu);
         if (!fence) {
-                event_free(gpu, event);
+                for (i = 0; i < nr_events; i++)
+                        event_free(gpu, event[i]);
+
                 ret = -ENOMEM;
                 goto out_unlock;
         }
 
-        gpu->event[event].fence = fence;
+        gpu->event[event[0]].fence = fence;
         submit->fence = dma_fence_get(fence);
         gpu->active_fence = submit->fence->seqno;
 
@@ -1358,7 +1436,19 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
                 gpu->lastctx = cmdbuf->ctx;
         }
 
-        etnaviv_buffer_queue(gpu, event, cmdbuf);
+        if (cmdbuf->nr_pmrs) {
+                gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
+                gpu->event[event[1]].cmdbuf = cmdbuf;
+                etnaviv_sync_point_queue(gpu, event[1]);
+        }
+
+        etnaviv_buffer_queue(gpu, event[0], cmdbuf);
+
+        if (cmdbuf->nr_pmrs) {
+                gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
+                gpu->event[event[2]].cmdbuf = cmdbuf;
+                etnaviv_sync_point_queue(gpu, event[2]);
+        }
 
         cmdbuf->fence = fence;
         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
@@ -1394,6 +1484,24 @@ out_pm_put:
         return ret;
 }
 
+static void etnaviv_process_sync_point(struct etnaviv_gpu *gpu,
+        struct etnaviv_event *event)
+{
+        u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
+
+        event->sync_point(gpu, event);
+        etnaviv_gpu_start_fe(gpu, addr + 2, 2);
+}
+
+static void sync_point_worker(struct work_struct *work)
+{
+        struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
+                                               sync_point_work);
+
+        etnaviv_process_sync_point(gpu, &gpu->event[gpu->sync_point_event]);
+        event_free(gpu, gpu->sync_point_event);
+}
+
 /*
  * Init/Cleanup:
  */
@@ -1440,7 +1548,15 @@ static irqreturn_t irq_handler(int irq, void *data)
 
                         dev_dbg(gpu->dev, "event %u\n", event);
 
+                        if (gpu->event[event].sync_point) {
+                                gpu->sync_point_event = event;
+                                etnaviv_queue_work(gpu->drm, &gpu->sync_point_work);
+                        }
+
                         fence = gpu->event[event].fence;
+                        if (!fence)
+                                continue;
+
                         gpu->event[event].fence = NULL;
                         dma_fence_signal(fence);
 
@@ -1645,6 +1761,7 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master,
 
         INIT_LIST_HEAD(&gpu->active_cmd_list);
         INIT_WORK(&gpu->retire_work, retire_worker);
+        INIT_WORK(&gpu->sync_point_work, sync_point_worker);
         INIT_WORK(&gpu->recover_work, recover_worker);
         init_waitqueue_head(&gpu->fence_event);
 
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 689cb8f3680c..4f10f147297a 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -88,13 +88,17 @@ struct etnaviv_chip_identity {
 };
 
 struct etnaviv_event {
-        bool used;
         struct dma_fence *fence;
+        struct etnaviv_cmdbuf *cmdbuf;
+
+        void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
 };
 
 struct etnaviv_cmdbuf_suballoc;
 struct etnaviv_cmdbuf;
 
+#define ETNA_NR_EVENTS 30
+
 struct etnaviv_gpu {
         struct drm_device *drm;
         struct thermal_cooling_device *cooling;
@@ -112,7 +116,8 @@ struct etnaviv_gpu {
         u32 memory_base;
 
         /* event management: */
-        struct etnaviv_event event[30];
+        DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
+        struct etnaviv_event event[ETNA_NR_EVENTS];
         struct completion event_free;
         spinlock_t event_spinlock;
 
@@ -133,6 +138,10 @@ struct etnaviv_gpu {
         /* worker for handling active-list retiring: */
         struct work_struct retire_work;
 
+        /* worker for handling 'sync' points: */
+        struct work_struct sync_point_work;
+        int sync_point_event;
+
         void __iomem *mmio;
         int irq;
 
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
index 7a7c97f599d7..14e24ac6573f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/iommu.h>
 #include <linux/platform_device.h>
 #include <linux/sizes.h>
 #include <linux/slab.h>
@@ -31,174 +30,115 @@
 
 #define GPU_MEM_START   0x80000000
 
-struct etnaviv_iommu_domain_pgtable {
-        u32 *pgtable;
-        dma_addr_t paddr;
+struct etnaviv_iommuv1_domain {
+        struct etnaviv_iommu_domain base;
+        u32 *pgtable_cpu;
+        dma_addr_t pgtable_dma;
 };
 
-struct etnaviv_iommu_domain {
-        struct iommu_domain domain;
-        struct device *dev;
-        void *bad_page_cpu;
-        dma_addr_t bad_page_dma;
-        struct etnaviv_iommu_domain_pgtable pgtable;
-        spinlock_t map_lock;
-};
-
-static struct etnaviv_iommu_domain *to_etnaviv_domain(struct iommu_domain *domain)
-{
-        return container_of(domain, struct etnaviv_iommu_domain, domain);
-}
-
-static int pgtable_alloc(struct etnaviv_iommu_domain_pgtable *pgtable,
-                         size_t size)
-{
-        pgtable->pgtable = dma_alloc_coherent(NULL, size, &pgtable->paddr, GFP_KERNEL);
-        if (!pgtable->pgtable)
-                return -ENOMEM;
-
-        return 0;
-}
-
-static void pgtable_free(struct etnaviv_iommu_domain_pgtable *pgtable,
-                         size_t size)
+static struct etnaviv_iommuv1_domain *
+to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
 {
-        dma_free_coherent(NULL, size, pgtable->pgtable, pgtable->paddr);
-}
-
-static u32 pgtable_read(struct etnaviv_iommu_domain_pgtable *pgtable,
-                           unsigned long iova)
-{
-        /* calcuate index into page table */
-        unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
-        phys_addr_t paddr;
-
-        paddr = pgtable->pgtable[index];
-
-        return paddr;
+        return container_of(domain, struct etnaviv_iommuv1_domain, base);
 }
 
-static void pgtable_write(struct etnaviv_iommu_domain_pgtable *pgtable,
-                          unsigned long iova, phys_addr_t paddr)
-{
-        /* calcuate index into page table */
-        unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
-
-        pgtable->pgtable[index] = paddr;
-}
-
-static int __etnaviv_iommu_init(struct etnaviv_iommu_domain *etnaviv_domain)
+static int __etnaviv_iommu_init(struct etnaviv_iommuv1_domain *etnaviv_domain)
 {
         u32 *p;
-        int ret, i;
-
-        etnaviv_domain->bad_page_cpu = dma_alloc_coherent(etnaviv_domain->dev,
-                                                  SZ_4K,
-                                                  &etnaviv_domain->bad_page_dma,
-                                                  GFP_KERNEL);
-        if (!etnaviv_domain->bad_page_cpu)
+        int i;
+
+        etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
+                                                etnaviv_domain->base.dev,
+                                                SZ_4K,
+                                                &etnaviv_domain->base.bad_page_dma,
+                                                GFP_KERNEL);
+        if (!etnaviv_domain->base.bad_page_cpu)
                 return -ENOMEM;
 
-        p = etnaviv_domain->bad_page_cpu;
+        p = etnaviv_domain->base.bad_page_cpu;
         for (i = 0; i < SZ_4K / 4; i++)
                 *p++ = 0xdead55aa;
 
-        ret = pgtable_alloc(&etnaviv_domain->pgtable, PT_SIZE);
-        if (ret < 0) {
-                dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-                                  etnaviv_domain->bad_page_cpu,
-                                  etnaviv_domain->bad_page_dma);
-                return ret;
+        etnaviv_domain->pgtable_cpu =
+                        dma_alloc_coherent(etnaviv_domain->base.dev, PT_SIZE,
+                                           &etnaviv_domain->pgtable_dma,
+                                           GFP_KERNEL);
+        if (!etnaviv_domain->pgtable_cpu) {
+                dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                                  etnaviv_domain->base.bad_page_cpu,
+                                  etnaviv_domain->base.bad_page_dma);
+                return -ENOMEM;
         }
 
         for (i = 0; i < PT_ENTRIES; i++)
-                etnaviv_domain->pgtable.pgtable[i] =
-                        etnaviv_domain->bad_page_dma;
-
-        spin_lock_init(&etnaviv_domain->map_lock);
+                etnaviv_domain->pgtable_cpu[i] =
+                                etnaviv_domain->base.bad_page_dma;
 
         return 0;
 }
 
-static void etnaviv_domain_free(struct iommu_domain *domain)
+static void etnaviv_iommuv1_domain_free(struct etnaviv_iommu_domain *domain)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
+        struct etnaviv_iommuv1_domain *etnaviv_domain =
+                        to_etnaviv_domain(domain);
 
-        pgtable_free(&etnaviv_domain->pgtable, PT_SIZE);
+        dma_free_coherent(etnaviv_domain->base.dev, PT_SIZE,
+                          etnaviv_domain->pgtable_cpu,
+                          etnaviv_domain->pgtable_dma);
 
-        dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-                          etnaviv_domain->bad_page_cpu,
-                          etnaviv_domain->bad_page_dma);
+        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                          etnaviv_domain->base.bad_page_cpu,
+                          etnaviv_domain->base.bad_page_dma);
 
         kfree(etnaviv_domain);
 }
 
-static int etnaviv_iommuv1_map(struct iommu_domain *domain, unsigned long iova,
-           phys_addr_t paddr, size_t size, int prot)
+static int etnaviv_iommuv1_map(struct etnaviv_iommu_domain *domain,
+                               unsigned long iova, phys_addr_t paddr,
+                               size_t size, int prot)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
+        struct etnaviv_iommuv1_domain *etnaviv_domain = to_etnaviv_domain(domain);
+        unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
 
         if (size != SZ_4K)
                 return -EINVAL;
 
-        spin_lock(&etnaviv_domain->map_lock);
-        pgtable_write(&etnaviv_domain->pgtable, iova, paddr);
-        spin_unlock(&etnaviv_domain->map_lock);
+        etnaviv_domain->pgtable_cpu[index] = paddr;
 
         return 0;
 }
 
-static size_t etnaviv_iommuv1_unmap(struct iommu_domain *domain,
+static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_domain *domain,
         unsigned long iova, size_t size)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
+        struct etnaviv_iommuv1_domain *etnaviv_domain =
+                        to_etnaviv_domain(domain);
+        unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
 
         if (size != SZ_4K)
                 return -EINVAL;
 
-        spin_lock(&etnaviv_domain->map_lock);
-        pgtable_write(&etnaviv_domain->pgtable, iova,
-                      etnaviv_domain->bad_page_dma);
-        spin_unlock(&etnaviv_domain->map_lock);
+        etnaviv_domain->pgtable_cpu[index] = etnaviv_domain->base.bad_page_dma;
 
         return SZ_4K;
 }
 
-static phys_addr_t etnaviv_iommu_iova_to_phys(struct iommu_domain *domain,
-        dma_addr_t iova)
-{
-        struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
-
-        return pgtable_read(&etnaviv_domain->pgtable, iova);
-}
-
-static size_t etnaviv_iommuv1_dump_size(struct iommu_domain *domain)
+static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_domain *domain)
 {
         return PT_SIZE;
 }
 
-static void etnaviv_iommuv1_dump(struct iommu_domain *domain, void *buf)
+static void etnaviv_iommuv1_dump(struct etnaviv_iommu_domain *domain, void *buf)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
+        struct etnaviv_iommuv1_domain *etnaviv_domain =
+                        to_etnaviv_domain(domain);
 
-        memcpy(buf, etnaviv_domain->pgtable.pgtable, PT_SIZE);
+        memcpy(buf, etnaviv_domain->pgtable_cpu, PT_SIZE);
 }
 
-static const struct etnaviv_iommu_ops etnaviv_iommu_ops = {
-        .ops = {
-                .domain_free = etnaviv_domain_free,
-                .map = etnaviv_iommuv1_map,
-                .unmap = etnaviv_iommuv1_unmap,
-                .iova_to_phys = etnaviv_iommu_iova_to_phys,
-                .pgsize_bitmap = SZ_4K,
-        },
-        .dump_size = etnaviv_iommuv1_dump_size,
-        .dump = etnaviv_iommuv1_dump,
-};
-
 void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain =
+        struct etnaviv_iommuv1_domain *etnaviv_domain =
                         to_etnaviv_domain(gpu->mmu->domain);
         u32 pgtable;
 
@@ -210,7 +150,7 @@ void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 
         /* set page table address in MC */
-        pgtable = (u32)etnaviv_domain->pgtable.paddr;
+        pgtable = (u32)etnaviv_domain->pgtable_dma;
 
         gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
         gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
@@ -219,28 +159,37 @@ void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
         gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
 }
 
-struct iommu_domain *etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
+const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
+        .free = etnaviv_iommuv1_domain_free,
+        .map = etnaviv_iommuv1_map,
+        .unmap = etnaviv_iommuv1_unmap,
+        .dump_size = etnaviv_iommuv1_dump_size,
+        .dump = etnaviv_iommuv1_dump,
+};
+
+struct etnaviv_iommu_domain *
+etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
 {
-        struct etnaviv_iommu_domain *etnaviv_domain;
+        struct etnaviv_iommuv1_domain *etnaviv_domain;
+        struct etnaviv_iommu_domain *domain;
         int ret;
 
         etnaviv_domain = kzalloc(sizeof(*etnaviv_domain), GFP_KERNEL);
         if (!etnaviv_domain)
                 return NULL;
 
-        etnaviv_domain->dev = gpu->dev;
+        domain = &etnaviv_domain->base;
 
-        etnaviv_domain->domain.type = __IOMMU_DOMAIN_PAGING;
-        etnaviv_domain->domain.ops = &etnaviv_iommu_ops.ops;
-        etnaviv_domain->domain.pgsize_bitmap = SZ_4K;
-        etnaviv_domain->domain.geometry.aperture_start = GPU_MEM_START;
-        etnaviv_domain->domain.geometry.aperture_end = GPU_MEM_START + PT_ENTRIES * SZ_4K - 1;
+        domain->dev = gpu->dev;
+        domain->base = GPU_MEM_START;
+        domain->size = PT_ENTRIES * SZ_4K;
+        domain->ops = &etnaviv_iommuv1_ops;
 
         ret = __etnaviv_iommu_init(etnaviv_domain);
         if (ret)
                 goto out_free;
 
-        return &etnaviv_domain->domain;
+        return &etnaviv_domain->base;
 
 out_free:
         kfree(etnaviv_domain);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu.h b/drivers/gpu/drm/etnaviv/etnaviv_iommu.h
index 8b51e7c16feb..01d59bf70d78 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu.h
@@ -18,11 +18,14 @@
 #define __ETNAVIV_IOMMU_H__
 
 struct etnaviv_gpu;
+struct etnaviv_iommu_domain;
 
-struct iommu_domain *etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu);
+struct etnaviv_iommu_domain *
+etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu);
 void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu);
 
-struct iommu_domain *etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu);
+struct etnaviv_iommu_domain *
+etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu);
 void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu);
 
 #endif /* __ETNAVIV_IOMMU_H__ */
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
index cbe447ac5974..fc60fc8ddbf0 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/iommu.h>
 #include <linux/platform_device.h>
 #include <linux/sizes.h>
 #include <linux/slab.h>
@@ -40,10 +39,7 @@
 #define MMUv2_MAX_STLB_ENTRIES          1024
 
 struct etnaviv_iommuv2_domain {
-        struct iommu_domain domain;
-        struct device *dev;
-        void *bad_page_cpu;
-        dma_addr_t bad_page_dma;
+        struct etnaviv_iommu_domain base;
         /* M(aster) TLB aka first level pagetable */
         u32 *mtlb_cpu;
         dma_addr_t mtlb_dma;
@@ -52,13 +48,15 @@ struct etnaviv_iommuv2_domain {
         dma_addr_t stlb_dma[1024];
 };
 
-static struct etnaviv_iommuv2_domain *to_etnaviv_domain(struct iommu_domain *domain)
+static struct etnaviv_iommuv2_domain *
+to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
 {
-        return container_of(domain, struct etnaviv_iommuv2_domain, domain);
+        return container_of(domain, struct etnaviv_iommuv2_domain, base);
 }
 
-static int etnaviv_iommuv2_map(struct iommu_domain *domain, unsigned long iova,
-           phys_addr_t paddr, size_t size, int prot)
+static int etnaviv_iommuv2_map(struct etnaviv_iommu_domain *domain,
+                               unsigned long iova, phys_addr_t paddr,
+                               size_t size, int prot)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
                         to_etnaviv_domain(domain);
@@ -68,7 +66,7 @@ static int etnaviv_iommuv2_map(struct iommu_domain *domain, unsigned long iova,
         if (size != SZ_4K)
                 return -EINVAL;
 
-        if (prot & IOMMU_WRITE)
+        if (prot & ETNAVIV_PROT_WRITE)
                 entry |= MMUv2_PTE_WRITEABLE;
 
         mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
@@ -79,8 +77,8 @@ static int etnaviv_iommuv2_map(struct iommu_domain *domain, unsigned long iova,
         return 0;
 }
 
-static size_t etnaviv_iommuv2_unmap(struct iommu_domain *domain,
-        unsigned long iova, size_t size)
+static size_t etnaviv_iommuv2_unmap(struct etnaviv_iommu_domain *domain,
+                                    unsigned long iova, size_t size)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
                         to_etnaviv_domain(domain);
@@ -97,38 +95,26 @@ static size_t etnaviv_iommuv2_unmap(struct iommu_domain *domain,
         return SZ_4K;
 }
 
-static phys_addr_t etnaviv_iommuv2_iova_to_phys(struct iommu_domain *domain,
-        dma_addr_t iova)
-{
-        struct etnaviv_iommuv2_domain *etnaviv_domain =
-                        to_etnaviv_domain(domain);
-        int mtlb_entry, stlb_entry;
-
-        mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
-        stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
-
-        return etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] & ~(SZ_4K - 1);
-}
-
 static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
 {
         u32 *p;
         int ret, i, j;
 
         /* allocate scratch page */
-        etnaviv_domain->bad_page_cpu = dma_alloc_coherent(etnaviv_domain->dev,
-                                                  SZ_4K,
-                                                  &etnaviv_domain->bad_page_dma,
-                                                  GFP_KERNEL);
-        if (!etnaviv_domain->bad_page_cpu) {
+        etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
+                                                etnaviv_domain->base.dev,
+                                                SZ_4K,
+                                                &etnaviv_domain->base.bad_page_dma,
+                                                GFP_KERNEL);
+        if (!etnaviv_domain->base.bad_page_cpu) {
                 ret = -ENOMEM;
                 goto fail_mem;
         }
-        p = etnaviv_domain->bad_page_cpu;
+        p = etnaviv_domain->base.bad_page_cpu;
         for (i = 0; i < SZ_4K / 4; i++)
                 *p++ = 0xdead55aa;
 
-        etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->dev,
+        etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
                                                   SZ_4K,
                                                   &etnaviv_domain->mtlb_dma,
                                                   GFP_KERNEL);
@@ -140,7 +126,7 @@ static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
         /* pre-populate STLB pages (may want to switch to on-demand later) */
         for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
                 etnaviv_domain->stlb_cpu[i] =
-                                dma_alloc_coherent(etnaviv_domain->dev,
+                                dma_alloc_coherent(etnaviv_domain->base.dev,
                                                    SZ_4K,
                                                    &etnaviv_domain->stlb_dma[i],
                                                    GFP_KERNEL);
@@ -159,19 +145,19 @@ static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
         return 0;
 
 fail_mem:
-        if (etnaviv_domain->bad_page_cpu)
-                dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-                                  etnaviv_domain->bad_page_cpu,
-                                  etnaviv_domain->bad_page_dma);
+        if (etnaviv_domain->base.bad_page_cpu)
+                dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                                  etnaviv_domain->base.bad_page_cpu,
+                                  etnaviv_domain->base.bad_page_dma);
 
         if (etnaviv_domain->mtlb_cpu)
-                dma_free_coherent(etnaviv_domain->dev, SZ_4K,
+                dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                                   etnaviv_domain->mtlb_cpu,
                                   etnaviv_domain->mtlb_dma);
 
         for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
                 if (etnaviv_domain->stlb_cpu[i])
-                        dma_free_coherent(etnaviv_domain->dev, SZ_4K,
+                        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                                           etnaviv_domain->stlb_cpu[i],
                                           etnaviv_domain->stlb_dma[i]);
         }
@@ -179,23 +165,23 @@ fail_mem:
         return ret;
 }
 
-static void etnaviv_iommuv2_domain_free(struct iommu_domain *domain)
+static void etnaviv_iommuv2_domain_free(struct etnaviv_iommu_domain *domain)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
                         to_etnaviv_domain(domain);
         int i;
 
-        dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-                          etnaviv_domain->bad_page_cpu,
-                          etnaviv_domain->bad_page_dma);
+        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                          etnaviv_domain->base.bad_page_cpu,
+                          etnaviv_domain->base.bad_page_dma);
 
-        dma_free_coherent(etnaviv_domain->dev, SZ_4K,
+        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                           etnaviv_domain->mtlb_cpu,
                           etnaviv_domain->mtlb_dma);
 
         for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
                 if (etnaviv_domain->stlb_cpu[i])
-                        dma_free_coherent(etnaviv_domain->dev, SZ_4K,
+                        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                                           etnaviv_domain->stlb_cpu[i],
                                           etnaviv_domain->stlb_dma[i]);
         }
@@ -203,7 +189,7 @@ static void etnaviv_iommuv2_domain_free(struct iommu_domain *domain)
         vfree(etnaviv_domain);
 }
 
-static size_t etnaviv_iommuv2_dump_size(struct iommu_domain *domain)
+static size_t etnaviv_iommuv2_dump_size(struct etnaviv_iommu_domain *domain)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
                         to_etnaviv_domain(domain);
@@ -217,7 +203,7 @@ static size_t etnaviv_iommuv2_dump_size(struct iommu_domain *domain)
         return dump_size;
 }
 
-static void etnaviv_iommuv2_dump(struct iommu_domain *domain, void *buf)
+static void etnaviv_iommuv2_dump(struct etnaviv_iommu_domain *domain, void *buf)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
                         to_etnaviv_domain(domain);
@@ -230,18 +216,6 @@ static void etnaviv_iommuv2_dump(struct iommu_domain *domain, void *buf)
                         memcpy(buf, etnaviv_domain->stlb_cpu[i], SZ_4K);
 }
 
-static const struct etnaviv_iommu_ops etnaviv_iommu_ops = {
-        .ops = {
-                .domain_free = etnaviv_iommuv2_domain_free,
-                .map = etnaviv_iommuv2_map,
-                .unmap = etnaviv_iommuv2_unmap,
-                .iova_to_phys = etnaviv_iommuv2_iova_to_phys,
-                .pgsize_bitmap = SZ_4K,
-        },
-        .dump_size = etnaviv_iommuv2_dump_size,
-        .dump = etnaviv_iommuv2_dump,
-};
-
 void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain =
@@ -254,35 +228,45 @@ void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
 
         prefetch = etnaviv_buffer_config_mmuv2(gpu,
                                 (u32)etnaviv_domain->mtlb_dma,
-                                (u32)etnaviv_domain->bad_page_dma);
+                                (u32)etnaviv_domain->base.bad_page_dma);
         etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(gpu->buffer),
                              prefetch);
         etnaviv_gpu_wait_idle(gpu, 100);
 
         gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
 }
-struct iommu_domain *etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
+
+const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
+        .free = etnaviv_iommuv2_domain_free,
+        .map = etnaviv_iommuv2_map,
+        .unmap = etnaviv_iommuv2_unmap,
+        .dump_size = etnaviv_iommuv2_dump_size,
+        .dump = etnaviv_iommuv2_dump,
+};
+
+struct etnaviv_iommu_domain *
+etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
 {
         struct etnaviv_iommuv2_domain *etnaviv_domain;
+        struct etnaviv_iommu_domain *domain;
         int ret;
 
         etnaviv_domain = vzalloc(sizeof(*etnaviv_domain));
         if (!etnaviv_domain)
                 return NULL;
 
-        etnaviv_domain->dev = gpu->dev;
+        domain = &etnaviv_domain->base;
 
-        etnaviv_domain->domain.type = __IOMMU_DOMAIN_PAGING;
-        etnaviv_domain->domain.ops = &etnaviv_iommu_ops.ops;
-        etnaviv_domain->domain.pgsize_bitmap = SZ_4K;
-        etnaviv_domain->domain.geometry.aperture_start = 0;
-        etnaviv_domain->domain.geometry.aperture_end = ~0UL & ~(SZ_4K - 1);
+        domain->dev = gpu->dev;
+        domain->base = 0;
+        domain->size = (u64)SZ_1G * 4;
+        domain->ops = &etnaviv_iommuv2_ops;
 
         ret = etnaviv_iommuv2_init(etnaviv_domain);
         if (ret)
                 goto out_free;
 
-        return &etnaviv_domain->domain;
+        return &etnaviv_domain->base;
 
 out_free:
         vfree(etnaviv_domain);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
index f103e787de94..35074b944778 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
@@ -22,17 +22,64 @@
 #include "etnaviv_iommu.h"
 #include "etnaviv_mmu.h"
 
-static int etnaviv_fault_handler(struct iommu_domain *iommu, struct device *dev,
-                unsigned long iova, int flags, void *arg)
+static void etnaviv_domain_unmap(struct etnaviv_iommu_domain *domain,
+                                 unsigned long iova, size_t size)
 {
-        DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
-        return 0;
+        size_t unmapped_page, unmapped = 0;
+        size_t pgsize = SZ_4K;
+
+        if (!IS_ALIGNED(iova | size, pgsize)) {
+                pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n",
+                       iova, size, pgsize);
+                return;
+        }
+
+        while (unmapped < size) {
+                unmapped_page = domain->ops->unmap(domain, iova, pgsize);
+                if (!unmapped_page)
+                        break;
+
+                iova += unmapped_page;
+                unmapped += unmapped_page;
+        }
 }
 
-int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
-                struct sg_table *sgt, unsigned len, int prot)
+static int etnaviv_domain_map(struct etnaviv_iommu_domain *domain,
+                              unsigned long iova, phys_addr_t paddr,
+                              size_t size, int prot)
 {
-        struct iommu_domain *domain = iommu->domain;
+        unsigned long orig_iova = iova;
+        size_t pgsize = SZ_4K;
+        size_t orig_size = size;
+        int ret = 0;
+
+        if (!IS_ALIGNED(iova | paddr | size, pgsize)) {
+                pr_err("unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%x\n",
+                       iova, &paddr, size, pgsize);
+                return -EINVAL;
+        }
+
+        while (size) {
+                ret = domain->ops->map(domain, iova, paddr, pgsize, prot);
+                if (ret)
+                        break;
+
+                iova += pgsize;
+                paddr += pgsize;
+                size -= pgsize;
+        }
+
+        /* unroll mapping in case something went wrong */
+        if (ret)
+                etnaviv_domain_unmap(domain, orig_iova, orig_size - size);
+
+        return ret;
+}
+
+static int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
+                             struct sg_table *sgt, unsigned len, int prot)
+{
+        struct etnaviv_iommu_domain *domain = iommu->domain;
         struct scatterlist *sg;
         unsigned int da = iova;
         unsigned int i, j;
@@ -47,7 +94,7 @@ int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
 
                 VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes);
 
-                ret = iommu_map(domain, da, pa, bytes, prot);
+                ret = etnaviv_domain_map(domain, da, pa, bytes, prot);
                 if (ret)
                         goto fail;
 
@@ -62,27 +109,24 @@ fail:
         for_each_sg(sgt->sgl, sg, i, j) {
                 size_t bytes = sg_dma_len(sg) + sg->offset;
 
-                iommu_unmap(domain, da, bytes);
+                etnaviv_domain_unmap(domain, da, bytes);
                 da += bytes;
         }
         return ret;
 }
 
-int etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
-                struct sg_table *sgt, unsigned len)
+static void etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
+                                struct sg_table *sgt, unsigned len)
 {
-        struct iommu_domain *domain = iommu->domain;
+        struct etnaviv_iommu_domain *domain = iommu->domain;
         struct scatterlist *sg;
         unsigned int da = iova;
         int i;
 
         for_each_sg(sgt->sgl, sg, sgt->nents, i) {
                 size_t bytes = sg_dma_len(sg) + sg->offset;
-                size_t unmapped;
 
-                unmapped = iommu_unmap(domain, da, bytes);
-                if (unmapped < bytes)
-                        return unmapped;
+                etnaviv_domain_unmap(domain, da, bytes);
 
                 VERB("unmap[%d]: %08x(%zx)", i, iova, bytes);
 
@@ -90,8 +134,6 @@ int etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
 
                 da += bytes;
         }
-
-        return 0;
 }
 
 static void etnaviv_iommu_remove_mapping(struct etnaviv_iommu *mmu,
@@ -237,7 +279,7 @@ int etnaviv_iommu_map_gem(struct etnaviv_iommu *mmu,
         mmu->last_iova = node->start + etnaviv_obj->base.size;
         mapping->iova = node->start;
         ret = etnaviv_iommu_map(mmu, node->start, sgt, etnaviv_obj->base.size,
-                                IOMMU_READ | IOMMU_WRITE);
+                                ETNAVIV_PROT_READ | ETNAVIV_PROT_WRITE);
 
         if (ret < 0) {
                 drm_mm_remove_node(node);
@@ -271,7 +313,7 @@ void etnaviv_iommu_unmap_gem(struct etnaviv_iommu *mmu,
 void etnaviv_iommu_destroy(struct etnaviv_iommu *mmu)
 {
         drm_mm_takedown(&mmu->mm);
-        iommu_domain_free(mmu->domain);
+        mmu->domain->ops->free(mmu->domain);
         kfree(mmu);
 }
 
@@ -303,11 +345,7 @@ struct etnaviv_iommu *etnaviv_iommu_new(struct etnaviv_gpu *gpu)
         mutex_init(&mmu->lock);
         INIT_LIST_HEAD(&mmu->mappings);
 
-        drm_mm_init(&mmu->mm, mmu->domain->geometry.aperture_start,
-                    mmu->domain->geometry.aperture_end -
-                    mmu->domain->geometry.aperture_start + 1);
-
-        iommu_set_fault_handler(mmu->domain, etnaviv_fault_handler, gpu->dev);
+        drm_mm_init(&mmu->mm, mmu->domain->base, mmu->domain->size);
 
         return mmu;
 }
@@ -338,8 +376,8 @@ int etnaviv_iommu_get_suballoc_va(struct etnaviv_gpu *gpu, dma_addr_t paddr,
                         mutex_unlock(&mmu->lock);
                         return ret;
                 }
-                ret = iommu_map(mmu->domain, vram_node->start, paddr, size,
-                                IOMMU_READ);
+                ret = etnaviv_domain_map(mmu->domain, vram_node->start, paddr,
+                                         size, ETNAVIV_PROT_READ);
                 if (ret < 0) {
                         drm_mm_remove_node(vram_node);
                         mutex_unlock(&mmu->lock);
@@ -362,25 +400,17 @@ void etnaviv_iommu_put_suballoc_va(struct etnaviv_gpu *gpu,
 
         if (mmu->version == ETNAVIV_IOMMU_V2) {
                 mutex_lock(&mmu->lock);
-                iommu_unmap(mmu->domain,iova, size);
+                etnaviv_domain_unmap(mmu->domain, iova, size);
                 drm_mm_remove_node(vram_node);
                 mutex_unlock(&mmu->lock);
         }
 }
 size_t etnaviv_iommu_dump_size(struct etnaviv_iommu *iommu)
 {
-        struct etnaviv_iommu_ops *ops;
-
-        ops = container_of(iommu->domain->ops, struct etnaviv_iommu_ops, ops);
-
-        return ops->dump_size(iommu->domain);
+        return iommu->domain->ops->dump_size(iommu->domain);
 }
 
 void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf)
 {
-        struct etnaviv_iommu_ops *ops;
-
-        ops = container_of(iommu->domain->ops, struct etnaviv_iommu_ops, ops);
-
-        ops->dump(iommu->domain, buf);
+        iommu->domain->ops->dump(iommu->domain, buf);
 }
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.h b/drivers/gpu/drm/etnaviv/etnaviv_mmu.h
index 54be289e5981..ab603f5166b1 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.h
@@ -17,7 +17,8 @@
 #ifndef __ETNAVIV_MMU_H__
 #define __ETNAVIV_MMU_H__
 
-#include <linux/iommu.h>
+#define ETNAVIV_PROT_READ       (1 << 0)
+#define ETNAVIV_PROT_WRITE      (1 << 1)
 
 enum etnaviv_iommu_version {
         ETNAVIV_IOMMU_V1 = 0,
@@ -26,16 +27,31 @@ enum etnaviv_iommu_version {
 
 struct etnaviv_gpu;
 struct etnaviv_vram_mapping;
+struct etnaviv_iommu_domain;
 
-struct etnaviv_iommu_ops {
-        struct iommu_ops ops;
-        size_t (*dump_size)(struct iommu_domain *);
-        void (*dump)(struct iommu_domain *, void *);
+struct etnaviv_iommu_domain_ops {
+        void (*free)(struct etnaviv_iommu_domain *);
+        int (*map)(struct etnaviv_iommu_domain *domain, unsigned long iova,
+                   phys_addr_t paddr, size_t size, int prot);
+        size_t (*unmap)(struct etnaviv_iommu_domain *domain, unsigned long iova,
+                        size_t size);
+        size_t (*dump_size)(struct etnaviv_iommu_domain *);
+        void (*dump)(struct etnaviv_iommu_domain *, void *);
+};
+
+struct etnaviv_iommu_domain {
+        struct device *dev;
+        void *bad_page_cpu;
+        dma_addr_t bad_page_dma;
+        u64 base;
+        u64 size;
+
+        const struct etnaviv_iommu_domain_ops *ops;
 };
 
 struct etnaviv_iommu {
         struct etnaviv_gpu *gpu;
-        struct iommu_domain *domain;
+        struct etnaviv_iommu_domain *domain;
 
         enum etnaviv_iommu_version version;
 
@@ -49,18 +65,11 @@ struct etnaviv_iommu {
 
 struct etnaviv_gem_object;
 
-int etnaviv_iommu_attach(struct etnaviv_iommu *iommu, const char **names,
-        int cnt);
-int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
-        struct sg_table *sgt, unsigned len, int prot);
-int etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
-        struct sg_table *sgt, unsigned len);
 int etnaviv_iommu_map_gem(struct etnaviv_iommu *mmu,
         struct etnaviv_gem_object *etnaviv_obj, u32 memory_base,
         struct etnaviv_vram_mapping *mapping);
 void etnaviv_iommu_unmap_gem(struct etnaviv_iommu *mmu,
         struct etnaviv_vram_mapping *mapping);
-void etnaviv_iommu_destroy(struct etnaviv_iommu *iommu);
 
 int etnaviv_iommu_get_suballoc_va(struct etnaviv_gpu *gpu, dma_addr_t paddr,
                                   struct drm_mm_node *vram_node, size_t size,
@@ -73,6 +82,7 @@ size_t etnaviv_iommu_dump_size(struct etnaviv_iommu *iommu);
 void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf);
 
 struct etnaviv_iommu *etnaviv_iommu_new(struct etnaviv_gpu *gpu);
+void etnaviv_iommu_destroy(struct etnaviv_iommu *iommu);
 void etnaviv_iommu_restore(struct etnaviv_gpu *gpu);
 
 #endif /* __ETNAVIV_MMU_H__ */
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
new file mode 100644
index 000000000000..768f5aafdd18
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -0,0 +1,495 @@
+/*
+ * Copyright (C) 2017 Etnaviv Project
+ * Copyright (C) 2017 Zodiac Inflight Innovations
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "etnaviv_gpu.h"
+#include "etnaviv_perfmon.h"
+#include "state_hi.xml.h"
+
+struct etnaviv_pm_domain;
+
+struct etnaviv_pm_signal {
+        char name[64];
+        u32 data;
+
+        u32 (*sample)(struct etnaviv_gpu *gpu,
+                      const struct etnaviv_pm_domain *domain,
+                      const struct etnaviv_pm_signal *signal);
+};
+
+struct etnaviv_pm_domain {
+        char name[64];
+
+        /* profile register */
+        u32 profile_read;
+        u32 profile_config;
+
+        u8 nr_signals;
+        const struct etnaviv_pm_signal *signal;
+};
+
+struct etnaviv_pm_domain_meta {
+        const struct etnaviv_pm_domain *domains;
+        u32 nr_domains;
+};
+
+static u32 simple_reg_read(struct etnaviv_gpu *gpu,
+        const struct etnaviv_pm_domain *domain,
+        const struct etnaviv_pm_signal *signal)
+{
+        return gpu_read(gpu, signal->data);
+}
+
+static u32 perf_reg_read(struct etnaviv_gpu *gpu,
+        const struct etnaviv_pm_domain *domain,
+        const struct etnaviv_pm_signal *signal)
+{
+        gpu_write(gpu, domain->profile_config, signal->data);
+
+        return gpu_read(gpu, domain->profile_read);
+}
+
+static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
+        const struct etnaviv_pm_domain *domain,
+        const struct etnaviv_pm_signal *signal)
+{
+        u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+        u32 value = 0;
+        unsigned i;
+
+        for (i = 0; i < gpu->identity.pixel_pipes; i++) {
+                clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
+                clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
+                gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
+                gpu_write(gpu, domain->profile_config, signal->data);
+                value += gpu_read(gpu, domain->profile_read);
+        }
+
+        /* switch back to pixel pipe 0 to prevent GPU hang */
+        clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
+        clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
+        gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
+
+        return value;
+}
+
+static const struct etnaviv_pm_domain doms_3d[] = {
+        {
+                .name = "HI",
+                .profile_read = VIVS_MC_PROFILE_HI_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG2,
+                .nr_signals = 5,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "TOTAL_CYCLES",
+                                VIVS_HI_PROFILE_TOTAL_CYCLES,
+                                &simple_reg_read
+                        },
+                        {
+                                "IDLE_CYCLES",
+                                VIVS_HI_PROFILE_IDLE_CYCLES,
+                                &simple_reg_read
+                        },
+                        {
+                                "AXI_CYCLES_READ_REQUEST_STALLED",
+                                VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
+                                &perf_reg_read
+                        },
+                        {
+                                "AXI_CYCLES_WRITE_REQUEST_STALLED",
+                                VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
+                                &perf_reg_read
+                        },
+                        {
+                                "AXI_CYCLES_WRITE_DATA_STALLED",
+                                VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
+                                &perf_reg_read
+                        }
+                }
+        },
+        {
+                .name = "PE",
+                .profile_read = VIVS_MC_PROFILE_PE_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG0,
+                .nr_signals = 5,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
+                                VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
+                                &pipe_reg_read
+                        },
+                        {
+                                "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
+                                VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
+                                &pipe_reg_read
+                        },
+                        {
+                                "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
+                                VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
+                                &pipe_reg_read
+                        },
+                        {
+                                "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
+                                VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
+                                &pipe_reg_read
+                        }
+                }
+        },
+        {
+                .name = "SH",
+                .profile_read = VIVS_MC_PROFILE_SH_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG0,
+                .nr_signals = 9,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "SHADER_CYCLES",
+                                VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
+                                &perf_reg_read
+                        },
+                        {
+                                "PS_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "RENDERED_PIXEL_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "VS_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "RENDERED_VERTICE_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "VTX_BRANCH_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "VTX_TEXLD_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "PXL_BRANCH_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "PXL_TEXLD_INST_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
+                                &pipe_reg_read
+                        }
+                }
+        },
+        {
+                .name = "PA",
+                .profile_read = VIVS_MC_PROFILE_PA_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG1,
+                .nr_signals = 6,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "INPUT_VTX_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "INPUT_PRIM_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "OUTPUT_PRIM_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "DEPTH_CLIPPED_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "TRIVIAL_REJECTED_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
+                                &pipe_reg_read
+                        },
+                        {
+                                "CULLED_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
+                                &pipe_reg_read
+                        }
+                }
+        },
+        {
+                .name = "SE",
+                .profile_read = VIVS_MC_PROFILE_SE_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG1,
+                .nr_signals = 2,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "CULLED_TRIANGLE_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "CULLED_LINES_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT,
+                                &perf_reg_read
+                        }
+                }
+        },
+        {
+                .name = "RA",
+                .profile_read = VIVS_MC_PROFILE_RA_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG1,
+                .nr_signals = 7,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "VALID_PIXEL_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_QUAD_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "VALID_QUAD_COUNT_AFTER_EARLY_Z",
+                                VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_PRIMITIVE_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "PIPE_CACHE_MISS_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "PREFETCH_CACHE_MISS_COUNTER",
+                                VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
+                                &perf_reg_read
+                        },
+                        {
+                                "CULLED_QUAD_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
+                                &perf_reg_read
+                        }
+                }
+        },
+        {
+                .name = "TX",
+                .profile_read = VIVS_MC_PROFILE_TX_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG1,
+                .nr_signals = 9,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "TOTAL_BILINEAR_REQUESTS",
+                                VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_TRILINEAR_REQUESTS",
+                                VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_DISCARDED_TEXTURE_REQUESTS",
+                                VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_TEXTURE_REQUESTS",
+                                VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
+                                &perf_reg_read
+                        },
+                        {
+                                "MEM_READ_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "MEM_READ_IN_8B_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "CACHE_MISS_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "CACHE_HIT_TEXEL_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
+                                &perf_reg_read
+                        },
+                        {
+                                "CACHE_MISS_TEXEL_COUNT",
+                                VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
+                                &perf_reg_read
+                        }
+                }
+        },
+        {
+                .name = "MC",
+                .profile_read = VIVS_MC_PROFILE_MC_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG2,
+                .nr_signals = 3,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "TOTAL_READ_REQ_8B_FROM_PIPELINE",
+                                VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_READ_REQ_8B_FROM_IP",
+                                VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP,
+                                &perf_reg_read
+                        },
+                        {
+                                "TOTAL_WRITE_REQ_8B_FROM_PIPELINE",
+                                VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE,
+                                &perf_reg_read
+                        }
+                }
+        }
+};
+
+static const struct etnaviv_pm_domain doms_2d[] = {
+        {
+                .name = "PE",
+                .profile_read = VIVS_MC_PROFILE_PE_READ,
+                .profile_config = VIVS_MC_PROFILE_CONFIG0,
+                .nr_signals = 1,
+                .signal = (const struct etnaviv_pm_signal[]) {
+                        {
+                                "PIXELS_RENDERED_2D",
+                                VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
+                                &pipe_reg_read
+                        }
+                }
+        }
+};
+
+static const struct etnaviv_pm_domain doms_vg[] = {
+};
+
+static const struct etnaviv_pm_domain_meta doms_meta[] = {
+        {
+                .nr_domains = ARRAY_SIZE(doms_3d),
+                .domains = &doms_3d[0]
+        },
+        {
+                .nr_domains = ARRAY_SIZE(doms_2d),
+                .domains = &doms_2d[0]
+        },
+        {
+                .nr_domains = ARRAY_SIZE(doms_vg),
+                .domains = &doms_vg[0]
+        }
+};
+
+int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
+        struct drm_etnaviv_pm_domain *domain)
+{
+        const struct etnaviv_pm_domain_meta *meta = &doms_meta[domain->pipe];
+        const struct etnaviv_pm_domain *dom;
+
+        if (domain->iter >= meta->nr_domains)
+                return -EINVAL;
+
+        dom = meta->domains + domain->iter;
+
+        domain->id = domain->iter;
+        domain->nr_signals = dom->nr_signals;
+        strncpy(domain->name, dom->name, sizeof(domain->name));
+
+        domain->iter++;
+        if (domain->iter == meta->nr_domains)
+                domain->iter = 0xff;
+
+        return 0;
+}
+
+int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
+        struct drm_etnaviv_pm_signal *signal)
+{
+        const struct etnaviv_pm_domain_meta *meta = &doms_meta[signal->pipe];
+        const struct etnaviv_pm_domain *dom;
+        const struct etnaviv_pm_signal *sig;
+
+        if (signal->domain >= meta->nr_domains)
+                return -EINVAL;
+
+        dom = meta->domains + signal->domain;
+
+        if (signal->iter > dom->nr_signals)
+                return -EINVAL;
+
+        sig = &dom->signal[signal->iter];
+
+        signal->id = signal->iter;
+        strncpy(signal->name, sig->name, sizeof(signal->name));
+
+        signal->iter++;
+        if (signal->iter == dom->nr_signals)
+                signal->iter = 0xffff;
+
+        return 0;
+}
+
+int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
+        u32 exec_state)
+{
+        const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
+        const struct etnaviv_pm_domain *dom;
+
+        if (r->domain >= meta->nr_domains)
+                return -EINVAL;
+
+        dom = meta->domains + r->domain;
+
+        if (r->signal > dom->nr_signals)
+                return -EINVAL;
+
+        return 0;
+}
+
+void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
+        const struct etnaviv_perfmon_request *pmr)
+{
+        const struct etnaviv_pm_domain_meta *meta = &doms_meta[gpu->exec_state];
+        const struct etnaviv_pm_domain *dom;
+        const struct etnaviv_pm_signal *sig;
+        u32 *bo = pmr->bo_vma;
+        u32 val;
+
+        dom = meta->domains + pmr->domain;
+        sig = &dom->signal[pmr->signal];
+        val = sig->sample(gpu, dom, sig);
+
+        *(bo + pmr->offset) = val;
+}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.h b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.h
new file mode 100644
index 000000000000..35dce194cb00
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2017 Etnaviv Project
+ * Copyright (C) 2017 Zodiac Inflight Innovations
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ETNAVIV_PERFMON_H__
+#define __ETNAVIV_PERFMON_H__
+
+struct etnaviv_gpu;
+struct drm_etnaviv_pm_domain;
+struct drm_etnaviv_pm_signal;
+
+struct etnaviv_perfmon_request
+{
+        u32 flags;
+        u8 domain;
+        u8 signal;
+        u32 sequence;
+
+        /* bo to store a value */
+        u32 *bo_vma;
+        u32 offset;
+};
+
+int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
+        struct drm_etnaviv_pm_domain *domain);
+
+int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
+        struct drm_etnaviv_pm_signal *signal);
+
+int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
+        u32 exec_state);
+
+void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
+        const struct etnaviv_perfmon_request *pmr);
+
+#endif /* __ETNAVIV_PERFMON_H__ */
diff --git a/drivers/gpu/drm/gma500/mid_bios.c b/drivers/gpu/drm/gma500/mid_bios.c
index d75ecb3bdee7..1fa163373a47 100644
--- a/drivers/gpu/drm/gma500/mid_bios.c
+++ b/drivers/gpu/drm/gma500/mid_bios.c
@@ -237,7 +237,7 @@ static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
 
         gct = kmalloc(sizeof(*gct) * vbt.panel_count, GFP_KERNEL);
         if (!gct)
-                return -1;
+                return -ENOMEM;
 
         gct_virtual = ioremap(addr + sizeof(vbt),
                         sizeof(*gct) * vbt.panel_count);
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index e787d376ba67..84507912be84 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -37,6 +37,7 @@
 #include "psb_drv.h"
 #include "psb_intel_sdvo_regs.h"
 #include "psb_intel_reg.h"
+#include <linux/kernel.h>
 
 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
 #define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
@@ -62,8 +63,6 @@ static const char *tv_format_names[] = {
         "SECAM_60"
 };
 
-#define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))
-
 struct psb_intel_sdvo {
         struct gma_encoder base;
 
@@ -148,7 +147,7 @@ struct psb_intel_sdvo_connector {
         int force_audio;
 
         /* This contains all current supported TV format */
-        u8 tv_format_supported[TV_FORMAT_NUM];
+        u8 tv_format_supported[ARRAY_SIZE(tv_format_names)];
         int   format_supported_num;
         struct drm_property *tv_format;
 
@@ -1709,7 +1708,7 @@ psb_intel_sdvo_set_property(struct drm_connector *connector,
         }
 
         if (property == psb_intel_sdvo_connector->tv_format) {
-                if (val >= TV_FORMAT_NUM)
+                if (val >= ARRAY_SIZE(tv_format_names))
                         return -EINVAL;
 
                 if (psb_intel_sdvo->tv_format_index ==
@@ -2269,7 +2268,7 @@ static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_s
                 return false;
 
         psb_intel_sdvo_connector->format_supported_num = 0;
-        for (i = 0 ; i < TV_FORMAT_NUM; i++)
+        for (i = 0 ; i < ARRAY_SIZE(tv_format_names); i++)
                 if (format_map & (1 << i))
                         psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
 
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
index ec4dd9df9150..f4eba87c96f3 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
@@ -36,7 +36,7 @@ static int hibmc_connector_mode_valid(struct drm_connector *connector,
 static struct drm_encoder *
 hibmc_connector_best_encoder(struct drm_connector *connector)
 {
-        return drm_encoder_find(connector->dev, connector->encoder_ids[0]);
+        return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
 }
 
 static const struct drm_connector_helper_funcs
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
index c19ab4f91ae7..ddb0403f1975 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
@@ -237,8 +237,8 @@ static int kirin_drm_platform_probe(struct platform_device *pdev)
         }
 
         remote = of_graph_get_remote_node(np, 0, 0);
-        if (IS_ERR(remote))
-                return PTR_ERR(remote);
+        if (!remote)
+                return -ENODEV;
 
         drm_of_component_match_add(dev, &match, compare_of, remote);
         of_node_put(remote);
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index e9e64e8e9765..dfd95889f4b7 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -12,6 +12,7 @@ config DRM_I915
         select DRM_PANEL
         select DRM_MIPI_DSI
         select RELAY
+        select IRQ_WORK
         # i915 depends on ACPI_VIDEO when ACPI is enabled
         # but for select to work, need to select ACPI_VIDEO's dependencies, ick
         select BACKLIGHT_LCD_SUPPORT if ACPI
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1cb8059a3a16..5182e3d5557d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,7 +139,8 @@ i915-y += i915_perf.o \
           i915_oa_bxt.o \
           i915_oa_kblgt2.o \
           i915_oa_kblgt3.o \
-          i915_oa_glk.o
+          i915_oa_glk.o \
+          i915_oa_cflgt2.o
 
 ifeq ($(CONFIG_DRM_I915_GVT),y)
 i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c
index ff3154fe6588..ab19545d59a1 100644
--- a/drivers/gpu/drm/i915/gvt/cfg_space.c
+++ b/drivers/gpu/drm/i915/gvt/cfg_space.c
@@ -101,7 +101,7 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
         if (WARN_ON(bytes > 4))
                 return -EINVAL;
 
-        if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
+        if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
                 return -EINVAL;
 
         memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -110,13 +110,25 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
 
 static int map_aperture(struct intel_vgpu *vgpu, bool map)
 {
-        u64 first_gfn, first_mfn;
+        phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu);
+        unsigned long aperture_sz = vgpu_aperture_sz(vgpu);
+        u64 first_gfn;
         u64 val;
         int ret;
 
         if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
                 return 0;
 
+        if (map) {
+                vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz,
+                                                MEMREMAP_WC);
+                if (!vgpu->gm.aperture_va)
+                        return -ENOMEM;
+        } else {
+                memunmap(vgpu->gm.aperture_va);
+                vgpu->gm.aperture_va = NULL;
+        }
+
         val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
         if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
                 val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
@@ -124,14 +136,16 @@ static int map_aperture(struct intel_vgpu *vgpu, bool map)
                 val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
 
         first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
-        first_mfn = vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT;
 
         ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
-                                                  first_mfn,
-                                                  vgpu_aperture_sz(vgpu) >>
-                                                  PAGE_SHIFT, map);
-        if (ret)
+                                                  aperture_pa >> PAGE_SHIFT,
+                                                  aperture_sz >> PAGE_SHIFT,
+                                                  map);
+        if (ret) {
+                memunmap(vgpu->gm.aperture_va);
+                vgpu->gm.aperture_va = NULL;
                 return ret;
+        }
 
         vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
         return 0;
@@ -275,7 +289,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
         if (WARN_ON(bytes > 4))
                 return -EINVAL;
 
-        if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
+        if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
                 return -EINVAL;
 
         /* First check if it's PCI_COMMAND */
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 21c36e256884..2c0ccbb817dc 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1576,11 +1576,11 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s)
         return 1;
 }
 
-static uint32_t find_bb_size(struct parser_exec_state *s)
+static int find_bb_size(struct parser_exec_state *s)
 {
         unsigned long gma = 0;
         struct cmd_info *info;
-        uint32_t bb_size = 0;
+        int bb_size = 0;
         uint32_t cmd_len = 0;
         bool met_bb_end = false;
         struct intel_vgpu *vgpu = s->vgpu;
@@ -1637,6 +1637,8 @@ static int perform_bb_shadow(struct parser_exec_state *s)
 
         /* get the size of the batch buffer */
         bb_size = find_bb_size(s);
+        if (bb_size < 0)
+                return -EINVAL;
 
         /* allocate shadow batch buffer */
         entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
@@ -2603,7 +2605,8 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
 {
         struct intel_vgpu *vgpu = workload->vgpu;
         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
-        u32 *cs;
+        void *shadow_ring_buffer_va;
+        int ring_id = workload->ring_id;
         int ret;
 
         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
@@ -2616,34 +2619,42 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
         gma_tail = workload->rb_start + workload->rb_tail;
         gma_top = workload->rb_start + guest_rb_size;
 
-        /* allocate shadow ring buffer */
-        cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
-        if (IS_ERR(cs))
-                return PTR_ERR(cs);
+        if (workload->rb_len > vgpu->reserve_ring_buffer_size[ring_id]) {
+                void *va = vgpu->reserve_ring_buffer_va[ring_id];
+                /* realloc the new ring buffer if needed */
+                vgpu->reserve_ring_buffer_va[ring_id] =
+                        krealloc(va, workload->rb_len, GFP_KERNEL);
+                if (!vgpu->reserve_ring_buffer_va[ring_id]) {
+                        gvt_vgpu_err("fail to alloc reserve ring buffer\n");
+                        return -ENOMEM;
+                }
+                vgpu->reserve_ring_buffer_size[ring_id] = workload->rb_len;
+        }
+
+        shadow_ring_buffer_va = vgpu->reserve_ring_buffer_va[ring_id];
 
         /* get shadow ring buffer va */
-        workload->shadow_ring_buffer_va = cs;
+        workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
 
         /* head > tail --> copy head <-> top */
         if (gma_head > gma_tail) {
                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
-                                      gma_head, gma_top, cs);
+                                      gma_head, gma_top, shadow_ring_buffer_va);
                 if (ret < 0) {
                         gvt_vgpu_err("fail to copy guest ring buffer\n");
                         return ret;
                 }
-                cs += ret / sizeof(u32);
+                shadow_ring_buffer_va += ret;
                 gma_head = workload->rb_start;
         }
 
         /* copy head or start <-> tail */
-        ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, cs);
+        ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
+                                shadow_ring_buffer_va);
         if (ret < 0) {
                 gvt_vgpu_err("fail to copy guest ring buffer\n");
                 return ret;
         }
-        cs += ret / sizeof(u32);
-        intel_ring_advance(workload->req, cs);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index 91b4300f3b39..5ec07ecf33ad 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -368,7 +368,7 @@ static void free_workload(struct intel_vgpu_workload *workload)
 #define get_desc_from_elsp_dwords(ed, i) \
         ((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
 
-static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
+static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 {
         const int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
         struct intel_shadow_bb_entry *entry_obj;
@@ -379,7 +379,7 @@ static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 
                 vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
                 if (IS_ERR(vma)) {
-                        return;
+                        return PTR_ERR(vma);
                 }
 
                 /* FIXME: we are not tracking our pinned VMA leaving it
@@ -392,6 +392,7 @@ static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
                 if (gmadr_bytes == 8)
                         entry_obj->bb_start_cmd_va[2] = 0;
         }
+        return 0;
 }
 
 static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
@@ -420,7 +421,7 @@ static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
         return 0;
 }
 
-static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 {
         struct i915_vma *vma;
         unsigned char *per_ctx_va =
@@ -428,12 +429,12 @@ static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
                 wa_ctx->indirect_ctx.size;
 
         if (wa_ctx->indirect_ctx.size == 0)
-                return;
+                return 0;
 
         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
                                        0, CACHELINE_BYTES, 0);
         if (IS_ERR(vma)) {
-                return;
+                return PTR_ERR(vma);
         }
 
         /* FIXME: we are not tracking our pinned VMA leaving it
@@ -447,26 +448,7 @@ static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
         memset(per_ctx_va, 0, CACHELINE_BYTES);
 
         update_wa_ctx_2_shadow_ctx(wa_ctx);
-}
-
-static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
-{
-        struct intel_vgpu *vgpu = workload->vgpu;
-        struct execlist_ctx_descriptor_format ctx[2];
-        int ring_id = workload->ring_id;
-
-        intel_vgpu_pin_mm(workload->shadow_mm);
-        intel_vgpu_sync_oos_pages(workload->vgpu);
-        intel_vgpu_flush_post_shadow(workload->vgpu);
-        prepare_shadow_batch_buffer(workload);
-        prepare_shadow_wa_ctx(&workload->wa_ctx);
-        if (!workload->emulate_schedule_in)
-                return 0;
-
-        ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
-        ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
-
-        return emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
+        return 0;
 }
 
 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
@@ -489,13 +471,62 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
         }
 }
 
-static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
 {
-        if (!wa_ctx->indirect_ctx.obj)
-                return;
+        struct intel_vgpu *vgpu = workload->vgpu;
+        struct execlist_ctx_descriptor_format ctx[2];
+        int ring_id = workload->ring_id;
+        int ret;
+
+        ret = intel_vgpu_pin_mm(workload->shadow_mm);
+        if (ret) {
+                gvt_vgpu_err("fail to vgpu pin mm\n");
+                goto out;
+        }
+
+        ret = intel_vgpu_sync_oos_pages(workload->vgpu);
+        if (ret) {
+                gvt_vgpu_err("fail to vgpu sync oos pages\n");
+                goto err_unpin_mm;
+        }
 
-        i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
-        i915_gem_object_put(wa_ctx->indirect_ctx.obj);
+        ret = intel_vgpu_flush_post_shadow(workload->vgpu);
+        if (ret) {
+                gvt_vgpu_err("fail to flush post shadow\n");
+                goto err_unpin_mm;
+        }
+
+        ret = prepare_shadow_batch_buffer(workload);
+        if (ret) {
+                gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
+                goto err_unpin_mm;
+        }
+
+        ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
+        if (ret) {
+                gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
+                goto err_shadow_batch;
+        }
+
+        if (!workload->emulate_schedule_in)
+                return 0;
+
+        ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
+        ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
+
+        ret = emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
+        if (!ret)
+                goto out;
+        else
+                gvt_vgpu_err("fail to emulate execlist schedule in\n");
+
+        release_shadow_wa_ctx(&workload->wa_ctx);
+err_shadow_batch:
+        release_shadow_batch_buffer(workload);
+err_unpin_mm:
+        intel_vgpu_unpin_mm(workload->shadow_mm);
+out:
+        return ret;
 }
 
 static int complete_execlist_workload(struct intel_vgpu_workload *workload)
@@ -511,8 +542,10 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
         gvt_dbg_el("complete workload %p status %d\n", workload,
                         workload->status);
 
-        release_shadow_batch_buffer(workload);
-        release_shadow_wa_ctx(&workload->wa_ctx);
+        if (!workload->status) {
+                release_shadow_batch_buffer(workload);
+                release_shadow_wa_ctx(&workload->wa_ctx);
+        }
 
         if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
                 /* if workload->status is not successful means HW GPU
@@ -820,10 +853,21 @@ static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask)
 
 void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)
 {
+        enum intel_engine_id i;
+        struct intel_engine_cs *engine;
+
         clean_workloads(vgpu, ALL_ENGINES);
         kmem_cache_destroy(vgpu->workloads);
+
+        for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+                kfree(vgpu->reserve_ring_buffer_va[i]);
+                vgpu->reserve_ring_buffer_va[i] = NULL;
+                vgpu->reserve_ring_buffer_size[i] = 0;
+        }
+
 }
 
+#define RESERVE_RING_BUFFER_SIZE                ((1 * PAGE_SIZE)/8)
 int intel_vgpu_init_execlist(struct intel_vgpu *vgpu)
 {
         enum intel_engine_id i;
@@ -843,7 +887,26 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu)
         if (!vgpu->workloads)
                 return -ENOMEM;
 
+        /* each ring has a shadow ring buffer until vgpu destroyed */
+        for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+                vgpu->reserve_ring_buffer_va[i] =
+                        kmalloc(RESERVE_RING_BUFFER_SIZE, GFP_KERNEL);
+                if (!vgpu->reserve_ring_buffer_va[i]) {
+                        gvt_vgpu_err("fail to alloc reserve ring buffer\n");
+                        goto out;
+                }
+                vgpu->reserve_ring_buffer_size[i] = RESERVE_RING_BUFFER_SIZE;
+        }
         return 0;
+out:
+        for_each_engine(engine, vgpu->gvt->dev_priv, i) {
+                if (vgpu->reserve_ring_buffer_size[i]) {
+                        kfree(vgpu->reserve_ring_buffer_va[i]);
+                        vgpu->reserve_ring_buffer_va[i] = NULL;
+                        vgpu->reserve_ring_buffer_size[i] = 0;
+                }
+        }
+        return -ENOMEM;
 }
 
 void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index e6dfc3331f4b..2801d70579d8 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1647,14 +1647,13 @@ int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
         if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
                 return 0;
 
-        atomic_inc(&mm->pincount);
-
         if (!mm->shadowed) {
                 ret = shadow_mm(mm);
                 if (ret)
                         return ret;
         }
 
+        atomic_inc(&mm->pincount);
         list_del_init(&mm->lru_list);
         list_add_tail(&mm->lru_list, &mm->vgpu->gvt->gtt.mm_lru_list_head);
         return 0;
@@ -1972,7 +1971,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
                  */
                 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
                 if (type == GTT_TYPE_PPGTT_PDE_PT)
-                        se.val64 |= PPAT_CACHED_INDEX;
+                        se.val64 |= PPAT_CACHED;
 
                 for (i = 0; i < page_entry_num; i++)
                         ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index c27c6838eaca..aaa347f8620c 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -111,7 +111,7 @@ static void init_device_info(struct intel_gvt *gvt)
         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
                 || IS_KABYLAKE(gvt->dev_priv)) {
                 info->max_support_vgpus = 8;
-                info->cfg_space_size = 256;
+                info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
                 info->mmio_size = 2 * 1024 * 1024;
                 info->mmio_bar = 0;
                 info->gtt_start_offset = 8 * 1024 * 1024;
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 44b719eda8c4..9c2e7c0aa38f 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -80,6 +80,7 @@ struct intel_gvt_device_info {
 struct intel_vgpu_gm {
         u64 aperture_sz;
         u64 hidden_sz;
+        void *aperture_va;
         struct drm_mm_node low_gm_node;
         struct drm_mm_node high_gm_node;
 };
@@ -99,7 +100,6 @@ struct intel_vgpu_mmio {
         bool disable_warn_untrack;
 };
 
-#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
 #define INTEL_GVT_MAX_BAR_NUM 4
 
 struct intel_vgpu_pci_bar {
@@ -108,7 +108,7 @@ struct intel_vgpu_pci_bar {
 };
 
 struct intel_vgpu_cfg_space {
-        unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
+        unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
         struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
 };
 
@@ -165,6 +165,9 @@ struct intel_vgpu {
         struct list_head workload_q_head[I915_NUM_ENGINES];
         struct kmem_cache *workloads;
         atomic_t running_workload_num;
+        /* 1/2K for each reserve ring buffer */
+        void *reserve_ring_buffer_va[I915_NUM_ENGINES];
+        int reserve_ring_buffer_size[I915_NUM_ENGINES];
         DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
         struct i915_gem_context *shadow_ctx;
         DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
@@ -474,6 +477,13 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
                 void *p_data, unsigned int bytes);
 
+static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
+{
+        /* We are 64bit bar. */
+        return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
+                        PCI_BASE_ADDRESS_MEM_MASK;
+}
+
 void intel_gvt_clean_opregion(struct intel_gvt *gvt);
 int intel_gvt_init_opregion(struct intel_gvt *gvt);
 
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 83e88c70272a..96060920a6fe 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -609,21 +609,20 @@ static void intel_vgpu_release_work(struct work_struct *work)
         __intel_vgpu_release(vgpu);
 }
 
-static uint64_t intel_vgpu_get_bar0_addr(struct intel_vgpu *vgpu)
+static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
 {
         u32 start_lo, start_hi;
         u32 mem_type;
-        int pos = PCI_BASE_ADDRESS_0;
 
-        start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + pos)) &
+        start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
                         PCI_BASE_ADDRESS_MEM_MASK;
-        mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + pos)) &
+        mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
                         PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 
         switch (mem_type) {
         case PCI_BASE_ADDRESS_MEM_TYPE_64:
                 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space
-                                                + pos + 4));
+                                                + bar + 4));
                 break;
         case PCI_BASE_ADDRESS_MEM_TYPE_32:
         case PCI_BASE_ADDRESS_MEM_TYPE_1M:
@@ -637,6 +636,21 @@ static uint64_t intel_vgpu_get_bar0_addr(struct intel_vgpu *vgpu)
         return ((u64)start_hi << 32) | start_lo;
 }
 
+static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
+                             void *buf, unsigned int count, bool is_write)
+{
+        uint64_t bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
+        int ret;
+
+        if (is_write)
+                ret = intel_gvt_ops->emulate_mmio_write(vgpu,
+                                        bar_start + off, buf, count);
+        else
+                ret = intel_gvt_ops->emulate_mmio_read(vgpu,
+                                        bar_start + off, buf, count);
+        return ret;
+}
+
 static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
                         size_t count, loff_t *ppos, bool is_write)
 {
@@ -661,20 +675,14 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
                                                 buf, count);
                 break;
         case VFIO_PCI_BAR0_REGION_INDEX:
-        case VFIO_PCI_BAR1_REGION_INDEX:
-                if (is_write) {
-                        uint64_t bar0_start = intel_vgpu_get_bar0_addr(vgpu);
-
-                        ret = intel_gvt_ops->emulate_mmio_write(vgpu,
-                                                bar0_start + pos, buf, count);
-                } else {
-                        uint64_t bar0_start = intel_vgpu_get_bar0_addr(vgpu);
-
-                        ret = intel_gvt_ops->emulate_mmio_read(vgpu,
-                                                bar0_start + pos, buf, count);
-                }
+                ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos,
+                                        buf, count, is_write);
                 break;
         case VFIO_PCI_BAR2_REGION_INDEX:
+                ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_2, pos,
+                                        buf, count, is_write);
+                break;
+        case VFIO_PCI_BAR1_REGION_INDEX:
         case VFIO_PCI_BAR3_REGION_INDEX:
         case VFIO_PCI_BAR4_REGION_INDEX:
         case VFIO_PCI_BAR5_REGION_INDEX:
@@ -970,7 +978,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd,
                 switch (info.index) {
                 case VFIO_PCI_CONFIG_REGION_INDEX:
                         info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index);
-                        info.size = INTEL_GVT_MAX_CFG_SPACE_SZ;
+                        info.size = vgpu->gvt->device_info.cfg_space_size;
                         info.flags = VFIO_REGION_INFO_FLAG_READ |
                                      VFIO_REGION_INFO_FLAG_WRITE;
                         break;
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 980ec8906b1e..1e1310f50289 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -45,8 +45,7 @@
  */
 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
 {
-        u64 gttmmio_gpa = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0) &
-                          ~GENMASK(3, 0);
+        u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
         return gpa - gttmmio_gpa;
 }
 
@@ -57,6 +56,38 @@ int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
         (reg >= gvt->device_info.gtt_start_offset \
          && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
 
+static bool vgpu_gpa_is_aperture(struct intel_vgpu *vgpu, uint64_t gpa)
+{
+        u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
+        u64 aperture_sz = vgpu_aperture_sz(vgpu);
+
+        return gpa >= aperture_gpa && gpa < aperture_gpa + aperture_sz;
+}
+
+static int vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t gpa,
+                            void *pdata, unsigned int size, bool is_read)
+{
+        u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
+        u64 offset = gpa - aperture_gpa;
+
+        if (!vgpu_gpa_is_aperture(vgpu, gpa + size - 1)) {
+                gvt_vgpu_err("Aperture rw out of range, offset %llx, size %d\n",
+                             offset, size);
+                return -EINVAL;
+        }
+
+        if (!vgpu->gm.aperture_va) {
+                gvt_vgpu_err("BAR is not enabled\n");
+                return -ENXIO;
+        }
+
+        if (is_read)
+                memcpy(pdata, vgpu->gm.aperture_va + offset, size);
+        else
+                memcpy(vgpu->gm.aperture_va + offset, pdata, size);
+        return 0;
+}
+
 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
                 void *p_data, unsigned int bytes, bool read)
 {
@@ -133,6 +164,12 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
         }
         mutex_lock(&gvt->lock);
 
+        if (vgpu_gpa_is_aperture(vgpu, pa)) {
+                ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, true);
+                mutex_unlock(&gvt->lock);
+                return ret;
+        }
+
         if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
                 struct intel_vgpu_guest_page *gp;
 
@@ -224,6 +261,12 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
 
         mutex_lock(&gvt->lock);
 
+        if (vgpu_gpa_is_aperture(vgpu, pa)) {
+                ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, false);
+                mutex_unlock(&gvt->lock);
+                return ret;
+        }
+
         if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
                 struct intel_vgpu_guest_page *gp;
 
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index 2ea542257f03..6d066cf35478 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -293,7 +293,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
                  */
                 if (mmio->in_context &&
                                 ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-                                i915.enable_execlists)
+                                i915_modparams.enable_execlists)
                         continue;
 
                 if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 391800d2067b..d5892d24f0b6 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -87,7 +87,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
                         return -EINVAL;
                 }
 
-                page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
+                page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
                 dst = kmap(page);
                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
                                 GTT_PAGE_SIZE);
@@ -201,6 +201,43 @@ static void shadow_context_descriptor_update(struct i915_gem_context *ctx,
         ce->lrc_desc = desc;
 }
 
+static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
+{
+        struct intel_vgpu *vgpu = workload->vgpu;
+        void *shadow_ring_buffer_va;
+        u32 *cs;
+
+        /* allocate shadow ring buffer */
+        cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
+        if (IS_ERR(cs)) {
+                gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
+                        workload->rb_len);
+                return PTR_ERR(cs);
+        }
+
+        shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
+
+        /* get shadow ring buffer va */
+        workload->shadow_ring_buffer_va = cs;
+
+        memcpy(cs, shadow_ring_buffer_va,
+                        workload->rb_len);
+
+        cs += workload->rb_len / sizeof(u32);
+        intel_ring_advance(workload->req, cs);
+
+        return 0;
+}
+
+void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
+{
+        if (!wa_ctx->indirect_ctx.obj)
+                return;
+
+        i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
+        i915_gem_object_put(wa_ctx->indirect_ctx.obj);
+}
+
 /**
  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
  * shadow it as well, include ringbuffer,wa_ctx and ctx.
@@ -214,8 +251,10 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         int ring_id = workload->ring_id;
         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
+        struct intel_engine_cs *engine = dev_priv->engine[ring_id];
         struct drm_i915_gem_request *rq;
         struct intel_vgpu *vgpu = workload->vgpu;
+        struct intel_ring *ring;
         int ret;
 
         lockdep_assert_held(&dev_priv->drm.struct_mutex);
@@ -231,35 +270,56 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
                 shadow_context_descriptor_update(shadow_ctx,
                                         dev_priv->engine[ring_id]);
 
-        rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
-        if (IS_ERR(rq)) {
-                gvt_vgpu_err("fail to allocate gem request\n");
-                ret = PTR_ERR(rq);
-                goto out;
-        }
-
-        gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
-
-        workload->req = i915_gem_request_get(rq);
-
         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
         if (ret)
-                goto out;
+                goto err_scan;
 
         if ((workload->ring_id == RCS) &&
             (workload->wa_ctx.indirect_ctx.size != 0)) {
                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
                 if (ret)
-                        goto out;
+                        goto err_scan;
+        }
+
+        /* pin shadow context by gvt even the shadow context will be pinned
+         * when i915 alloc request. That is because gvt will update the guest
+         * context from shadow context when workload is completed, and at that
+         * moment, i915 may already unpined the shadow context to make the
+         * shadow_ctx pages invalid. So gvt need to pin itself. After update
+         * the guest context, gvt can unpin the shadow_ctx safely.
+         */
+        ring = engine->context_pin(engine, shadow_ctx);
+        if (IS_ERR(ring)) {
+                ret = PTR_ERR(ring);
+                gvt_vgpu_err("fail to pin shadow context\n");
+                goto err_shadow;
         }
 
         ret = populate_shadow_context(workload);
         if (ret)
-                goto out;
+                goto err_unpin;
 
+        rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
+        if (IS_ERR(rq)) {
+                gvt_vgpu_err("fail to allocate gem request\n");
+                ret = PTR_ERR(rq);
+                goto err_unpin;
+        }
+
+        gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
+
+        workload->req = i915_gem_request_get(rq);
+        ret = copy_workload_to_ring_buffer(workload);
+        if (ret)
+                goto err_unpin;
         workload->shadowed = true;
+        return 0;
 
-out:
+err_unpin:
+        engine->context_unpin(engine, shadow_ctx);
+err_shadow:
+        release_shadow_wa_ctx(&workload->wa_ctx);
+err_scan:
         return ret;
 }
 
@@ -269,8 +329,6 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
         struct intel_engine_cs *engine = dev_priv->engine[ring_id];
-        struct intel_vgpu *vgpu = workload->vgpu;
-        struct intel_ring *ring;
         int ret = 0;
 
         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
@@ -284,22 +342,10 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
 
         if (workload->prepare) {
                 ret = workload->prepare(workload);
-                if (ret)
+                if (ret) {
+                        engine->context_unpin(engine, shadow_ctx);
                         goto out;
-        }
-
-        /* pin shadow context by gvt even the shadow context will be pinned
-         * when i915 alloc request. That is because gvt will update the guest
-         * context from shadow context when workload is completed, and at that
-         * moment, i915 may already unpined the shadow context to make the
-         * shadow_ctx pages invalid. So gvt need to pin itself. After update
-         * the guest context, gvt can unpin the shadow_ctx safely.
-         */
-        ring = engine->context_pin(engine, shadow_ctx);
-        if (IS_ERR(ring)) {
-                ret = PTR_ERR(ring);
-                gvt_vgpu_err("fail to pin shadow context\n");
-                goto out;
+                }
         }
 
 out:
@@ -408,7 +454,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
                         return;
                 }
 
-                page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
+                page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
                 src = kmap(page);
                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
                                 GTT_PAGE_SIZE);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 0d431a968a32..f36b85fd6d01 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -140,4 +140,5 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
 
 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
 
+void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
 #endif
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e4d4b6b41e26..b4a6ac60e7c6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -67,7 +67,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
 #undef PRINT_FLAG
 
         kernel_param_lock(THIS_MODULE);
-#define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x);
+#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
         I915_PARAMS_FOR_EACH(PRINT_PARAM);
 #undef PRINT_PARAM
         kernel_param_unlock(THIS_MODULE);
@@ -1267,7 +1267,7 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
                 seq_puts(m, "struct_mutex blocked for reset\n");
 
-        if (!i915.enable_hangcheck) {
+        if (!i915_modparams.enable_hangcheck) {
                 seq_puts(m, "Hangcheck disabled\n");
                 return 0;
         }
@@ -1422,6 +1422,9 @@ static int i915_forcewake_domains(struct seq_file *m, void *data)
         struct intel_uncore_forcewake_domain *fw_domain;
         unsigned int tmp;
 
+        seq_printf(m, "user.bypass_count = %u\n",
+                   i915->uncore.user_forcewake.count);
+
         for_each_fw_domain(fw_domain, i915, tmp)
                 seq_printf(m, "%s.wake_count = %u\n",
                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
@@ -1699,7 +1702,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
         intel_runtime_pm_get(dev_priv);
 
         seq_printf(m, "Enabled by kernel parameter: %s\n",
-                   yesno(i915.enable_ips));
+                   yesno(i915_modparams.enable_ips));
 
         if (INTEL_GEN(dev_priv) >= 8) {
                 seq_puts(m, "Currently: unknown\n");
@@ -2014,7 +2017,7 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
         enum intel_engine_id id;
         int ret;
 
-        if (!i915.enable_execlists) {
+        if (!i915_modparams.enable_execlists) {
                 seq_printf(m, "Logical Ring Contexts are disabled\n");
                 return 0;
         }
@@ -2443,12 +2446,8 @@ static void i915_guc_client_info(struct seq_file *m,
 
         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
                 client->priority, client->stage_id, client->proc_desc_offset);
-        seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
-                client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
-        seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
-                client->wq_size, client->wq_offset, client->wq_tail);
-
-        seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
+        seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
+                client->doorbell_id, client->doorbell_offset);
 
         for_each_engine(engine, dev_priv, id) {
                 u64 submissions = client->submissions[id];
@@ -2594,7 +2593,7 @@ static int i915_guc_log_control_get(void *data, u64 *val)
         if (!dev_priv->guc.log.vma)
                 return -EINVAL;
 
-        *val = i915.guc_log_level;
+        *val = i915_modparams.guc_log_level;
 
         return 0;
 }
@@ -3312,7 +3311,9 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
                            upper_32_bits(addr), lower_32_bits(addr));
 
-                if (i915.enable_execlists) {
+                if (i915_modparams.enable_execlists) {
+                        const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+                        struct intel_engine_execlists * const execlists = &engine->execlists;
                         u32 ptr, read, write;
                         unsigned int idx;
 
@@ -3323,8 +3324,10 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
                         read = GEN8_CSB_READ_PTR(ptr);
                         write = GEN8_CSB_WRITE_PTR(ptr);
-                        seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n",
-                                   read, write,
+                        seq_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
+                                   read, execlists->csb_head,
+                                   write,
+                                   intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
                                    yesno(test_bit(ENGINE_IRQ_EXECLIST,
                                                   &engine->irq_posted)));
                         if (read >= GEN8_CSB_ENTRIES)
@@ -3335,18 +3338,19 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                                 write += GEN8_CSB_ENTRIES;
                         while (read < write) {
                                 idx = ++read % GEN8_CSB_ENTRIES;
-                                seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
+                                seq_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
                                            idx,
                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
-                                           I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+                                           hws[idx * 2],
+                                           I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
+                                           hws[idx * 2 + 1]);
                         }
 
                         rcu_read_lock();
-                        for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); idx++) {
+                        for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
                                 unsigned int count;
 
-                                rq = port_unpack(&engine->execlist_port[idx],
-                                                 &count);
+                                rq = port_unpack(&execlists->port[idx], &count);
                                 if (rq) {
                                         seq_printf(m, "\t\tELSP[%d] count=%d, ",
                                                    idx, count);
@@ -3359,7 +3363,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                         rcu_read_unlock();
 
                         spin_lock_irq(&engine->timeline->lock);
-                        for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+                        for (rb = execlists->first; rb; rb = rb_next(rb)) {
                                 struct i915_priolist *p =
                                         rb_entry(rb, typeof(*p), node);
 
@@ -3403,7 +3407,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
         enum intel_engine_id id;
         int j, ret;
 
-        if (!i915.semaphores) {
+        if (!i915_modparams.semaphores) {
                 seq_puts(m, "Semaphores are disabled\n");
                 return 0;
         }
@@ -3523,6 +3527,57 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
         return 0;
 }
 
+static int i915_ipc_status_show(struct seq_file *m, void *data)
+{
+        struct drm_i915_private *dev_priv = m->private;
+
+        seq_printf(m, "Isochronous Priority Control: %s\n",
+                        yesno(dev_priv->ipc_enabled));
+        return 0;
+}
+
+static int i915_ipc_status_open(struct inode *inode, struct file *file)
+{
+        struct drm_i915_private *dev_priv = inode->i_private;
+
+        if (!HAS_IPC(dev_priv))
+                return -ENODEV;
+
+        return single_open(file, i915_ipc_status_show, dev_priv);
+}
+
+static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
+                                     size_t len, loff_t *offp)
+{
+        struct seq_file *m = file->private_data;
+        struct drm_i915_private *dev_priv = m->private;
+        int ret;
+        bool enable;
+
+        ret = kstrtobool_from_user(ubuf, len, &enable);
+        if (ret < 0)
+                return ret;
+
+        intel_runtime_pm_get(dev_priv);
+        if (!dev_priv->ipc_enabled && enable)
+                DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
+        dev_priv->wm.distrust_bios_wm = true;
+        dev_priv->ipc_enabled = enable;
+        intel_enable_ipc(dev_priv);
+        intel_runtime_pm_put(dev_priv);
+
+        return len;
+}
+
+static const struct file_operations i915_ipc_status_fops = {
+        .owner = THIS_MODULE,
+        .open = i915_ipc_status_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+        .write = i915_ipc_status_write
+};
+
 static int i915_ddb_info(struct seq_file *m, void *unused)
 {
         struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4674,26 +4729,26 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 
 static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
-        struct drm_i915_private *dev_priv = inode->i_private;
+        struct drm_i915_private *i915 = inode->i_private;
 
-        if (INTEL_GEN(dev_priv) < 6)
+        if (INTEL_GEN(i915) < 6)
                 return 0;
 
-        intel_runtime_pm_get(dev_priv);
-        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+        intel_runtime_pm_get(i915);
+        intel_uncore_forcewake_user_get(i915);
 
         return 0;
 }
 
 static int i915_forcewake_release(struct inode *inode, struct file *file)
 {
-        struct drm_i915_private *dev_priv = inode->i_private;
+        struct drm_i915_private *i915 = inode->i_private;
 
-        if (INTEL_GEN(dev_priv) < 6)
+        if (INTEL_GEN(i915) < 6)
                 return 0;
 
-        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
-        intel_runtime_pm_put(dev_priv);
+        intel_uncore_forcewake_user_put(i915);
+        intel_runtime_pm_put(i915);
 
         return 0;
 }
@@ -4859,7 +4914,8 @@ static const struct i915_debugfs_files {
         {"i915_dp_test_type", &i915_displayport_test_type_fops},
         {"i915_dp_test_active", &i915_displayport_test_active_fops},
         {"i915_guc_log_control", &i915_guc_log_control_fops},
-        {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
+        {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
+        {"i915_ipc_status", &i915_ipc_status_fops}
 };
 
 int i915_debugfs_register(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff70fc45ba7c..59ac9199b35d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -58,12 +58,12 @@ static unsigned int i915_load_fail_count;
 
 bool __i915_inject_load_failure(const char *func, int line)
 {
-        if (i915_load_fail_count >= i915.inject_load_failure)
+        if (i915_load_fail_count >= i915_modparams.inject_load_failure)
                 return false;
 
-        if (++i915_load_fail_count == i915.inject_load_failure) {
+        if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
-                         i915.inject_load_failure, func, line);
+                         i915_modparams.inject_load_failure, func, line);
                 return true;
         }
 
@@ -106,8 +106,8 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level,
 
 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 {
-        return i915.inject_load_failure &&
-               i915_load_fail_count == i915.inject_load_failure;
+        return i915_modparams.inject_load_failure &&
+               i915_load_fail_count == i915_modparams.inject_load_failure;
 }
 
 #define i915_load_error(dev_priv, fmt, ...)                                  \
@@ -321,7 +321,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
                 value = USES_PPGTT(dev_priv);
                 break;
         case I915_PARAM_HAS_SEMAPHORES:
-                value = i915.semaphores;
+                value = i915_modparams.semaphores;
                 break;
         case I915_PARAM_HAS_SECURE_BATCHES:
                 value = capable(CAP_SYS_ADMIN);
@@ -340,7 +340,8 @@ static int i915_getparam(struct drm_device *dev, void *data,
                         return -ENODEV;
                 break;
         case I915_PARAM_HAS_GPU_RESET:
-                value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
+                value = i915_modparams.enable_hangcheck &&
+                        intel_has_gpu_reset(dev_priv);
                 if (value && intel_has_reset_engine(dev_priv))
                         value = 2;
                 break;
@@ -869,6 +870,10 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
         memcpy(device_info, match_info, sizeof(*device_info));
         device_info->device_id = dev_priv->drm.pdev->device;
 
+        BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+                     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+        device_info->platform_mask = BIT(device_info->platform);
+
         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
         device_info->gen_mask = BIT(device_info->gen - 1);
 
@@ -1031,9 +1036,9 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 
 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 {
-        i915.enable_execlists =
+        i915_modparams.enable_execlists =
                 intel_sanitize_enable_execlists(dev_priv,
-                                                i915.enable_execlists);
+                                                i915_modparams.enable_execlists);
 
         /*
          * i915.enable_ppgtt is read-only, so do an early pass to validate the
@@ -1041,12 +1046,15 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
          * do this now so that we can print out any log messages once rather
          * than every time we check intel_enable_ppgtt().
          */
-        i915.enable_ppgtt =
-                intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
-        DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
+        i915_modparams.enable_ppgtt =
+                intel_sanitize_enable_ppgtt(dev_priv,
+                                            i915_modparams.enable_ppgtt);
+        DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-        i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
-        DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
+        i915_modparams.semaphores =
+                intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
+        DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
+                         yesno(i915_modparams.semaphores));
 
         intel_uc_sanitize_options(dev_priv);
 
@@ -1277,7 +1285,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
         int ret;
 
         /* Enable nuclear pageflip on ILK+ */
-        if (!i915.nuclear_pageflip && match_info->gen < 5)
+        if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
                 driver.driver_features &= ~DRIVER_ATOMIC;
 
         ret = -ENOMEM;
@@ -1341,7 +1349,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         intel_runtime_pm_enable(dev_priv);
 
-        dev_priv->ipc_enabled = false;
+        intel_init_ipc(dev_priv);
 
         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
                 DRM_INFO("DRM_I915_DEBUG enabled\n");
@@ -2609,6 +2617,8 @@ static int intel_runtime_resume(struct device *kdev)
         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
                 intel_hpd_init(dev_priv);
 
+        intel_enable_ipc(dev_priv);
+
         enable_rpm_wakeref_asserts(dev_priv);
 
         if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b1fa81348ee9..7ca11318ac69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -80,8 +80,8 @@
 
 #define DRIVER_NAME             "i915"
 #define DRIVER_DESC             "Intel Graphics"
-#define DRIVER_DATE             "20170907"
-#define DRIVER_TIMESTAMP        1504772900
+#define DRIVER_DATE             "20170929"
+#define DRIVER_TIMESTAMP        1506682238
 
 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
@@ -93,7 +93,7 @@
 #define I915_STATE_WARN(condition, format...) ({                        \
         int __ret_warn_on = !!(condition);                              \
         if (unlikely(__ret_warn_on))                                    \
-                if (!WARN(i915.verbose_state_checks, format))           \
+                if (!WARN(i915_modparams.verbose_state_checks, format)) \
                         DRM_ERROR(format);                              \
         unlikely(__ret_warn_on);                                        \
 })
@@ -126,7 +126,7 @@ static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
 {
         uint_fixed_16_16_t fp;
 
-        WARN_ON(val >> 16);
+        WARN_ON(val > U16_MAX);
 
         fp.val = val << 16;
         return fp;
@@ -163,8 +163,8 @@ static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
 {
         uint_fixed_16_16_t fp;
-        WARN_ON(val >> 32);
-        fp.val = clamp_t(uint32_t, val, 0, ~0);
+        WARN_ON(val > U32_MAX);
+        fp.val = (uint32_t) val;
         return fp;
 }
 
@@ -181,8 +181,8 @@ static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
 
         intermediate_val = (uint64_t) val * mul.val;
         intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
-        WARN_ON(intermediate_val >> 32);
-        return clamp_t(uint32_t, intermediate_val, 0, ~0);
+        WARN_ON(intermediate_val > U32_MAX);
+        return (uint32_t) intermediate_val;
 }
 
 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
@@ -211,8 +211,8 @@ static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
 
         interm_val = (uint64_t)val << 16;
         interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
-        WARN_ON(interm_val >> 32);
-        return clamp_t(uint32_t, interm_val, 0, ~0);
+        WARN_ON(interm_val > U32_MAX);
+        return (uint32_t) interm_val;
 }
 
 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
@@ -776,7 +776,6 @@ struct intel_csr {
         func(has_fpga_dbg); \
         func(has_full_ppgtt); \
         func(has_full_48bit_ppgtt); \
-        func(has_gmbus_irq); \
         func(has_gmch_display); \
         func(has_guc); \
         func(has_guc_ct); \
@@ -797,7 +796,8 @@ struct intel_csr {
         func(cursor_needs_physical); \
         func(hws_needs_physical); \
         func(overlay_needs_physical); \
-        func(supports_tv);
+        func(supports_tv); \
+        func(has_ipc);
 
 struct sseu_dev_info {
         u8 slice_mask;
@@ -851,21 +851,28 @@ enum intel_platform {
 };
 
 struct intel_device_info {
-        u32 display_mmio_offset;
         u16 device_id;
-        u8 num_pipes;
-        u8 num_sprites[I915_MAX_PIPES];
-        u8 num_scalers[I915_MAX_PIPES];
-        u8 gen;
         u16 gen_mask;
-        enum intel_platform platform;
+
+        u8 gen;
         u8 gt; /* GT number, 0 if undefined */
-        u8 ring_mask; /* Rings supported by the HW */
         u8 num_rings;
+        u8 ring_mask; /* Rings supported by the HW */
+
+        enum intel_platform platform;
+        u32 platform_mask;
+
+        u32 display_mmio_offset;
+
+        u8 num_pipes;
+        u8 num_sprites[I915_MAX_PIPES];
+        u8 num_scalers[I915_MAX_PIPES];
+
 #define DEFINE_FLAG(name) u8 name:1
         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
         u16 ddb_size; /* in blocks */
+
         /* Register offsets for the various display pipes and transcoders */
         int pipe_offsets[I915_MAX_TRANSCODERS];
         int trans_offsets[I915_MAX_TRANSCODERS];
@@ -1000,7 +1007,8 @@ struct i915_gpu_state {
                         u32 seqno;
                         u32 head;
                         u32 tail;
-                } *requests, execlist[2];
+                } *requests, execlist[EXECLIST_MAX_PORTS];
+                unsigned int num_ports;
 
                 struct drm_i915_error_waiter {
                         char comm[TASK_COMM_LEN];
@@ -1178,6 +1186,14 @@ struct i915_psr {
         bool y_cord_support;
         bool colorimetry_support;
         bool alpm;
+
+        void (*enable_source)(struct intel_dp *,
+                              const struct intel_crtc_state *);
+        void (*disable_source)(struct intel_dp *,
+                               const struct intel_crtc_state *);
+        void (*enable_sink)(struct intel_dp *);
+        void (*activate)(struct intel_dp *);
+        void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
 };
 
 enum intel_pch {
@@ -1836,6 +1852,20 @@ struct skl_wm_level {
         uint8_t plane_res_l;
 };
 
+/* Stores plane specific WM parameters */
+struct skl_wm_params {
+        bool x_tiled, y_tiled;
+        bool rc_surface;
+        uint32_t width;
+        uint8_t cpp;
+        uint32_t plane_pixel_rate;
+        uint32_t y_min_scanlines;
+        uint32_t plane_bytes_per_line;
+        uint_fixed_16_16_t plane_blocks_per_line;
+        uint_fixed_16_16_t y_tile_minimum;
+        uint32_t linetime_us;
+};
+
 /*
  * This struct helps tracking the state needed for runtime PM, which puts the
  * device in PCI D3 state. Notice that when this happens, nothing on the
@@ -2331,6 +2361,8 @@ struct drm_i915_private {
         DECLARE_HASHTABLE(mm_structs, 7);
         struct mutex mm_lock;
 
+        struct intel_ppat ppat;
+
         /* Kernel Modesetting */
 
         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
@@ -2811,8 +2843,8 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
              ((__dmap) = (__iter).dma + (__iter).curr);                 \
-             (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
-             ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
+             (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?           \
+             (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
 
 /**
  * for_each_sgt_page - iterate over the pages of the given sg_table
@@ -2824,8 +2856,23 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
-             (((__iter).curr += PAGE_SIZE) < (__iter).max) ||           \
-             ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
+             (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?           \
+             (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
+
+static inline unsigned int i915_sg_segment_size(void)
+{
+        unsigned int size = swiotlb_max_segment();
+
+        if (size == 0)
+                return SCATTERLIST_MAX_SEGMENT;
+
+        size = rounddown(size, PAGE_SIZE);
+        /* swiotlb_max_segment_size can return 1 byte when it means one page. */
+        if (size < PAGE_SIZE)
+                size = PAGE_SIZE;
+
+        return size;
+}
 
 static inline const struct intel_device_info *
 intel_info(const struct drm_i915_private *dev_priv)
@@ -2842,23 +2889,21 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
 
 #define GEN_FOREVER (0)
+
+#define INTEL_GEN_MASK(s, e) ( \
+        BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
+        BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
+        GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
+                (s) != GEN_FOREVER ? (s) - 1 : 0) \
+)
+
 /*
  * Returns true if Gen is in inclusive range [Start, End].
  *
  * Use GEN_FOREVER for unbound start and or end.
  */
-#define IS_GEN(dev_priv, s, e) ({ \
-        unsigned int __s = (s), __e = (e); \
-        BUILD_BUG_ON(!__builtin_constant_p(s)); \
-        BUILD_BUG_ON(!__builtin_constant_p(e)); \
-        if ((__s) != GEN_FOREVER) \
-                __s = (s) - 1; \
-        if ((__e) == GEN_FOREVER) \
-                __e = BITS_PER_LONG - 1; \
-        else \
-                __e = (e) - 1; \
-        !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
-})
+#define IS_GEN(dev_priv, s, e) \
+        (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
 
 /*
  * Return true if revision is in range [since,until] inclusive.
@@ -2868,37 +2913,39 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_REVID(p, since, until) \
         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_I830(dev_priv)       ((dev_priv)->info.platform == INTEL_I830)
-#define IS_I845G(dev_priv)      ((dev_priv)->info.platform == INTEL_I845G)
-#define IS_I85X(dev_priv)       ((dev_priv)->info.platform == INTEL_I85X)
-#define IS_I865G(dev_priv)      ((dev_priv)->info.platform == INTEL_I865G)
-#define IS_I915G(dev_priv)      ((dev_priv)->info.platform == INTEL_I915G)
-#define IS_I915GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I915GM)
-#define IS_I945G(dev_priv)      ((dev_priv)->info.platform == INTEL_I945G)
-#define IS_I945GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I945GM)
-#define IS_I965G(dev_priv)      ((dev_priv)->info.platform == INTEL_I965G)
-#define IS_I965GM(dev_priv)     ((dev_priv)->info.platform == INTEL_I965GM)
-#define IS_G45(dev_priv)        ((dev_priv)->info.platform == INTEL_G45)
-#define IS_GM45(dev_priv)       ((dev_priv)->info.platform == INTEL_GM45)
+#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+
+#define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
+#define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
+#define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
+#define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
+#define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
+#define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
+#define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
+#define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
+#define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
+#define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
+#define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
+#define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv)   ((dev_priv)->info.platform == INTEL_PINEVIEW)
-#define IS_G33(dev_priv)        ((dev_priv)->info.platform == INTEL_G33)
+#define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
+#define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev_priv)  ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
+#define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
                                  (dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
-#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)    ((dev_priv)->info.platform == INTEL_HASWELL)
-#define IS_BROADWELL(dev_priv)  ((dev_priv)->info.platform == INTEL_BROADWELL)
-#define IS_SKYLAKE(dev_priv)    ((dev_priv)->info.platform == INTEL_SKYLAKE)
-#define IS_BROXTON(dev_priv)    ((dev_priv)->info.platform == INTEL_BROXTON)
-#define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.platform == INTEL_KABYLAKE)
-#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
-#define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
-#define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
+#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
+#define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
+#define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
+#define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
+#define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
+#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
+#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_MOBILE(dev_priv)     ((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2946,6 +2993,8 @@ intel_info(const struct drm_i915_private *dev_priv)
                                  (dev_priv)->info.gt == 3)
 #define IS_CFL_ULT(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
+                                 (dev_priv)->info.gt == 2)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
@@ -3036,9 +3085,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
                 ((dev_priv)->info.has_logical_ring_contexts)
-#define USES_PPGTT(dev_priv)            (i915.enable_ppgtt)
-#define USES_FULL_PPGTT(dev_priv)       (i915.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
+#define USES_PPGTT(dev_priv)            (i915_modparams.enable_ppgtt)
+#define USES_FULL_PPGTT(dev_priv)       (i915_modparams.enable_ppgtt >= 2)
+#define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
 
 #define HAS_OVERLAY(dev_priv)            ((dev_priv)->info.has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
@@ -3056,9 +3105,12 @@ intel_info(const struct drm_i915_private *dev_priv)
  * even when in MSI mode. This results in spurious interrupt warnings if the
  * legacy irq no. is shared with another device. The kernel then disables that
  * interrupt source and so prevents the other device from working properly.
+ *
+ * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
+ * interrupts.
  */
-#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
-#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
+#define HAS_AUX_IRQ(dev_priv)   true
+#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
@@ -3089,6 +3141,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
 
+#define HAS_IPC(dev_priv)                ((dev_priv)->info.has_ipc)
+
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
  * command submission once loaded. But these are logically independent
@@ -3234,7 +3288,7 @@ static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
 {
         unsigned long delay;
 
-        if (unlikely(!i915.enable_hangcheck))
+        if (unlikely(!i915_modparams.enable_hangcheck))
                 return;
 
         /* Don't continually defer the hangcheck so that it is always run at
@@ -3267,6 +3321,8 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
         return dev_priv->vgpu.active;
 }
 
+u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
+                              enum pipe pipe);
 void
 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
                      u32 status_mask);
@@ -4360,4 +4416,12 @@ int remap_io_mapping(struct vm_area_struct *vma,
                      unsigned long addr, unsigned long pfn, unsigned long size,
                      struct io_mapping *iomap);
 
+static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
+{
+        if (INTEL_GEN(i915) >= 10)
+                return CNL_HWS_CSB_WRITE_INDEX;
+        else
+                return I915_HWS_CSB_WRITE_INDEX;
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8f074c7f6253..73eeb6b1f1cd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -179,7 +179,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
          * the alignment of the buddy allocation will naturally match.
          */
         phys = drm_pci_alloc(obj->base.dev,
-                             obj->base.size,
+                             roundup_pow_of_two(obj->base.size),
                              roundup_pow_of_two(obj->base.size));
         if (!phys)
                 return ERR_PTR(-ENOMEM);
@@ -694,10 +694,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
 
         switch (obj->base.write_domain) {
         case I915_GEM_DOMAIN_GTT:
-                if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
+                if (!HAS_LLC(dev_priv)) {
                         intel_runtime_pm_get(dev_priv);
                         spin_lock_irq(&dev_priv->uncore.lock);
-                        POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+                        POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
                         spin_unlock_irq(&dev_priv->uncore.lock);
                         intel_runtime_pm_put(dev_priv);
                 }
@@ -2303,7 +2303,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
         struct sgt_iter sgt_iter;
         struct page *page;
         unsigned long last_pfn = 0;     /* suppress gcc warning */
-        unsigned int max_segment;
+        unsigned int max_segment = i915_sg_segment_size();
         gfp_t noreclaim;
         int ret;
 
@@ -2314,10 +2314,6 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
         GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
         GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
 
-        max_segment = swiotlb_max_segment();
-        if (!max_segment)
-                max_segment = rounddown(UINT_MAX, PAGE_SIZE);
-
         st = kmalloc(sizeof(*st), GFP_KERNEL);
         if (st == NULL)
                 return ERR_PTR(-ENOMEM);
@@ -2819,8 +2815,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
          * Turning off the engine->irq_tasklet until the reset is over
          * prevents the race.
          */
-        tasklet_kill(&engine->irq_tasklet);
-        tasklet_disable(&engine->irq_tasklet);
+        tasklet_kill(&engine->execlists.irq_tasklet);
+        tasklet_disable(&engine->execlists.irq_tasklet);
 
         if (engine->irq_seqno_barrier)
                 engine->irq_seqno_barrier(engine);
@@ -2999,7 +2995,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
 {
-        tasklet_enable(&engine->irq_tasklet);
+        tasklet_enable(&engine->execlists.irq_tasklet);
         kthread_unpark(engine->breadcrumbs.signaler);
 }
 
@@ -3026,9 +3022,6 @@ static void nop_submit_request(struct drm_i915_gem_request *request)
 
 static void engine_set_wedged(struct intel_engine_cs *engine)
 {
-        struct drm_i915_gem_request *request;
-        unsigned long flags;
-
         /* We need to be sure that no thread is running the old callback as
          * we install the nop handler (otherwise we would submit a request
          * to hardware that will never complete). In order to prevent this
@@ -3038,40 +3031,7 @@ static void engine_set_wedged(struct intel_engine_cs *engine)
         engine->submit_request = nop_submit_request;
 
         /* Mark all executing requests as skipped */
-        spin_lock_irqsave(&engine->timeline->lock, flags);
-        list_for_each_entry(request, &engine->timeline->requests, link)
-                if (!i915_gem_request_completed(request))
-                        dma_fence_set_error(&request->fence, -EIO);
-        spin_unlock_irqrestore(&engine->timeline->lock, flags);
-
-        /*
-         * Clear the execlists queue up before freeing the requests, as those
-         * are the ones that keep the context and ringbuffer backing objects
-         * pinned in place.
-         */
-
-        if (i915.enable_execlists) {
-                struct execlist_port *port = engine->execlist_port;
-                unsigned long flags;
-                unsigned int n;
-
-                spin_lock_irqsave(&engine->timeline->lock, flags);
-
-                for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
-                        i915_gem_request_put(port_request(&port[n]));
-                memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
-                engine->execlist_queue = RB_ROOT;
-                engine->execlist_first = NULL;
-
-                spin_unlock_irqrestore(&engine->timeline->lock, flags);
-
-                /* The port is checked prior to scheduling a tasklet, but
-                 * just in case we have suspended the tasklet to do the
-                 * wedging make sure that when it wakes, it decides there
-                 * is no work to do by clearing the irq_posted bit.
-                 */
-                clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-        }
+        engine->cancel_requests(engine);
 
         /* Mark all pending requests as complete so that any concurrent
          * (lockless) lookup doesn't try and wait upon the request as we
@@ -4778,7 +4738,7 @@ bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
                 return false;
 
         /* TODO: make semaphores and Execlists play nicely together */
-        if (i915.enable_execlists)
+        if (i915_modparams.enable_execlists)
                 return false;
 
         if (value >= 0)
@@ -4799,7 +4759,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 
         dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
 
-        if (!i915.enable_execlists) {
+        if (!i915_modparams.enable_execlists) {
                 dev_priv->gt.resume = intel_legacy_submission_resume;
                 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
         } else {
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 58a2a44f88bd..921ee369c74d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
          * present or not in use we still need a small bias as ring wraparound
          * at offset 0 sometimes hangs. No idea why.
          */
-        if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
+        if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
                 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
         else
                 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
@@ -407,7 +407,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
         i915_gem_context_set_closed(ctx); /* not user accessible */
         i915_gem_context_clear_bannable(ctx);
         i915_gem_context_set_force_single_submission(ctx);
-        if (!i915.enable_guc_submission)
+        if (!i915_modparams.enable_guc_submission)
                 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
 
         GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
@@ -431,7 +431,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 
         if (intel_vgpu_active(dev_priv) &&
             HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
-                if (!i915.enable_execlists) {
+                if (!i915_modparams.enable_execlists) {
                         DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
                         return -EINVAL;
                 }
@@ -483,7 +483,7 @@ void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
         }
 
         /* Force the GPU state to be restored on enabling */
-        if (!i915.enable_execlists) {
+        if (!i915_modparams.enable_execlists) {
                 struct i915_gem_context *ctx;
 
                 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
@@ -568,7 +568,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
         enum intel_engine_id id;
         const int num_rings =
                 /* Use an extended w/a on gen7 if signalling from other rings */
-                (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
+                (i915_modparams.semaphores && INTEL_GEN(dev_priv) == 7) ?
                 INTEL_INFO(dev_priv)->num_rings - 1 :
                 0;
         int len;
@@ -837,7 +837,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
         struct intel_engine_cs *engine = req->engine;
 
         lockdep_assert_held(&req->i915->drm.struct_mutex);
-        if (i915.enable_execlists)
+        if (i915_modparams.enable_execlists)
                 return 0;
 
         if (!req->ctx->engine[engine->id].state) {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index ca0eab343644..d733c4d5a500 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -58,6 +58,7 @@ enum {
 
 #define __EXEC_HAS_RELOC        BIT(31)
 #define __EXEC_VALIDATED        BIT(30)
+#define __EXEC_INTERNAL_FLAGS   (~0u << 30)
 #define UPDATE                  PIN_OFFSET_FIXED
 
 #define BATCH_OFFSET_BIAS (256*1024)
@@ -679,7 +680,7 @@ static int eb_select_context(struct i915_execbuffer *eb)
 static int eb_lookup_vmas(struct i915_execbuffer *eb)
 {
         struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
-        struct drm_i915_gem_object *uninitialized_var(obj);
+        struct drm_i915_gem_object *obj;
         unsigned int i;
         int err;
 
@@ -725,19 +726,17 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
                         goto err_obj;
                 }
 
+                /* transfer ref to ctx */
                 vma->open_count++;
                 list_add(&lut->obj_link, &obj->lut_list);
                 list_add(&lut->ctx_link, &eb->ctx->handles_list);
                 lut->ctx = eb->ctx;
                 lut->handle = handle;
 
-                /* transfer ref to ctx */
-                obj = NULL;
-
 add_vma:
                 err = eb_add_vma(eb, i, vma);
                 if (unlikely(err))
-                        goto err_obj;
+                        goto err_vma;
 
                 GEM_BUG_ON(vma != eb->vma[i]);
                 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
@@ -766,8 +765,7 @@ add_vma:
         return eb_reserve(eb);
 
 err_obj:
-        if (obj)
-                i915_gem_object_put(obj);
+        i915_gem_object_put(obj);
 err_vma:
         eb->vma[i] = NULL;
         return err;
@@ -1587,7 +1585,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb)
         const unsigned int count = eb->buffer_count;
         unsigned int i;
 
-        if (unlikely(i915.prefault_disable))
+        if (unlikely(i915_modparams.prefault_disable))
                 return 0;
 
         for (i = 0; i < count; i++) {
@@ -2188,6 +2186,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
         int out_fence_fd = -1;
         int err;
 
+        BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
         BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
                      ~__EXEC_OBJECT_UNKNOWN_FLAGS);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 40d446ba0b85..4c82ceb8d318 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -180,7 +180,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
                 return 0;
         }
 
-        if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
+        if (INTEL_GEN(dev_priv) >= 8 && i915_modparams.enable_execlists) {
                 if (has_full_48bit_ppgtt)
                         return 3;
 
@@ -230,13 +230,13 @@ static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 
         switch (level) {
         case I915_CACHE_NONE:
-                pte |= PPAT_UNCACHED_INDEX;
+                pte |= PPAT_UNCACHED;
                 break;
         case I915_CACHE_WT:
-                pte |= PPAT_DISPLAY_ELLC_INDEX;
+                pte |= PPAT_DISPLAY_ELLC;
                 break;
         default:
-                pte |= PPAT_CACHED_INDEX;
+                pte |= PPAT_CACHED;
                 break;
         }
 
@@ -249,9 +249,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
         pde |= addr;
         if (level != I915_CACHE_NONE)
-                pde |= PPAT_CACHED_PDE_INDEX;
+                pde |= PPAT_CACHED_PDE;
         else
-                pde |= PPAT_UNCACHED_INDEX;
+                pde |= PPAT_UNCACHED;
         return pde;
 }
 
@@ -481,10 +481,8 @@ static void fill_page_dma(struct i915_address_space *vm,
                           const u64 val)
 {
         u64 * const vaddr = kmap_atomic(p->page);
-        int i;
 
-        for (i = 0; i < 512; i++)
-                vaddr[i] = val;
+        memset64(vaddr, val, PAGE_SIZE / sizeof(val));
 
         kunmap_atomic(vaddr);
 }
@@ -1168,19 +1166,22 @@ static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
         unsigned int pde;
 
         gen8_for_each_pde(pt, pd, start, length, pde) {
+                int count = gen8_pte_count(start, length);
+
                 if (pt == vm->scratch_pt) {
                         pt = alloc_pt(vm);
                         if (IS_ERR(pt))
                                 goto unwind;
 
-                        gen8_initialize_pt(vm, pt);
+                        if (count < GEN8_PTES)
+                                gen8_initialize_pt(vm, pt);
 
                         gen8_ppgtt_set_pde(vm, pd, pt, pde);
                         pd->used_pdes++;
                         GEM_BUG_ON(pd->used_pdes > I915_PDES);
                 }
 
-                pt->used_ptes += gen8_pte_count(start, length);
+                pt->used_ptes += count;
         }
         return 0;
 
@@ -1969,7 +1970,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
         /* In the case of execlists, PPGTT is enabled by the context descriptor
          * and the PDPs are contained within the context itself.  We don't
          * need to do anything here. */
-        if (i915.enable_execlists)
+        if (i915_modparams.enable_execlists)
                 return 0;
 
         if (!USES_PPGTT(dev_priv))
@@ -2816,41 +2817,209 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
         return 0;
 }
 
-static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+static struct intel_ppat_entry *
+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
+{
+        struct intel_ppat_entry *entry = &ppat->entries[index];
+
+        GEM_BUG_ON(index >= ppat->max_entries);
+        GEM_BUG_ON(test_bit(index, ppat->used));
+
+        entry->ppat = ppat;
+        entry->value = value;
+        kref_init(&entry->ref);
+        set_bit(index, ppat->used);
+        set_bit(index, ppat->dirty);
+
+        return entry;
+}
+
+static void __free_ppat_entry(struct intel_ppat_entry *entry)
+{
+        struct intel_ppat *ppat = entry->ppat;
+        unsigned int index = entry - ppat->entries;
+
+        GEM_BUG_ON(index >= ppat->max_entries);
+        GEM_BUG_ON(!test_bit(index, ppat->used));
+
+        entry->value = ppat->clear_value;
+        clear_bit(index, ppat->used);
+        set_bit(index, ppat->dirty);
+}
+
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @i915: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, the partially
+ * matched entry will be used.
+ */
+const struct intel_ppat_entry *
+intel_ppat_get(struct drm_i915_private *i915, u8 value)
 {
+        struct intel_ppat *ppat = &i915->ppat;
+        struct intel_ppat_entry *entry;
+        unsigned int scanned, best_score;
+        int i;
+
+        GEM_BUG_ON(!ppat->max_entries);
+
+        scanned = best_score = 0;
+        for_each_set_bit(i, ppat->used, ppat->max_entries) {
+                unsigned int score;
+
+                score = ppat->match(ppat->entries[i].value, value);
+                if (score > best_score) {
+                        entry = &ppat->entries[i];
+                        if (score == INTEL_PPAT_PERFECT_MATCH) {
+                                kref_get(&entry->ref);
+                                return entry;
+                        }
+                        best_score = score;
+                }
+                scanned++;
+        }
+
+        if (scanned == ppat->max_entries) {
+                if (!best_score)
+                        return ERR_PTR(-ENOSPC);
+
+                kref_get(&entry->ref);
+                return entry;
+        }
+
+        i = find_first_zero_bit(ppat->used, ppat->max_entries);
+        entry = __alloc_ppat_entry(ppat, i, value);
+        ppat->update_hw(i915);
+        return entry;
+}
+
+static void release_ppat(struct kref *kref)
+{
+        struct intel_ppat_entry *entry =
+                container_of(kref, struct intel_ppat_entry, ref);
+        struct drm_i915_private *i915 = entry->ppat->i915;
+
+        __free_ppat_entry(entry);
+        entry->ppat->update_hw(i915);
+}
+
+/**
+ * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
+ * @entry: an intel PPAT entry
+ *
+ * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
+ * entry is dynamically allocated, its reference count will be decreased. Once
+ * the reference count becomes into zero, the PPAT index becomes free again.
+ */
+void intel_ppat_put(const struct intel_ppat_entry *entry)
+{
+        struct intel_ppat *ppat = entry->ppat;
+        unsigned int index = entry - ppat->entries;
+
+        GEM_BUG_ON(!ppat->max_entries);
+
+        kref_put(&ppat->entries[index].ref, release_ppat);
+}
+
+static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
+{
+        struct intel_ppat *ppat = &dev_priv->ppat;
+        int i;
+
+        for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
+                I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
+                clear_bit(i, ppat->dirty);
+        }
+}
+
+static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
+{
+        struct intel_ppat *ppat = &dev_priv->ppat;
+        u64 pat = 0;
+        int i;
+
+        for (i = 0; i < ppat->max_entries; i++)
+                pat |= GEN8_PPAT(i, ppat->entries[i].value);
+
+        bitmap_clear(ppat->dirty, 0, ppat->max_entries);
+
+        I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
+        I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
+}
+
+static unsigned int bdw_private_pat_match(u8 src, u8 dst)
+{
+        unsigned int score = 0;
+        enum {
+                AGE_MATCH = BIT(0),
+                TC_MATCH = BIT(1),
+                CA_MATCH = BIT(2),
+        };
+
+        /* Cache attribute has to be matched. */
+        if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
+                return 0;
+
+        score |= CA_MATCH;
+
+        if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
+                score |= TC_MATCH;
+
+        if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
+                score |= AGE_MATCH;
+
+        if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
+                return INTEL_PPAT_PERFECT_MATCH;
+
+        return score;
+}
+
+static unsigned int chv_private_pat_match(u8 src, u8 dst)
+{
+        return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
+                INTEL_PPAT_PERFECT_MATCH : 0;
+}
+
+static void cnl_setup_private_ppat(struct intel_ppat *ppat)
+{
+        ppat->max_entries = 8;
+        ppat->update_hw = cnl_private_pat_update_hw;
+        ppat->match = bdw_private_pat_match;
+        ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
+
         /* XXX: spec is unclear if this is still needed for CNL+ */
-        if (!USES_PPGTT(dev_priv)) {
-                I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
+        if (!USES_PPGTT(ppat->i915)) {
+                __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
                 return;
         }
 
-        I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
-        I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-        I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-        I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
-        I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-        I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-        I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-        I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+        __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
+        __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
+        __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+        __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
+        __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+        __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+        __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+        __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
-static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
+static void bdw_setup_private_ppat(struct intel_ppat *ppat)
 {
-        u64 pat;
+        ppat->max_entries = 8;
+        ppat->update_hw = bdw_private_pat_update_hw;
+        ppat->match = bdw_private_pat_match;
+        ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
 
-        pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
-              GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
-              GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
-              GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
-              GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
-              GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
-              GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
-              GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
-
-        if (!USES_PPGTT(dev_priv))
+        if (!USES_PPGTT(ppat->i915)) {
                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
                  * so RTL will always use the value corresponding to
                  * pat_sel = 000".
@@ -2864,17 +3033,26 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
                  * So we can still hold onto all our assumptions wrt cpu
                  * clflushing on LLC machines.
                  */
-                pat = GEN8_PPAT(0, GEN8_PPAT_UC);
+                __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+                return;
+        }
 
-        /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
-         * write would work. */
-        I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-        I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+        __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
+        __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
+        __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
+        __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
+        __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+        __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+        __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+        __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
 }
 
-static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
+static void chv_setup_private_ppat(struct intel_ppat *ppat)
 {
-        u64 pat;
+        ppat->max_entries = 8;
+        ppat->update_hw = bdw_private_pat_update_hw;
+        ppat->match = chv_private_pat_match;
+        ppat->clear_value = CHV_PPAT_SNOOP;
 
         /*
          * Map WB on BDW to snooped on CHV.
@@ -2894,17 +3072,15 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
          * Which means we must set the snoop bit in PAT entry 0
          * in order to keep the global status page working.
          */
-        pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
-              GEN8_PPAT(1, 0) |
-              GEN8_PPAT(2, 0) |
-              GEN8_PPAT(3, 0) |
-              GEN8_PPAT(4, CHV_PPAT_SNOOP) |
-              GEN8_PPAT(5, CHV_PPAT_SNOOP) |
-              GEN8_PPAT(6, CHV_PPAT_SNOOP) |
-              GEN8_PPAT(7, CHV_PPAT_SNOOP);
 
-        I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-        I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+        __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
+        __alloc_ppat_entry(ppat, 1, 0);
+        __alloc_ppat_entry(ppat, 2, 0);
+        __alloc_ppat_entry(ppat, 3, 0);
+        __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
+        __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
+        __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
+        __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
 }
 
 static void gen6_gmch_remove(struct i915_address_space *vm)
@@ -2915,6 +3091,31 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
         cleanup_scratch_page(vm);
 }
 
+static void setup_private_pat(struct drm_i915_private *dev_priv)
+{
+        struct intel_ppat *ppat = &dev_priv->ppat;
+        int i;
+
+        ppat->i915 = dev_priv;
+
+        if (INTEL_GEN(dev_priv) >= 10)
+                cnl_setup_private_ppat(ppat);
+        else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+                chv_setup_private_ppat(ppat);
+        else
+                bdw_setup_private_ppat(ppat);
+
+        GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
+
+        for_each_clear_bit(i, ppat->used, ppat->max_entries) {
+                ppat->entries[i].value = ppat->clear_value;
+                ppat->entries[i].ppat = ppat;
+                set_bit(i, ppat->dirty);
+        }
+
+        ppat->update_hw(dev_priv);
+}
+
 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 {
         struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -2947,14 +3148,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
         }
 
         ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-
-        if (INTEL_GEN(dev_priv) >= 10)
-                cnl_setup_private_ppat(dev_priv);
-        else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-                chv_setup_private_ppat(dev_priv);
-        else
-                bdw_setup_private_ppat(dev_priv);
-
         ggtt->base.cleanup = gen6_gmch_remove;
         ggtt->base.bind_vma = ggtt_bind_vma;
         ggtt->base.unbind_vma = ggtt_unbind_vma;
@@ -2975,6 +3168,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
         ggtt->invalidate = gen6_ggtt_invalidate;
 
+        setup_private_pat(dev_priv);
+
         return ggtt_probe_common(ggtt, size);
 }
 
@@ -3095,7 +3290,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
          * currently don't have any bits spare to pass in this upper
          * restriction!
          */
-        if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
+        if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
                 ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
         }
@@ -3232,13 +3427,10 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
         ggtt->base.closed = false;
 
         if (INTEL_GEN(dev_priv) >= 8) {
-                if (INTEL_GEN(dev_priv) >= 10)
-                        cnl_setup_private_ppat(dev_priv);
-                else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-                        chv_setup_private_ppat(dev_priv);
-                else
-                        bdw_setup_private_ppat(dev_priv);
+                struct intel_ppat *ppat = &dev_priv->ppat;
 
+                bitmap_set(ppat->dirty, 0, ppat->max_entries);
+                dev_priv->ppat.update_hw(dev_priv);
                 return;
         }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index b4e3aa7c0ce1..f62fb903dc24 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -126,13 +126,13 @@ typedef u64 gen8_ppgtt_pml4e_t;
  * tables */
 #define GEN8_PDPE_MASK                  0x1ff
 
-#define PPAT_UNCACHED_INDEX             (_PAGE_PWT | _PAGE_PCD)
-#define PPAT_CACHED_PDE_INDEX           0 /* WB LLC */
-#define PPAT_CACHED_INDEX               _PAGE_PAT /* WB LLCeLLC */
-#define PPAT_DISPLAY_ELLC_INDEX         _PAGE_PCD /* WT eLLC */
+#define PPAT_UNCACHED                   (_PAGE_PWT | _PAGE_PCD)
+#define PPAT_CACHED_PDE                 0 /* WB LLC */
+#define PPAT_CACHED                     _PAGE_PAT /* WB LLCeLLC */
+#define PPAT_DISPLAY_ELLC               _PAGE_PCD /* WT eLLC */
 
 #define CHV_PPAT_SNOOP                  (1<<6)
-#define GEN8_PPAT_AGE(x)                (x<<4)
+#define GEN8_PPAT_AGE(x)                ((x)<<4)
 #define GEN8_PPAT_LLCeLLC               (3<<2)
 #define GEN8_PPAT_LLCELLC               (2<<2)
 #define GEN8_PPAT_LLC                   (1<<2)
@@ -143,6 +143,11 @@ typedef u64 gen8_ppgtt_pml4e_t;
 #define GEN8_PPAT_ELLC_OVERRIDE         (0<<2)
 #define GEN8_PPAT(i, x)                 ((u64)(x) << ((i) * 8))
 
+#define GEN8_PPAT_GET_CA(x) ((x) & 3)
+#define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
+#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
+#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
+
 struct sg_table;
 
 struct intel_rotation_info {
@@ -536,6 +541,37 @@ i915_vm_to_ggtt(struct i915_address_space *vm)
         return container_of(vm, struct i915_ggtt, base);
 }
 
+#define INTEL_MAX_PPAT_ENTRIES 8
+#define INTEL_PPAT_PERFECT_MATCH (~0U)
+
+struct intel_ppat;
+
+struct intel_ppat_entry {
+        struct intel_ppat *ppat;
+        struct kref ref;
+        u8 value;
+};
+
+struct intel_ppat {
+        struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
+        DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
+        DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
+        unsigned int max_entries;
+        u8 clear_value;
+        /*
+         * Return a score to show how two PPAT values match,
+         * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
+         */
+        unsigned int (*match)(u8 src, u8 dst);
+        void (*update_hw)(struct drm_i915_private *i915);
+
+        struct drm_i915_private *i915;
+};
+
+const struct intel_ppat_entry *
+intel_ppat_get(struct drm_i915_private *i915, u8 value);
+void intel_ppat_put(const struct intel_ppat_entry *entry);
+
 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 813a3b546d6e..4eb1a76731b2 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1021,12 +1021,28 @@ static bool busywait_stop(unsigned long timeout, unsigned int cpu)
         return this_cpu != cpu;
 }
 
-bool __i915_spin_request(const struct drm_i915_gem_request *req,
-                         u32 seqno, int state, unsigned long timeout_us)
+static bool __i915_spin_request(const struct drm_i915_gem_request *req,
+                                u32 seqno, int state, unsigned long timeout_us)
 {
         struct intel_engine_cs *engine = req->engine;
         unsigned int irq, cpu;
 
+        GEM_BUG_ON(!seqno);
+
+        /*
+         * Only wait for the request if we know it is likely to complete.
+         *
+         * We don't track the timestamps around requests, nor the average
+         * request length, so we do not have a good indicator that this
+         * request will complete within the timeout. What we do know is the
+         * order in which requests are executed by the engine and so we can
+         * tell if the request has started. If the request hasn't started yet,
+         * it is a fair assumption that it will not complete within our
+         * relatively short timeout.
+         */
+        if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1))
+                return false;
+
         /* When waiting for high frequency requests, e.g. during synchronous
          * rendering split between the CPU and GPU, the finite amount of time
          * required to set up the irq and wait upon it limits the response
@@ -1040,12 +1056,8 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req,
         irq = atomic_read(&engine->irq_count);
         timeout_us += local_clock_us(&cpu);
         do {
-                if (seqno != i915_gem_request_global_seqno(req))
-                        break;
-
-                if (i915_seqno_passed(intel_engine_get_seqno(req->engine),
-                                      seqno))
-                        return true;
+                if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
+                        return seqno == i915_gem_request_global_seqno(req);
 
                 /* Seqno are meant to be ordered *before* the interrupt. If
                  * we see an interrupt without a corresponding seqno advance,
@@ -1156,7 +1168,7 @@ restart:
         GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
 
         /* Optimistic short spin before touching IRQs */
-        if (i915_spin_request(req, state, 5))
+        if (__i915_spin_request(req, wait.seqno, state, 5))
                 goto complete;
 
         set_current_state(state);
@@ -1213,7 +1225,7 @@ wakeup:
                         continue;
 
                 /* Only spin if we know the GPU is processing this request */
-                if (i915_spin_request(req, state, 2))
+                if (__i915_spin_request(req, wait.seqno, state, 2))
                         break;
 
                 if (!intel_wait_check_request(&wait, req)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 49a4c8994ff0..96eb52471dad 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -313,26 +313,6 @@ static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
 }
 
 static inline bool
-__i915_gem_request_started(const struct drm_i915_gem_request *req, u32 seqno)
-{
-        GEM_BUG_ON(!seqno);
-        return i915_seqno_passed(intel_engine_get_seqno(req->engine),
-                                 seqno - 1);
-}
-
-static inline bool
-i915_gem_request_started(const struct drm_i915_gem_request *req)
-{
-        u32 seqno;
-
-        seqno = i915_gem_request_global_seqno(req);
-        if (!seqno)
-                return false;
-
-        return __i915_gem_request_started(req, seqno);
-}
-
-static inline bool
 __i915_gem_request_completed(const struct drm_i915_gem_request *req, u32 seqno)
 {
         GEM_BUG_ON(!seqno);
@@ -352,21 +332,6 @@ i915_gem_request_completed(const struct drm_i915_gem_request *req)
         return __i915_gem_request_completed(req, seqno);
 }
 
-bool __i915_spin_request(const struct drm_i915_gem_request *request,
-                         u32 seqno, int state, unsigned long timeout_us);
-static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
-                                     int state, unsigned long timeout_us)
-{
-        u32 seqno;
-
-        seqno = i915_gem_request_global_seqno(request);
-        if (!seqno)
-                return 0;
-
-        return (__i915_gem_request_started(request, seqno) &&
-                __i915_spin_request(request, seqno, state, timeout_us));
-}
-
 /* We treat requests as fences. This is not be to confused with our
  * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
  * We use the fences to synchronize access from the CPU with activity on the
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 709efe2357ea..2d4996de7331 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -399,64 +399,42 @@ struct get_pages_work {
         struct task_struct *task;
 };
 
-#if IS_ENABLED(CONFIG_SWIOTLB)
-#define swiotlb_active() swiotlb_nr_tbl()
-#else
-#define swiotlb_active() 0
-#endif
-
-static int
-st_set_pages(struct sg_table **st, struct page **pvec, int num_pages)
-{
-        struct scatterlist *sg;
-        int ret, n;
-
-        *st = kmalloc(sizeof(**st), GFP_KERNEL);
-        if (*st == NULL)
-                return -ENOMEM;
-
-        if (swiotlb_active()) {
-                ret = sg_alloc_table(*st, num_pages, GFP_KERNEL);
-                if (ret)
-                        goto err;
-
-                for_each_sg((*st)->sgl, sg, num_pages, n)
-                        sg_set_page(sg, pvec[n], PAGE_SIZE, 0);
-        } else {
-                ret = sg_alloc_table_from_pages(*st, pvec, num_pages,
-                                                0, num_pages << PAGE_SHIFT,
-                                                GFP_KERNEL);
-                if (ret)
-                        goto err;
-        }
-
-        return 0;
-
-err:
-        kfree(*st);
-        *st = NULL;
-        return ret;
-}
-
 static struct sg_table *
-__i915_gem_userptr_set_pages(struct drm_i915_gem_object *obj,
-                             struct page **pvec, int num_pages)
+__i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj,
+                               struct page **pvec, int num_pages)
 {
-        struct sg_table *pages;
+        unsigned int max_segment = i915_sg_segment_size();
+        struct sg_table *st;
         int ret;
 
-        ret = st_set_pages(&pages, pvec, num_pages);
-        if (ret)
+        st = kmalloc(sizeof(*st), GFP_KERNEL);
+        if (!st)
+                return ERR_PTR(-ENOMEM);
+
+alloc_table:
+        ret = __sg_alloc_table_from_pages(st, pvec, num_pages,
+                                          0, num_pages << PAGE_SHIFT,
+                                          max_segment,
+                                          GFP_KERNEL);
+        if (ret) {
+                kfree(st);
                 return ERR_PTR(ret);
+        }
 
-        ret = i915_gem_gtt_prepare_pages(obj, pages);
+        ret = i915_gem_gtt_prepare_pages(obj, st);
         if (ret) {
-                sg_free_table(pages);
-                kfree(pages);
+                sg_free_table(st);
+
+                if (max_segment > PAGE_SIZE) {
+                        max_segment = PAGE_SIZE;
+                        goto alloc_table;
+                }
+
+                kfree(st);
                 return ERR_PTR(ret);
         }
 
-        return pages;
+        return st;
 }
 
 static int
@@ -540,7 +518,8 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
                 struct sg_table *pages = ERR_PTR(ret);
 
                 if (pinned == npages) {
-                        pages = __i915_gem_userptr_set_pages(obj, pvec, npages);
+                        pages = __i915_gem_userptr_alloc_pages(obj, pvec,
+                                                               npages);
                         if (!IS_ERR(pages)) {
                                 __i915_gem_object_set_pages(obj, pages);
                                 pinned = 0;
@@ -661,7 +640,7 @@ i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
                 pages = __i915_gem_userptr_get_pages_schedule(obj);
                 active = pages == ERR_PTR(-EAGAIN);
         } else {
-                pages = __i915_gem_userptr_set_pages(obj, pvec, num_pages);
+                pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages);
                 active = !IS_ERR(pages);
         }
         if (active)
@@ -834,7 +813,9 @@ int i915_gem_init_userptr(struct drm_i915_private *dev_priv)
         hash_init(dev_priv->mm_structs);
 
         dev_priv->mm.userptr_wq =
-                alloc_workqueue("i915-userptr-acquire", WQ_HIGHPRI, 0);
+                alloc_workqueue("i915-userptr-acquire",
+                                WQ_HIGHPRI | WQ_MEM_RECLAIM,
+                                0);
         if (!dev_priv->mm.userptr_wq)
                 return -ENOMEM;
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0c779671fe2d..c14552ab270b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -396,6 +396,8 @@ static void error_print_context(struct drm_i915_error_state_buf *m,
 static void error_print_engine(struct drm_i915_error_state_buf *m,
                                const struct drm_i915_error_engine *ee)
 {
+        int n;
+
         err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
         err_printf(m, "  START: 0x%08x\n", ee->start);
         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
@@ -465,8 +467,11 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
                    jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 
-        error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
-        error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
+        for (n = 0; n < ee->num_ports; n++) {
+                err_printf(m, "  ELSP[%d]:", n);
+                error_print_request(m, " ", &ee->execlist[n]);
+        }
+
         error_print_context(m, "  Active context: ", &ee->context);
 }
 
@@ -567,7 +572,7 @@ static __always_inline void err_print_param(struct drm_i915_error_state_buf *m,
 static void err_print_params(struct drm_i915_error_state_buf *m,
                              const struct i915_params *p)
 {
-#define PRINT(T, x) err_print_param(m, #x, #T, &p->x);
+#define PRINT(T, x, ...) err_print_param(m, #x, #T, &p->x);
         I915_PARAMS_FOR_EACH(PRINT);
 #undef PRINT
 }
@@ -861,7 +866,7 @@ void __i915_gpu_state_free(struct kref *error_ref)
         kfree(error->overlay);
         kfree(error->display);
 
-#define FREE(T, x) free_param(#T, &error->params.x);
+#define FREE(T, x, ...) free_param(#T, &error->params.x);
         I915_PARAMS_FOR_EACH(FREE);
 #undef FREE
 
@@ -1327,17 +1332,19 @@ static void engine_record_requests(struct intel_engine_cs *engine,
 static void error_record_engine_execlists(struct intel_engine_cs *engine,
                                           struct drm_i915_error_engine *ee)
 {
-        const struct execlist_port *port = engine->execlist_port;
+        const struct intel_engine_execlists * const execlists = &engine->execlists;
         unsigned int n;
 
-        for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
-                struct drm_i915_gem_request *rq = port_request(&port[n]);
+        for (n = 0; n < execlists_num_ports(execlists); n++) {
+                struct drm_i915_gem_request *rq = port_request(&execlists->port[n]);
 
                 if (!rq)
                         break;
 
                 record_request(rq, &ee->execlist[n]);
         }
+
+        ee->num_ports = n;
 }
 
 static void record_context(struct drm_i915_error_context *e,
@@ -1554,7 +1561,7 @@ static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
                                             struct i915_gpu_state *error)
 {
         /* Capturing log buf contents won't be useful if logging was disabled */
-        if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
+        if (!dev_priv->guc.log.vma || (i915_modparams.guc_log_level < 0))
                 return;
 
         error->guc_log = i915_error_object_create(dev_priv,
@@ -1696,8 +1703,8 @@ static int capture(void *data)
                 ktime_to_timeval(ktime_sub(ktime_get(),
                                            error->i915->gt.last_init_time));
 
-        error->params = i915;
-#define DUP(T, x) dup_param(#T, &error->params.x);
+        error->params = i915_modparams;
+#define DUP(T, x, ...) dup_param(#T, &error->params.x);
         I915_PARAMS_FOR_EACH(DUP);
 #undef DUP
 
@@ -1751,7 +1758,7 @@ void i915_capture_error_state(struct drm_i915_private *dev_priv,
         struct i915_gpu_state *error;
         unsigned long flags;
 
-        if (!i915.error_capture)
+        if (!i915_modparams.error_capture)
                 return;
 
         if (READ_ONCE(dev_priv->gpu_error.first_error))
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e9349a2c..04f1281d81a5 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -192,13 +192,12 @@ static int __create_doorbell(struct i915_guc_client *client)
 
         doorbell = __get_doorbell(client);
         doorbell->db_status = GUC_DOORBELL_ENABLED;
-        doorbell->cookie = client->doorbell_cookie;
+        doorbell->cookie = 0;
 
         err = __guc_allocate_doorbell(client->guc, client->stage_id);
-        if (err) {
+        if (err)
                 doorbell->db_status = GUC_DOORBELL_DISABLED;
-                doorbell->cookie = 0;
-        }
+
         return err;
 }
 
@@ -306,7 +305,7 @@ static void guc_proc_desc_init(struct intel_guc *guc,
         desc->db_base_addr = 0;
 
         desc->stage_id = client->stage_id;
-        desc->wq_size_bytes = client->wq_size;
+        desc->wq_size_bytes = GUC_WQ_SIZE;
         desc->wq_status = WQ_STATUS_ACTIVE;
         desc->priority = client->priority;
 }
@@ -391,8 +390,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
         desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
         desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
         desc->process_desc = gfx_addr + client->proc_desc_offset;
-        desc->wq_addr = gfx_addr + client->wq_offset;
-        desc->wq_size = client->wq_size;
+        desc->wq_addr = gfx_addr + GUC_DB_SIZE;
+        desc->wq_size = GUC_WQ_SIZE;
 
         desc->desc_private = (uintptr_t)client;
 }
@@ -406,82 +405,23 @@ static void guc_stage_desc_fini(struct intel_guc *guc,
         memset(desc, 0, sizeof(*desc));
 }
 
-/**
- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
- * @request:    request associated with the commands
- *
- * Return:      0 if space is available
- *              -EAGAIN if space is not currently available
- *
- * This function must be called (and must return 0) before a request
- * is submitted to the GuC via i915_guc_submit() below. Once a result
- * of 0 has been returned, it must be balanced by a corresponding
- * call to submit().
- *
- * Reservation allows the caller to determine in advance that space
- * will be available for the next submission before committing resources
- * to it, and helps avoid late failures with complicated recovery paths.
- */
-int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
-{
-        const size_t wqi_size = sizeof(struct guc_wq_item);
-        struct i915_guc_client *client = request->i915->guc.execbuf_client;
-        struct guc_process_desc *desc = __get_process_desc(client);
-        u32 freespace;
-        int ret;
-
-        spin_lock_irq(&client->wq_lock);
-        freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
-        freespace -= client->wq_rsvd;
-        if (likely(freespace >= wqi_size)) {
-                client->wq_rsvd += wqi_size;
-                ret = 0;
-        } else {
-                client->no_wq_space++;
-                ret = -EAGAIN;
-        }
-        spin_unlock_irq(&client->wq_lock);
-
-        return ret;
-}
-
-static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&client->wq_lock, flags);
-        client->wq_rsvd += size;
-        spin_unlock_irqrestore(&client->wq_lock, flags);
-}
-
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
-{
-        const int wqi_size = sizeof(struct guc_wq_item);
-        struct i915_guc_client *client = request->i915->guc.execbuf_client;
-
-        GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
-        guc_client_update_wq_rsvd(client, -wqi_size);
-}
-
 /* Construct a Work Item and append it to the GuC's Work Queue */
 static void guc_wq_item_append(struct i915_guc_client *client,
                                struct drm_i915_gem_request *rq)
 {
         /* wqi_len is in DWords, and does not include the one-word header */
         const size_t wqi_size = sizeof(struct guc_wq_item);
-        const u32 wqi_len = wqi_size/sizeof(u32) - 1;
+        const u32 wqi_len = wqi_size / sizeof(u32) - 1;
         struct intel_engine_cs *engine = rq->engine;
+        struct i915_gem_context *ctx = rq->ctx;
         struct guc_process_desc *desc = __get_process_desc(client);
         struct guc_wq_item *wqi;
-        u32 freespace, tail, wq_off;
+        u32 ring_tail, wq_off;
 
-        /* Free space is guaranteed, see i915_guc_wq_reserve() above */
-        freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
-        GEM_BUG_ON(freespace < wqi_size);
+        lockdep_assert_held(&client->wq_lock);
 
-        /* The GuC firmware wants the tail index in QWords, not bytes */
-        tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3;
-        GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
+        ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
+        GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
 
         /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
          * should not have the case where structure wqi is across page, neither
@@ -491,29 +431,29 @@ static void guc_wq_item_append(struct i915_guc_client *client,
          * workqueue buffer dw by dw.
          */
         BUILD_BUG_ON(wqi_size != 16);
-        GEM_BUG_ON(client->wq_rsvd < wqi_size);
 
-        /* postincrement WQ tail for next time */
-        wq_off = client->wq_tail;
+        /* Free space is guaranteed. */
+        wq_off = READ_ONCE(desc->tail);
+        GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
+                              GUC_WQ_SIZE) < wqi_size);
         GEM_BUG_ON(wq_off & (wqi_size - 1));
-        client->wq_tail += wqi_size;
-        client->wq_tail &= client->wq_size - 1;
-        client->wq_rsvd -= wqi_size;
 
         /* WQ starts from the page after doorbell / process_desc */
         wqi = client->vaddr + wq_off + GUC_DB_SIZE;
 
         /* Now fill in the 4-word work queue item */
         wqi->header = WQ_TYPE_INORDER |
-                        (wqi_len << WQ_LEN_SHIFT) |
-                        (engine->guc_id << WQ_TARGET_SHIFT) |
-                        WQ_NO_WCFLUSH_WAIT;
+                      (wqi_len << WQ_LEN_SHIFT) |
+                      (engine->guc_id << WQ_TARGET_SHIFT) |
+                      WQ_NO_WCFLUSH_WAIT;
 
-        /* The GuC wants only the low-order word of the context descriptor */
-        wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
+        wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx, engine));
 
-        wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
+        wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
         wqi->fence_id = rq->global_seqno;
+
+        /* Postincrement WQ tail for next time. */
+        WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
 }
 
 static void guc_reset_wq(struct i915_guc_client *client)
@@ -522,106 +462,64 @@ static void guc_reset_wq(struct i915_guc_client *client)
 
         desc->head = 0;
         desc->tail = 0;
-
-        client->wq_tail = 0;
 }
 
-static int guc_ring_doorbell(struct i915_guc_client *client)
+static void guc_ring_doorbell(struct i915_guc_client *client)
 {
-        struct guc_process_desc *desc = __get_process_desc(client);
-        union guc_doorbell_qw db_cmp, db_exc, db_ret;
-        union guc_doorbell_qw *db;
-        int attempt = 2, ret = -EAGAIN;
-
-        /* Update the tail so it is visible to GuC */
-        desc->tail = client->wq_tail;
-
-        /* current cookie */
-        db_cmp.db_status = GUC_DOORBELL_ENABLED;
-        db_cmp.cookie = client->doorbell_cookie;
+        struct guc_doorbell_info *db;
+        u32 cookie;
 
-        /* cookie to be updated */
-        db_exc.db_status = GUC_DOORBELL_ENABLED;
-        db_exc.cookie = client->doorbell_cookie + 1;
-        if (db_exc.cookie == 0)
-                db_exc.cookie = 1;
+        lockdep_assert_held(&client->wq_lock);
 
         /* pointer of current doorbell cacheline */
-        db = (union guc_doorbell_qw *)__get_doorbell(client);
-
-        while (attempt--) {
-                /* lets ring the doorbell */
-                db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
-                        db_cmp.value_qw, db_exc.value_qw);
-
-                /* if the exchange was successfully executed */
-                if (db_ret.value_qw == db_cmp.value_qw) {
-                        /* db was successfully rung */
-                        client->doorbell_cookie = db_exc.cookie;
-                        ret = 0;
-                        break;
-                }
-
-                /* XXX: doorbell was lost and need to acquire it again */
-                if (db_ret.db_status == GUC_DOORBELL_DISABLED)
-                        break;
+        db = __get_doorbell(client);
 
-                DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
-                         db_cmp.cookie, db_ret.cookie);
-
-                /* update the cookie to newly read cookie from GuC */
-                db_cmp.cookie = db_ret.cookie;
-                db_exc.cookie = db_ret.cookie + 1;
-                if (db_exc.cookie == 0)
-                        db_exc.cookie = 1;
-        }
+        /* we're not expecting the doorbell cookie to change behind our back */
+        cookie = READ_ONCE(db->cookie);
+        WARN_ON_ONCE(xchg(&db->cookie, cookie + 1) != cookie);
 
-        return ret;
+        /* XXX: doorbell was lost and need to acquire it again */
+        GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
 }
 
 /**
- * __i915_guc_submit() - Submit commands through GuC
- * @rq:         request associated with the commands
- *
- * The caller must have already called i915_guc_wq_reserve() above with
- * a result of 0 (success), guaranteeing that there is space in the work
- * queue for the new request, so enqueuing the item cannot fail.
- *
- * Bad Things Will Happen if the caller violates this protocol e.g. calls
- * submit() when _reserve() says there's no space, or calls _submit()
- * a different number of times from (successful) calls to _reserve().
+ * i915_guc_submit() - Submit commands through GuC
+ * @engine: engine associated with the commands
  *
  * The only error here arises if the doorbell hardware isn't functioning
  * as expected, which really shouln't happen.
  */
-static void __i915_guc_submit(struct drm_i915_gem_request *rq)
+static void i915_guc_submit(struct intel_engine_cs *engine)
 {
-        struct drm_i915_private *dev_priv = rq->i915;
-        struct intel_engine_cs *engine = rq->engine;
-        unsigned int engine_id = engine->id;
-        struct intel_guc *guc = &rq->i915->guc;
+        struct drm_i915_private *dev_priv = engine->i915;
+        struct intel_guc *guc = &dev_priv->guc;
         struct i915_guc_client *client = guc->execbuf_client;
-        unsigned long flags;
-        int b_ret;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct execlist_port *port = execlists->port;
+        const unsigned int engine_id = engine->id;
+        unsigned int n;
 
-        /* WA to flush out the pending GMADR writes to ring buffer. */
-        if (i915_vma_is_map_and_fenceable(rq->ring->vma))
-                POSTING_READ_FW(GUC_STATUS);
+        for (n = 0; n < ARRAY_SIZE(execlists->port); n++) {
+                struct drm_i915_gem_request *rq;
+                unsigned int count;
 
-        spin_lock_irqsave(&client->wq_lock, flags);
+                rq = port_unpack(&port[n], &count);
+                if (rq && count == 0) {
+                        port_set(&port[n], port_pack(rq, ++count));
 
-        guc_wq_item_append(client, rq);
-        b_ret = guc_ring_doorbell(client);
+                        if (i915_vma_is_map_and_fenceable(rq->ring->vma))
+                                POSTING_READ_FW(GUC_STATUS);
 
-        client->submissions[engine_id] += 1;
+                        spin_lock(&client->wq_lock);
 
-        spin_unlock_irqrestore(&client->wq_lock, flags);
-}
+                        guc_wq_item_append(client, rq);
+                        guc_ring_doorbell(client);
 
-static void i915_guc_submit(struct drm_i915_gem_request *rq)
-{
-        __i915_gem_request_submit(rq);
-        __i915_guc_submit(rq);
+                        client->submissions[engine_id] += 1;
+
+                        spin_unlock(&client->wq_lock);
+                }
+        }
 }
 
 static void nested_enable_signaling(struct drm_i915_gem_request *rq)
@@ -655,27 +553,33 @@ static void port_assign(struct execlist_port *port,
         if (port_isset(port))
                 i915_gem_request_put(port_request(port));
 
-        port_set(port, i915_gem_request_get(rq));
+        port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
         nested_enable_signaling(rq);
 }
 
-static bool i915_guc_dequeue(struct intel_engine_cs *engine)
+static void i915_guc_dequeue(struct intel_engine_cs *engine)
 {
-        struct execlist_port *port = engine->execlist_port;
-        struct drm_i915_gem_request *last = port_request(port);
-        struct rb_node *rb;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct execlist_port *port = execlists->port;
+        struct drm_i915_gem_request *last = NULL;
+        const struct execlist_port * const last_port =
+                &execlists->port[execlists->port_mask];
         bool submit = false;
+        struct rb_node *rb;
+
+        if (port_isset(port))
+                port++;
 
         spin_lock_irq(&engine->timeline->lock);
-        rb = engine->execlist_first;
-        GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
+        rb = execlists->first;
+        GEM_BUG_ON(rb_first(&execlists->queue) != rb);
         while (rb) {
                 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
                 struct drm_i915_gem_request *rq, *rn;
 
                 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
                         if (last && rq->ctx != last->ctx) {
-                                if (port != engine->execlist_port) {
+                                if (port == last_port) {
                                         __list_del_many(&p->requests,
                                                         &rq->priotree.link);
                                         goto done;
@@ -689,50 +593,48 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
                         INIT_LIST_HEAD(&rq->priotree.link);
                         rq->priotree.priority = INT_MAX;
 
-                        i915_guc_submit(rq);
-                        trace_i915_gem_request_in(rq, port_index(port, engine));
+                        __i915_gem_request_submit(rq);
+                        trace_i915_gem_request_in(rq, port_index(port, execlists));
                         last = rq;
                         submit = true;
                 }
 
                 rb = rb_next(rb);
-                rb_erase(&p->node, &engine->execlist_queue);
+                rb_erase(&p->node, &execlists->queue);
                 INIT_LIST_HEAD(&p->requests);
                 if (p->priority != I915_PRIORITY_NORMAL)
                         kmem_cache_free(engine->i915->priorities, p);
         }
 done:
-        engine->execlist_first = rb;
-        if (submit)
+        execlists->first = rb;
+        if (submit) {
                 port_assign(port, last);
+                i915_guc_submit(engine);
+        }
         spin_unlock_irq(&engine->timeline->lock);
-
-        return submit;
 }
 
 static void i915_guc_irq_handler(unsigned long data)
 {
-        struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
-        struct execlist_port *port = engine->execlist_port;
+        struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct execlist_port *port = execlists->port;
+        const struct execlist_port * const last_port =
+                &execlists->port[execlists->port_mask];
         struct drm_i915_gem_request *rq;
-        bool submit;
 
-        do {
-                rq = port_request(&port[0]);
-                while (rq && i915_gem_request_completed(rq)) {
-                        trace_i915_gem_request_out(rq);
-                        i915_gem_request_put(rq);
+        rq = port_request(&port[0]);
+        while (rq && i915_gem_request_completed(rq)) {
+                trace_i915_gem_request_out(rq);
+                i915_gem_request_put(rq);
 
-                        port[0] = port[1];
-                        memset(&port[1], 0, sizeof(port[1]));
+                execlists_port_complete(execlists, port);
 
-                        rq = port_request(&port[0]);
-                }
+                rq = port_request(&port[0]);
+        }
 
-                submit = false;
-                if (!port_count(&port[1]))
-                        submit = i915_guc_dequeue(engine);
-        } while (submit);
+        if (!port_isset(last_port))
+                i915_guc_dequeue(engine);
 }
 
 /*
@@ -913,8 +815,6 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
         client->engines = engines;
         client->priority = priority;
         client->doorbell_id = GUC_DOORBELL_INVALID;
-        client->wq_offset = GUC_DB_SIZE;
-        client->wq_size = GUC_WQ_SIZE;
         spin_lock_init(&client->wq_lock);
 
         ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
@@ -996,28 +896,39 @@ static void guc_client_free(struct i915_guc_client *client)
         kfree(client);
 }
 
+static void guc_policy_init(struct guc_policy *policy)
+{
+        policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
+        policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
+        policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
+        policy->policy_flags = 0;
+}
+
 static void guc_policies_init(struct guc_policies *policies)
 {
         struct guc_policy *policy;
         u32 p, i;
 
-        policies->dpc_promote_time = 500000;
+        policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
         policies->max_num_work_items = POLICY_MAX_NUM_WI;
 
         for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
                 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
                         policy = &policies->policy[p][i];
 
-                        policy->execution_quantum = 1000000;
-                        policy->preemption_time = 500000;
-                        policy->fault_time = 250000;
-                        policy->policy_flags = 0;
+                        guc_policy_init(policy);
                 }
         }
 
         policies->is_valid = 1;
 }
 
+/*
+ * The first 80 dwords of the register state context, containing the
+ * execlists and ppgtt registers.
+ */
+#define LR_HW_CONTEXT_SIZE      (80 * sizeof(u32))
+
 static int guc_ads_create(struct intel_guc *guc)
 {
         struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1032,6 +943,8 @@ static int guc_ads_create(struct intel_guc *guc)
         } __packed *blob;
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
+        const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
+        const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
         u32 base;
 
         GEM_BUG_ON(guc->ads_vma);
@@ -1062,13 +975,20 @@ static int guc_ads_create(struct intel_guc *guc)
          * engines after a reset. Here we use the Render ring default
          * context, which must already exist and be pinned in the GGTT,
          * so its address won't change after we've told the GuC where
-         * to find it.
+         * to find it. Note that we have to skip our header (1 page),
+         * because our GuC shared data is there.
          */
         blob->ads.golden_context_lrca =
-                dev_priv->engine[RCS]->status_page.ggtt_offset;
+                guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) + skipped_offset;
 
+        /*
+         * The GuC expects us to exclude the portion of the context image that
+         * it skips from the size it is to read. It starts reading from after
+         * the execlist context (so skipping the first page [PPHWSP] and 80
+         * dwords). Weird guc is weird.
+         */
         for_each_engine(engine, dev_priv, id)
-                blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
+                blob->ads.eng_state_size[engine->guc_id] = engine->context_size - skipped_size;
 
         base = guc_ggtt_offset(vma);
         blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
@@ -1221,6 +1141,19 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
         enum intel_engine_id id;
         int err;
 
+        /*
+         * We're using GuC work items for submitting work through GuC. Since
+         * we're coalescing multiple requests from a single context into a
+         * single work item prior to assigning it to execlist_port, we can
+         * never have more work items than the total number of ports (for all
+         * engines). The GuC firmware is controlling the HEAD of work queue,
+         * and it is guaranteed that it will remove the work item from the
+         * queue before our request is completed.
+         */
+        BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
+                     sizeof(struct guc_wq_item) *
+                     I915_NUM_ENGINES > GUC_WQ_SIZE);
+
         if (!client) {
                 client = guc_client_alloc(dev_priv,
                                           INTEL_INFO(dev_priv)->ring_mask,
@@ -1248,24 +1181,15 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
         guc_interrupts_capture(dev_priv);
 
         for_each_engine(engine, dev_priv, id) {
-                const int wqi_size = sizeof(struct guc_wq_item);
-                struct drm_i915_gem_request *rq;
-
+                struct intel_engine_execlists * const execlists = &engine->execlists;
                 /* The tasklet was initialised by execlists, and may be in
                  * a state of flux (across a reset) and so we just want to
                  * take over the callback without changing any other state
                  * in the tasklet.
                  */
-                engine->irq_tasklet.func = i915_guc_irq_handler;
+                execlists->irq_tasklet.func = i915_guc_irq_handler;
                 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-
-                /* Replay the current set of previously submitted requests */
-                spin_lock_irq(&engine->timeline->lock);
-                list_for_each_entry(rq, &engine->timeline->requests, link) {
-                        guc_client_update_wq_rsvd(client, wqi_size);
-                        __i915_guc_submit(rq);
-                }
-                spin_unlock_irq(&engine->timeline->lock);
+                tasklet_schedule(&execlists->irq_tasklet);
         }
 
         return 0;
@@ -1310,7 +1234,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
         /* any value greater than GUC_POWER_D0 */
         data[1] = GUC_POWER_D1;
         /* first page is shared data with GuC */
-        data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+        data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
 
         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -1328,7 +1252,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
                 return 0;
 
-        if (i915.guc_log_level >= 0)
+        if (i915_modparams.guc_log_level >= 0)
                 gen9_enable_guc_interrupts(dev_priv);
 
         ctx = dev_priv->kernel_context;
@@ -1336,7 +1260,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
         data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
         data[1] = GUC_POWER_D0;
         /* first page is shared data with GuC */
-        data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+        data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
 
         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2fe92d2e0f62..efd7827ff181 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,7 +126,7 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
         POSTING_READ(GEN8_##type##_IIR(which)); \
 } while (0)
 
-#define GEN5_IRQ_RESET(type) do { \
+#define GEN3_IRQ_RESET(type) do { \
         I915_WRITE(type##IMR, 0xffffffff); \
         POSTING_READ(type##IMR); \
         I915_WRITE(type##IER, 0); \
@@ -136,10 +136,20 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
         POSTING_READ(type##IIR); \
 } while (0)
 
+#define GEN2_IRQ_RESET(type) do { \
+        I915_WRITE16(type##IMR, 0xffff); \
+        POSTING_READ16(type##IMR); \
+        I915_WRITE16(type##IER, 0); \
+        I915_WRITE16(type##IIR, 0xffff); \
+        POSTING_READ16(type##IIR); \
+        I915_WRITE16(type##IIR, 0xffff); \
+        POSTING_READ16(type##IIR); \
+} while (0)
+
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
+static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
                                     i915_reg_t reg)
 {
         u32 val = I915_READ(reg);
@@ -155,20 +165,43 @@ static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
         POSTING_READ(reg);
 }
 
+static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
+                                    i915_reg_t reg)
+{
+        u16 val = I915_READ16(reg);
+
+        if (val == 0)
+                return;
+
+        WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
+             i915_mmio_reg_offset(reg), val);
+        I915_WRITE16(reg, 0xffff);
+        POSTING_READ16(reg);
+        I915_WRITE16(reg, 0xffff);
+        POSTING_READ16(reg);
+}
+
 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
-        gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
+        gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
         POSTING_READ(GEN8_##type##_IMR(which)); \
 } while (0)
 
-#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
-        gen5_assert_iir_is_zero(dev_priv, type##IIR); \
+#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
+        gen3_assert_iir_is_zero(dev_priv, type##IIR); \
         I915_WRITE(type##IER, (ier_val)); \
         I915_WRITE(type##IMR, (imr_val)); \
         POSTING_READ(type##IMR); \
 } while (0)
 
+#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
+        gen2_assert_iir_is_zero(dev_priv, type##IIR); \
+        I915_WRITE16(type##IER, (ier_val)); \
+        I915_WRITE16(type##IMR, (imr_val)); \
+        POSTING_READ16(type##IMR); \
+} while (0)
+
 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 
@@ -534,62 +567,16 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
         POSTING_READ(SDEIMR);
 }
 
-static void
-__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
-                       u32 enable_mask, u32 status_mask)
+u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
+                              enum pipe pipe)
 {
-        i915_reg_t reg = PIPESTAT(pipe);
-        u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
-
-        lockdep_assert_held(&dev_priv->irq_lock);
-        WARN_ON(!intel_irqs_enabled(dev_priv));
-
-        if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
-                      status_mask & ~PIPESTAT_INT_STATUS_MASK,
-                      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
-                      pipe_name(pipe), enable_mask, status_mask))
-                return;
-
-        if ((pipestat & enable_mask) == enable_mask)
-                return;
-
-        dev_priv->pipestat_irq_mask[pipe] |= status_mask;
-
-        /* Enable the interrupt, clear any pending status */
-        pipestat |= enable_mask | status_mask;
-        I915_WRITE(reg, pipestat);
-        POSTING_READ(reg);
-}
-
-static void
-__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
-                        u32 enable_mask, u32 status_mask)
-{
-        i915_reg_t reg = PIPESTAT(pipe);
-        u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
+        u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
+        u32 enable_mask = status_mask << 16;
 
         lockdep_assert_held(&dev_priv->irq_lock);
-        WARN_ON(!intel_irqs_enabled(dev_priv));
-
-        if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
-                      status_mask & ~PIPESTAT_INT_STATUS_MASK,
-                      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
-                      pipe_name(pipe), enable_mask, status_mask))
-                return;
-
-        if ((pipestat & enable_mask) == 0)
-                return;
-
-        dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 
-        pipestat &= ~enable_mask;
-        I915_WRITE(reg, pipestat);
-        POSTING_READ(reg);
-}
-
-static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
-{
-        u32 enable_mask = status_mask << 16;
+        if (INTEL_GEN(dev_priv) < 5)
+                goto out;
 
         /*
          * On pipe A we don't support the PSR interrupt yet,
@@ -612,35 +599,59 @@ static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 
+out:
+        WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
+                  status_mask & ~PIPESTAT_INT_STATUS_MASK,
+                  "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
+                  pipe_name(pipe), enable_mask, status_mask);
+
         return enable_mask;
 }
 
-void
-i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
-                     u32 status_mask)
+void i915_enable_pipestat(struct drm_i915_private *dev_priv,
+                          enum pipe pipe, u32 status_mask)
 {
+        i915_reg_t reg = PIPESTAT(pipe);
         u32 enable_mask;
 
-        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-                enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
-                                                           status_mask);
-        else
-                enable_mask = status_mask << 16;
-        __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
+        WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
+                  "pipe %c: status_mask=0x%x\n",
+                  pipe_name(pipe), status_mask);
+
+        lockdep_assert_held(&dev_priv->irq_lock);
+        WARN_ON(!intel_irqs_enabled(dev_priv));
+
+        if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
+                return;
+
+        dev_priv->pipestat_irq_mask[pipe] |= status_mask;
+        enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+
+        I915_WRITE(reg, enable_mask | status_mask);
+        POSTING_READ(reg);
 }
 
-void
-i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
-                      u32 status_mask)
+void i915_disable_pipestat(struct drm_i915_private *dev_priv,
+                           enum pipe pipe, u32 status_mask)
 {
+        i915_reg_t reg = PIPESTAT(pipe);
         u32 enable_mask;
 
-        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-                enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
-                                                           status_mask);
-        else
-                enable_mask = status_mask << 16;
-        __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
+        WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
+                  "pipe %c: status_mask=0x%x\n",
+                  pipe_name(pipe), status_mask);
+
+        lockdep_assert_held(&dev_priv->irq_lock);
+        WARN_ON(!intel_irqs_enabled(dev_priv));
+
+        if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
+                return;
+
+        dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
+        enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+
+        I915_WRITE(reg, enable_mask | status_mask);
+        POSTING_READ(reg);
 }
 
 /**
@@ -772,6 +783,57 @@ static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
+/*
+ * On certain encoders on certain platforms, pipe
+ * scanline register will not work to get the scanline,
+ * since the timings are driven from the PORT or issues
+ * with scanline register updates.
+ * This function will use Framestamp and current
+ * timestamp registers to calculate the scanline.
+ */
+static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
+{
+        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+        struct drm_vblank_crtc *vblank =
+                &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
+        const struct drm_display_mode *mode = &vblank->hwmode;
+        u32 vblank_start = mode->crtc_vblank_start;
+        u32 vtotal = mode->crtc_vtotal;
+        u32 htotal = mode->crtc_htotal;
+        u32 clock = mode->crtc_clock;
+        u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
+
+        /*
+         * To avoid the race condition where we might cross into the
+         * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
+         * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
+         * during the same frame.
+         */
+        do {
+                /*
+                 * This field provides read back of the display
+                 * pipe frame time stamp. The time stamp value
+                 * is sampled at every start of vertical blank.
+                 */
+                scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+
+                /*
+                 * The TIMESTAMP_CTR register has the current
+                 * time stamp value.
+                 */
+                scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
+
+                scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
+        } while (scan_post_time != scan_prev_time);
+
+        scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
+                                        clock), 1000 * htotal);
+        scanline = min(scanline, vtotal - 1);
+        scanline = (scanline + vblank_start) % vtotal;
+
+        return scanline;
+}
+
 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 {
@@ -788,6 +850,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
         mode = &vblank->hwmode;
 
+        if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
+                return __intel_get_crtc_scanline_from_timestamp(crtc);
+
         vtotal = mode->crtc_vtotal;
         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
                 vtotal /= 2;
@@ -1005,6 +1070,8 @@ static void notify_ring(struct intel_engine_cs *engine)
         spin_lock(&engine->breadcrumbs.irq_lock);
         wait = engine->breadcrumbs.irq_wait;
         if (wait) {
+                bool wakeup = engine->irq_seqno_barrier;
+
                 /* We use a callback from the dma-fence to submit
                  * requests after waiting on our own requests. To
                  * ensure minimum delay in queuing the next request to
@@ -1017,12 +1084,18 @@ static void notify_ring(struct intel_engine_cs *engine)
                  * and many waiters.
                  */
                 if (i915_seqno_passed(intel_engine_get_seqno(engine),
-                                      wait->seqno) &&
-                    !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
-                              &wait->request->fence.flags))
-                        rq = i915_gem_request_get(wait->request);
+                                      wait->seqno)) {
+                        struct drm_i915_gem_request *waiter = wait->request;
+
+                        wakeup = true;
+                        if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+                                      &waiter->fence.flags) &&
+                            intel_wait_check_request(wait, waiter))
+                                rq = i915_gem_request_get(waiter);
+                }
 
-                wake_up_process(wait->tsk);
+                if (wakeup)
+                        wake_up_process(wait->tsk);
         } else {
                 __intel_engine_disarm_breadcrumbs(engine);
         }
@@ -1305,10 +1378,11 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
 static void
 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
 {
+        struct intel_engine_execlists * const execlists = &engine->execlists;
         bool tasklet = false;
 
         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
-                if (port_count(&engine->execlist_port[0])) {
+                if (port_count(&execlists->port[0])) {
                         __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
                         tasklet = true;
                 }
@@ -1316,11 +1390,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
 
         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
                 notify_ring(engine);
-                tasklet |= i915.enable_guc_submission;
+                tasklet |= i915_modparams.enable_guc_submission;
         }
 
         if (tasklet)
-                tasklet_hi_schedule(&engine->irq_tasklet);
+                tasklet_hi_schedule(&execlists->irq_tasklet);
 }
 
 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
@@ -1573,11 +1647,11 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
                  * bonkers. So let's just wait for the next vblank and read
                  * out the buggy result.
                  *
-                 * On CHV sometimes the second CRC is bonkers as well, so
+                 * On GEN8+ sometimes the second CRC is bonkers as well, so
                  * don't trust that one either.
                  */
                 if (pipe_crc->skipped == 0 ||
-                    (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
+                    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
                         pipe_crc->skipped++;
                         spin_unlock(&pipe_crc->lock);
                         return;
@@ -1706,8 +1780,21 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
         }
 }
 
-static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
-                                        u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
+{
+        enum pipe pipe;
+
+        for_each_pipe(dev_priv, pipe) {
+                I915_WRITE(PIPESTAT(pipe),
+                           PIPESTAT_INT_STATUS_MASK |
+                           PIPE_FIFO_UNDERRUN_STATUS);
+
+                dev_priv->pipestat_irq_mask[pipe] = 0;
+        }
+}
+
+static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
+                                  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
 {
         int pipe;
 
@@ -1720,7 +1807,7 @@ static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
         for_each_pipe(dev_priv, pipe) {
                 i915_reg_t reg;
-                u32 mask, iir_bit = 0;
+                u32 status_mask, enable_mask, iir_bit = 0;
 
                 /*
                  * PIPESTAT bits get signalled even when the interrupt is
@@ -1731,7 +1818,7 @@ static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
                  */
 
                 /* fifo underruns are filterered in the underrun handler. */
-                mask = PIPE_FIFO_UNDERRUN_STATUS;
+                status_mask = PIPE_FIFO_UNDERRUN_STATUS;
 
                 switch (pipe) {
                 case PIPE_A:
@@ -1745,25 +1832,92 @@ static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
                         break;
                 }
                 if (iir & iir_bit)
-                        mask |= dev_priv->pipestat_irq_mask[pipe];
+                        status_mask |= dev_priv->pipestat_irq_mask[pipe];
 
-                if (!mask)
+                if (!status_mask)
                         continue;
 
                 reg = PIPESTAT(pipe);
-                mask |= PIPESTAT_INT_ENABLE_MASK;
-                pipe_stats[pipe] = I915_READ(reg) & mask;
+                pipe_stats[pipe] = I915_READ(reg) & status_mask;
+                enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
                 /*
                  * Clear the PIPE*STAT regs before the IIR
                  */
-                if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
-                                        PIPESTAT_INT_STATUS_MASK))
-                        I915_WRITE(reg, pipe_stats[pipe]);
+                if (pipe_stats[pipe])
+                        I915_WRITE(reg, enable_mask | pipe_stats[pipe]);
         }
         spin_unlock(&dev_priv->irq_lock);
 }
 
+static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+                                      u16 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+        enum pipe pipe;
+
+        for_each_pipe(dev_priv, pipe) {
+                if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+                        drm_handle_vblank(&dev_priv->drm, pipe);
+
+                if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+                if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+        }
+}
+
+static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+                                      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+        bool blc_event = false;
+        enum pipe pipe;
+
+        for_each_pipe(dev_priv, pipe) {
+                if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+                        drm_handle_vblank(&dev_priv->drm, pipe);
+
+                if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+                        blc_event = true;
+
+                if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+                if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+        }
+
+        if (blc_event || (iir & I915_ASLE_INTERRUPT))
+                intel_opregion_asle_intr(dev_priv);
+}
+
+static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
+                                      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
+{
+        bool blc_event = false;
+        enum pipe pipe;
+
+        for_each_pipe(dev_priv, pipe) {
+                if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
+                        drm_handle_vblank(&dev_priv->drm, pipe);
+
+                if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+                        blc_event = true;
+
+                if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
+                        i9xx_pipe_crc_irq_handler(dev_priv, pipe);
+
+                if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+                        intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
+        }
+
+        if (blc_event || (iir & I915_ASLE_INTERRUPT))
+                intel_opregion_asle_intr(dev_priv);
+
+        if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
+                gmbus_irq_handler(dev_priv);
+}
+
 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
                                             u32 pipe_stats[I915_MAX_PIPES])
 {
@@ -1879,7 +2033,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 
                 /* Call regardless, as some status bits might not be
                  * signalled in iir */
-                valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+                i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
                            I915_LPE_PIPE_B_INTERRUPT))
@@ -1963,7 +2117,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 
                 /* Call regardless, as some status bits might not be
                  * signalled in iir */
-                valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
+                i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
                            I915_LPE_PIPE_B_INTERRUPT |
@@ -2860,7 +3014,7 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
         if (HAS_PCH_NOP(dev_priv))
                 return;
 
-        GEN5_IRQ_RESET(SDE);
+        GEN3_IRQ_RESET(SDE);
 
         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
                 I915_WRITE(SERR_INT, 0xffffffff);
@@ -2888,15 +3042,13 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
 
 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
 {
-        GEN5_IRQ_RESET(GT);
+        GEN3_IRQ_RESET(GT);
         if (INTEL_GEN(dev_priv) >= 6)
-                GEN5_IRQ_RESET(GEN6_PM);
+                GEN3_IRQ_RESET(GEN6_PM);
 }
 
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
-        enum pipe pipe;
-
         if (IS_CHERRYVIEW(dev_priv))
                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
         else
@@ -2905,14 +3057,9 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
-        for_each_pipe(dev_priv, pipe) {
-                I915_WRITE(PIPESTAT(pipe),
-                           PIPE_FIFO_UNDERRUN_STATUS |
-                           PIPESTAT_INT_STATUS_MASK);
-                dev_priv->pipestat_irq_mask[pipe] = 0;
-        }
+        i9xx_pipestat_irq_reset(dev_priv);
 
-        GEN5_IRQ_RESET(VLV_);
+        GEN3_IRQ_RESET(VLV_);
         dev_priv->irq_mask = ~0;
 }
 
@@ -2922,8 +3069,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
         u32 enable_mask;
         enum pipe pipe;
 
-        pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
-                        PIPE_CRC_DONE_INTERRUPT_STATUS;
+        pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
 
         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
         for_each_pipe(dev_priv, pipe)
@@ -2943,7 +3089,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 
         dev_priv->irq_mask = ~enable_mask;
 
-        GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
+        GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
 }
 
 /* drm_dma.h hooks
@@ -2952,9 +3098,10 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
 
-        I915_WRITE(HWSTAM, 0xffffffff);
+        if (IS_GEN5(dev_priv))
+                I915_WRITE(HWSTAM, 0xffffffff);
 
-        GEN5_IRQ_RESET(DE);
+        GEN3_IRQ_RESET(DE);
         if (IS_GEN7(dev_priv))
                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
 
@@ -2963,7 +3110,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
         ibx_irq_reset(dev_priv);
 }
 
-static void valleyview_irq_preinstall(struct drm_device *dev)
+static void valleyview_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -3001,9 +3148,9 @@ static void gen8_irq_reset(struct drm_device *dev)
                                                    POWER_DOMAIN_PIPE(pipe)))
                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
 
-        GEN5_IRQ_RESET(GEN8_DE_PORT_);
-        GEN5_IRQ_RESET(GEN8_DE_MISC_);
-        GEN5_IRQ_RESET(GEN8_PCU_);
+        GEN3_IRQ_RESET(GEN8_DE_PORT_);
+        GEN3_IRQ_RESET(GEN8_DE_MISC_);
+        GEN3_IRQ_RESET(GEN8_PCU_);
 
         if (HAS_PCH_SPLIT(dev_priv))
                 ibx_irq_reset(dev_priv);
@@ -3037,7 +3184,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
         synchronize_irq(dev_priv->drm.irq);
 }
 
-static void cherryview_irq_preinstall(struct drm_device *dev)
+static void cherryview_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -3046,7 +3193,7 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
 
         gen8_gt_irq_reset(dev_priv);
 
-        GEN5_IRQ_RESET(GEN8_PCU_);
+        GEN3_IRQ_RESET(GEN8_PCU_);
 
         spin_lock_irq(&dev_priv->irq_lock);
         if (dev_priv->display_irqs_enabled)
@@ -3111,7 +3258,15 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
-        u32 hotplug;
+        u32 val, hotplug;
+
+        /* Display WA #1179 WaHardHangonHotPlug: cnp */
+        if (HAS_PCH_CNP(dev_priv)) {
+                val = I915_READ(SOUTH_CHICKEN1);
+                val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
+                val |= CHASSIS_CLK_REQ_DURATION(0xf);
+                I915_WRITE(SOUTH_CHICKEN1, val);
+        }
 
         /* Enable digital hotplug on the PCH */
         hotplug = I915_READ(PCH_PORT_HOTPLUG);
@@ -3238,10 +3393,12 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 
         if (HAS_PCH_IBX(dev_priv))
                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
-        else
+        else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
+        else
+                mask = SDE_GMBUS_CPT;
 
-        gen5_assert_iir_is_zero(dev_priv, SDEIIR);
+        gen3_assert_iir_is_zero(dev_priv, SDEIIR);
         I915_WRITE(SDEIMR, ~mask);
 
         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
@@ -3272,7 +3429,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
         }
 
-        GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
+        GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
         if (INTEL_GEN(dev_priv) >= 6) {
                 /*
@@ -3285,7 +3442,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
                 }
 
                 dev_priv->pm_imr = 0xffffffff;
-                GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
+                GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
         }
 }
 
@@ -3296,18 +3453,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
         if (INTEL_GEN(dev_priv) >= 7) {
                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
-                                DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
-                                DE_PLANEB_FLIP_DONE_IVB |
-                                DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
+                                DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
                               DE_DP_A_HOTPLUG_IVB);
         } else {
                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
-                                DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
-                                DE_AUX_CHANNEL_A |
-                                DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
-                                DE_POISON);
+                                DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
+                                DE_PIPEA_CRC_DONE | DE_POISON);
                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
                               DE_DP_A_HOTPLUG);
@@ -3315,11 +3468,9 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
         dev_priv->irq_mask = ~display_mask;
 
-        I915_WRITE(HWSTAM, 0xeffe);
-
         ibx_irq_pre_postinstall(dev);
 
-        GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
+        GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
 
         gen5_gt_irq_postinstall(dev);
 
@@ -3429,15 +3580,13 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
         enum pipe pipe;
 
         if (INTEL_GEN(dev_priv) >= 9) {
-                de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
-                                  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+                de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
                                   GEN9_AUX_CHANNEL_D;
                 if (IS_GEN9_LP(dev_priv))
                         de_port_masked |= BXT_DE_PORT_GMBUS;
         } else {
-                de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
-                                  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+                de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
         }
 
         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
@@ -3460,8 +3609,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
                                           dev_priv->de_irq_mask[pipe],
                                           de_pipe_enables);
 
-        GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
-        GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
+        GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
+        GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
 
         if (IS_GEN9_LP(dev_priv))
                 bxt_hpd_detection_setup(dev_priv);
@@ -3505,98 +3654,36 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
         return 0;
 }
 
-static void gen8_irq_uninstall(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-
-        if (!dev_priv)
-                return;
-
-        gen8_irq_reset(dev);
-}
-
-static void valleyview_irq_uninstall(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-
-        if (!dev_priv)
-                return;
-
-        I915_WRITE(VLV_MASTER_IER, 0);
-        POSTING_READ(VLV_MASTER_IER);
-
-        gen5_gt_irq_reset(dev_priv);
-
-        I915_WRITE(HWSTAM, 0xffffffff);
-
-        spin_lock_irq(&dev_priv->irq_lock);
-        if (dev_priv->display_irqs_enabled)
-                vlv_display_irq_reset(dev_priv);
-        spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static void cherryview_irq_uninstall(struct drm_device *dev)
+static void i8xx_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
 
-        if (!dev_priv)
-                return;
-
-        I915_WRITE(GEN8_MASTER_IRQ, 0);
-        POSTING_READ(GEN8_MASTER_IRQ);
-
-        gen8_gt_irq_reset(dev_priv);
-
-        GEN5_IRQ_RESET(GEN8_PCU_);
-
-        spin_lock_irq(&dev_priv->irq_lock);
-        if (dev_priv->display_irqs_enabled)
-                vlv_display_irq_reset(dev_priv);
-        spin_unlock_irq(&dev_priv->irq_lock);
-}
-
-static void ironlake_irq_uninstall(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
+        i9xx_pipestat_irq_reset(dev_priv);
 
-        if (!dev_priv)
-                return;
-
-        ironlake_irq_reset(dev);
-}
-
-static void i8xx_irq_preinstall(struct drm_device * dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
+        I915_WRITE16(HWSTAM, 0xffff);
 
-        for_each_pipe(dev_priv, pipe)
-                I915_WRITE(PIPESTAT(pipe), 0);
-        I915_WRITE16(IMR, 0xffff);
-        I915_WRITE16(IER, 0x0);
-        POSTING_READ16(IER);
+        GEN2_IRQ_RESET();
 }
 
 static int i8xx_irq_postinstall(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
+        u16 enable_mask;
 
-        I915_WRITE16(EMR,
-                     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
+        I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
+                            I915_ERROR_MEMORY_REFRESH));
 
         /* Unmask the interrupts that we always want on. */
         dev_priv->irq_mask =
                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-                  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-                  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
-        I915_WRITE16(IMR, dev_priv->irq_mask);
+                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
+
+        enable_mask =
+                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+                I915_USER_INTERRUPT;
 
-        I915_WRITE16(IER,
-                     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-                     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-                     I915_USER_INTERRUPT);
-        POSTING_READ16(IER);
+        GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
 
         /* Interrupt setup is already guaranteed to be single-threaded, this is
          * just to make the assert_spin_locked check happy. */
@@ -3608,17 +3695,11 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
         return 0;
 }
 
-/*
- * Returns true when a page flip has completed.
- */
 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
 {
         struct drm_device *dev = arg;
         struct drm_i915_private *dev_priv = to_i915(dev);
-        u16 iir, new_iir;
-        u32 pipe_stats[2];
-        int pipe;
-        irqreturn_t ret;
+        irqreturn_t ret = IRQ_NONE;
 
         if (!intel_irqs_enabled(dev_priv))
                 return IRQ_NONE;
@@ -3626,96 +3707,50 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
         disable_rpm_wakeref_asserts(dev_priv);
 
-        ret = IRQ_NONE;
-        iir = I915_READ16(IIR);
-        if (iir == 0)
-                goto out;
+        do {
+                u32 pipe_stats[I915_MAX_PIPES] = {};
+                u16 iir;
 
-        while (iir) {
-                /* Can't rely on pipestat interrupt bit in iir as it might
-                 * have been cleared after the pipestat interrupt was received.
-                 * It doesn't set the bit in iir again, but it still produces
-                 * interrupts (for non-MSI).
-                 */
-                spin_lock(&dev_priv->irq_lock);
-                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
+                iir = I915_READ16(IIR);
+                if (iir == 0)
+                        break;
 
-                for_each_pipe(dev_priv, pipe) {
-                        i915_reg_t reg = PIPESTAT(pipe);
-                        pipe_stats[pipe] = I915_READ(reg);
+                ret = IRQ_HANDLED;
 
-                        /*
-                         * Clear the PIPE*STAT regs before the IIR
-                         */
-                        if (pipe_stats[pipe] & 0x8000ffff)
-                                I915_WRITE(reg, pipe_stats[pipe]);
-                }
-                spin_unlock(&dev_priv->irq_lock);
+                /* Call regardless, as some status bits might not be
+                 * signalled in iir */
+                i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
                 I915_WRITE16(IIR, iir);
-                new_iir = I915_READ16(IIR); /* Flush posted writes */
 
                 if (iir & I915_USER_INTERRUPT)
                         notify_ring(dev_priv->engine[RCS]);
 
-                for_each_pipe(dev_priv, pipe) {
-                        int plane = pipe;
-                        if (HAS_FBC(dev_priv))
-                                plane = !plane;
-
-                        if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
-                                drm_handle_vblank(&dev_priv->drm, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-                                intel_cpu_fifo_underrun_irq_handler(dev_priv,
-                                                                    pipe);
-                }
+                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
-                iir = new_iir;
-        }
-        ret = IRQ_HANDLED;
+                i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+        } while (0);
 
-out:
         enable_rpm_wakeref_asserts(dev_priv);
 
         return ret;
 }
 
-static void i8xx_irq_uninstall(struct drm_device * dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
-
-        for_each_pipe(dev_priv, pipe) {
-                /* Clear enable bits; then clear status bits */
-                I915_WRITE(PIPESTAT(pipe), 0);
-                I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
-        }
-        I915_WRITE16(IMR, 0xffff);
-        I915_WRITE16(IER, 0x0);
-        I915_WRITE16(IIR, I915_READ16(IIR));
-}
-
-static void i915_irq_preinstall(struct drm_device * dev)
+static void i915_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
 
         if (I915_HAS_HOTPLUG(dev_priv)) {
                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
         }
 
-        I915_WRITE16(HWSTAM, 0xeffe);
-        for_each_pipe(dev_priv, pipe)
-                I915_WRITE(PIPESTAT(pipe), 0);
-        I915_WRITE(IMR, 0xffffffff);
-        I915_WRITE(IER, 0x0);
-        POSTING_READ(IER);
+        i9xx_pipestat_irq_reset(dev_priv);
+
+        I915_WRITE(HWSTAM, 0xffffffff);
+
+        GEN3_IRQ_RESET();
 }
 
 static int i915_irq_postinstall(struct drm_device *dev)
@@ -3723,15 +3758,14 @@ static int i915_irq_postinstall(struct drm_device *dev)
         struct drm_i915_private *dev_priv = to_i915(dev);
         u32 enable_mask;
 
-        I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
+        I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
+                          I915_ERROR_MEMORY_REFRESH));
 
         /* Unmask the interrupts that we always want on. */
         dev_priv->irq_mask =
                 ~(I915_ASLE_INTERRUPT |
                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-                  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-                  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
+                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
 
         enable_mask =
                 I915_ASLE_INTERRUPT |
@@ -3740,20 +3774,13 @@ static int i915_irq_postinstall(struct drm_device *dev)
                 I915_USER_INTERRUPT;
 
         if (I915_HAS_HOTPLUG(dev_priv)) {
-                i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-                POSTING_READ(PORT_HOTPLUG_EN);
-
                 /* Enable in IER... */
                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                 /* and unmask in IMR */
                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
         }
 
-        I915_WRITE(IMR, dev_priv->irq_mask);
-        I915_WRITE(IER, enable_mask);
-        POSTING_READ(IER);
-
-        i915_enable_asle_pipestat(dev_priv);
+        GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
 
         /* Interrupt setup is already guaranteed to be single-threaded, this is
          * just to make the assert_spin_locked check happy. */
@@ -3762,6 +3789,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
         spin_unlock_irq(&dev_priv->irq_lock);
 
+        i915_enable_asle_pipestat(dev_priv);
+
         return 0;
 }
 
@@ -3769,8 +3798,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
 {
         struct drm_device *dev = arg;
         struct drm_i915_private *dev_priv = to_i915(dev);
-        u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
-        int pipe, ret = IRQ_NONE;
+        irqreturn_t ret = IRQ_NONE;
 
         if (!intel_irqs_enabled(dev_priv))
                 return IRQ_NONE;
@@ -3778,131 +3806,56 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
         disable_rpm_wakeref_asserts(dev_priv);
 
-        iir = I915_READ(IIR);
         do {
-                bool irq_received = (iir) != 0;
-                bool blc_event = false;
-
-                /* Can't rely on pipestat interrupt bit in iir as it might
-                 * have been cleared after the pipestat interrupt was received.
-                 * It doesn't set the bit in iir again, but it still produces
-                 * interrupts (for non-MSI).
-                 */
-                spin_lock(&dev_priv->irq_lock);
-                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
-
-                for_each_pipe(dev_priv, pipe) {
-                        i915_reg_t reg = PIPESTAT(pipe);
-                        pipe_stats[pipe] = I915_READ(reg);
-
-                        /* Clear the PIPE*STAT regs before the IIR */
-                        if (pipe_stats[pipe] & 0x8000ffff) {
-                                I915_WRITE(reg, pipe_stats[pipe]);
-                                irq_received = true;
-                        }
-                }
-                spin_unlock(&dev_priv->irq_lock);
+                u32 pipe_stats[I915_MAX_PIPES] = {};
+                u32 hotplug_status = 0;
+                u32 iir;
 
-                if (!irq_received)
+                iir = I915_READ(IIR);
+                if (iir == 0)
                         break;
 
-                /* Consume port.  Then clear IIR or we'll miss events */
+                ret = IRQ_HANDLED;
+
                 if (I915_HAS_HOTPLUG(dev_priv) &&
-                    iir & I915_DISPLAY_PORT_INTERRUPT) {
-                        u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
-                        if (hotplug_status)
-                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
-                }
+                    iir & I915_DISPLAY_PORT_INTERRUPT)
+                        hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+
+                /* Call regardless, as some status bits might not be
+                 * signalled in iir */
+                i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
                 I915_WRITE(IIR, iir);
-                new_iir = I915_READ(IIR); /* Flush posted writes */
 
                 if (iir & I915_USER_INTERRUPT)
                         notify_ring(dev_priv->engine[RCS]);
 
-                for_each_pipe(dev_priv, pipe) {
-                        int plane = pipe;
-                        if (HAS_FBC(dev_priv))
-                                plane = !plane;
-
-                        if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
-                                drm_handle_vblank(&dev_priv->drm, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
-                                blc_event = true;
-
-                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-                                intel_cpu_fifo_underrun_irq_handler(dev_priv,
-                                                                    pipe);
-                }
+                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
-                if (blc_event || (iir & I915_ASLE_INTERRUPT))
-                        intel_opregion_asle_intr(dev_priv);
+                if (hotplug_status)
+                        i9xx_hpd_irq_handler(dev_priv, hotplug_status);
 
-                /* With MSI, interrupts are only generated when iir
-                 * transitions from zero to nonzero.  If another bit got
-                 * set while we were handling the existing iir bits, then
-                 * we would never get another interrupt.
-                 *
-                 * This is fine on non-MSI as well, as if we hit this path
-                 * we avoid exiting the interrupt handler only to generate
-                 * another one.
-                 *
-                 * Note that for MSI this could cause a stray interrupt report
-                 * if an interrupt landed in the time between writing IIR and
-                 * the posting read.  This should be rare enough to never
-                 * trigger the 99% of 100,000 interrupts test for disabling
-                 * stray interrupts.
-                 */
-                ret = IRQ_HANDLED;
-                iir = new_iir;
-        } while (iir);
+                i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+        } while (0);
 
         enable_rpm_wakeref_asserts(dev_priv);
 
         return ret;
 }
 
-static void i915_irq_uninstall(struct drm_device * dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
-
-        if (I915_HAS_HOTPLUG(dev_priv)) {
-                i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-                I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
-        }
-
-        I915_WRITE16(HWSTAM, 0xffff);
-        for_each_pipe(dev_priv, pipe) {
-                /* Clear enable bits; then clear status bits */
-                I915_WRITE(PIPESTAT(pipe), 0);
-                I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
-        }
-        I915_WRITE(IMR, 0xffffffff);
-        I915_WRITE(IER, 0x0);
-
-        I915_WRITE(IIR, I915_READ(IIR));
-}
-
-static void i965_irq_preinstall(struct drm_device * dev)
+static void i965_irq_reset(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
 
         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
-        I915_WRITE(HWSTAM, 0xeffe);
-        for_each_pipe(dev_priv, pipe)
-                I915_WRITE(PIPESTAT(pipe), 0);
-        I915_WRITE(IMR, 0xffffffff);
-        I915_WRITE(IER, 0x0);
-        POSTING_READ(IER);
+        i9xx_pipestat_irq_reset(dev_priv);
+
+        I915_WRITE(HWSTAM, 0xffffffff);
+
+        GEN3_IRQ_RESET();
 }
 
 static int i965_irq_postinstall(struct drm_device *dev)
@@ -3911,31 +3864,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
         u32 enable_mask;
         u32 error_mask;
 
-        /* Unmask the interrupts that we always want on. */
-        dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
-                               I915_DISPLAY_PORT_INTERRUPT |
-                               I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-                               I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-                               I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-                               I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
-                               I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
-
-        enable_mask = ~dev_priv->irq_mask;
-        enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
-                         I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
-        enable_mask |= I915_USER_INTERRUPT;
-
-        if (IS_G4X(dev_priv))
-                enable_mask |= I915_BSD_USER_INTERRUPT;
-
-        /* Interrupt setup is already guaranteed to be single-threaded, this is
-         * just to make the assert_spin_locked check happy. */
-        spin_lock_irq(&dev_priv->irq_lock);
-        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
-        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
-        spin_unlock_irq(&dev_priv->irq_lock);
-
         /*
          * Enable some error detection, note the instruction error mask
          * bit is reserved, so we leave it masked.
@@ -3951,12 +3879,34 @@ static int i965_irq_postinstall(struct drm_device *dev)
         }
         I915_WRITE(EMR, error_mask);
 
-        I915_WRITE(IMR, dev_priv->irq_mask);
-        I915_WRITE(IER, enable_mask);
-        POSTING_READ(IER);
+        /* Unmask the interrupts that we always want on. */
+        dev_priv->irq_mask =
+                ~(I915_ASLE_INTERRUPT |
+                  I915_DISPLAY_PORT_INTERRUPT |
+                  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+                  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+                  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 
-        i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-        POSTING_READ(PORT_HOTPLUG_EN);
+        enable_mask =
+                I915_ASLE_INTERRUPT |
+                I915_DISPLAY_PORT_INTERRUPT |
+                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
+                I915_USER_INTERRUPT;
+
+        if (IS_G4X(dev_priv))
+                enable_mask |= I915_BSD_USER_INTERRUPT;
+
+        GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+
+        /* Interrupt setup is already guaranteed to be single-threaded, this is
+         * just to make the assert_spin_locked check happy. */
+        spin_lock_irq(&dev_priv->irq_lock);
+        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
+        i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
+        i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
+        spin_unlock_irq(&dev_priv->irq_lock);
 
         i915_enable_asle_pipestat(dev_priv);
 
@@ -3992,9 +3942,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 {
         struct drm_device *dev = arg;
         struct drm_i915_private *dev_priv = to_i915(dev);
-        u32 iir, new_iir;
-        u32 pipe_stats[I915_MAX_PIPES];
-        int ret = IRQ_NONE, pipe;
+        irqreturn_t ret = IRQ_NONE;
 
         if (!intel_irqs_enabled(dev_priv))
                 return IRQ_NONE;
@@ -4002,121 +3950,46 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
         disable_rpm_wakeref_asserts(dev_priv);
 
-        iir = I915_READ(IIR);
-
-        for (;;) {
-                bool irq_received = (iir) != 0;
-                bool blc_event = false;
-
-                /* Can't rely on pipestat interrupt bit in iir as it might
-                 * have been cleared after the pipestat interrupt was received.
-                 * It doesn't set the bit in iir again, but it still produces
-                 * interrupts (for non-MSI).
-                 */
-                spin_lock(&dev_priv->irq_lock);
-                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
-
-                for_each_pipe(dev_priv, pipe) {
-                        i915_reg_t reg = PIPESTAT(pipe);
-                        pipe_stats[pipe] = I915_READ(reg);
-
-                        /*
-                         * Clear the PIPE*STAT regs before the IIR
-                         */
-                        if (pipe_stats[pipe] & 0x8000ffff) {
-                                I915_WRITE(reg, pipe_stats[pipe]);
-                                irq_received = true;
-                        }
-                }
-                spin_unlock(&dev_priv->irq_lock);
+        do {
+                u32 pipe_stats[I915_MAX_PIPES] = {};
+                u32 hotplug_status = 0;
+                u32 iir;
 
-                if (!irq_received)
+                iir = I915_READ(IIR);
+                if (iir == 0)
                         break;
 
                 ret = IRQ_HANDLED;
 
-                /* Consume port.  Then clear IIR or we'll miss events */
-                if (iir & I915_DISPLAY_PORT_INTERRUPT) {
-                        u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
-                        if (hotplug_status)
-                                i9xx_hpd_irq_handler(dev_priv, hotplug_status);
-                }
+                if (iir & I915_DISPLAY_PORT_INTERRUPT)
+                        hotplug_status = i9xx_hpd_irq_ack(dev_priv);
+
+                /* Call regardless, as some status bits might not be
+                 * signalled in iir */
+                i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
 
                 I915_WRITE(IIR, iir);
-                new_iir = I915_READ(IIR); /* Flush posted writes */
 
                 if (iir & I915_USER_INTERRUPT)
                         notify_ring(dev_priv->engine[RCS]);
+
                 if (iir & I915_BSD_USER_INTERRUPT)
                         notify_ring(dev_priv->engine[VCS]);
 
-                for_each_pipe(dev_priv, pipe) {
-                        if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
-                                drm_handle_vblank(&dev_priv->drm, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
-                                blc_event = true;
-
-                        if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-                                i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-
-                        if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-                                intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
-                }
-
-                if (blc_event || (iir & I915_ASLE_INTERRUPT))
-                        intel_opregion_asle_intr(dev_priv);
+                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
+                        DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
 
-                if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
-                        gmbus_irq_handler(dev_priv);
+                if (hotplug_status)
+                        i9xx_hpd_irq_handler(dev_priv, hotplug_status);
 
-                /* With MSI, interrupts are only generated when iir
-                 * transitions from zero to nonzero.  If another bit got
-                 * set while we were handling the existing iir bits, then
-                 * we would never get another interrupt.
-                 *
-                 * This is fine on non-MSI as well, as if we hit this path
-                 * we avoid exiting the interrupt handler only to generate
-                 * another one.
-                 *
-                 * Note that for MSI this could cause a stray interrupt report
-                 * if an interrupt landed in the time between writing IIR and
-                 * the posting read.  This should be rare enough to never
-                 * trigger the 99% of 100,000 interrupts test for disabling
-                 * stray interrupts.
-                 */
-                iir = new_iir;
-        }
+                i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
+        } while (0);
 
         enable_rpm_wakeref_asserts(dev_priv);
 
         return ret;
 }
 
-static void i965_irq_uninstall(struct drm_device * dev)
-{
-        struct drm_i915_private *dev_priv = to_i915(dev);
-        int pipe;
-
-        if (!dev_priv)
-                return;
-
-        i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-        I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
-
-        I915_WRITE(HWSTAM, 0xffffffff);
-        for_each_pipe(dev_priv, pipe)
-                I915_WRITE(PIPESTAT(pipe), 0);
-        I915_WRITE(IMR, 0xffffffff);
-        I915_WRITE(IER, 0x0);
-
-        for_each_pipe(dev_priv, pipe)
-                I915_WRITE(PIPESTAT(pipe),
-                           I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
-        I915_WRITE(IIR, I915_READ(IIR));
-}
-
 /**
  * intel_irq_init - initializes irq support
  * @dev_priv: i915 device instance
@@ -4197,17 +4070,17 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 
         if (IS_CHERRYVIEW(dev_priv)) {
                 dev->driver->irq_handler = cherryview_irq_handler;
-                dev->driver->irq_preinstall = cherryview_irq_preinstall;
+                dev->driver->irq_preinstall = cherryview_irq_reset;
                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
-                dev->driver->irq_uninstall = cherryview_irq_uninstall;
+                dev->driver->irq_uninstall = cherryview_irq_reset;
                 dev->driver->enable_vblank = i965_enable_vblank;
                 dev->driver->disable_vblank = i965_disable_vblank;
                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
         } else if (IS_VALLEYVIEW(dev_priv)) {
                 dev->driver->irq_handler = valleyview_irq_handler;
-                dev->driver->irq_preinstall = valleyview_irq_preinstall;
+                dev->driver->irq_preinstall = valleyview_irq_reset;
                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
-                dev->driver->irq_uninstall = valleyview_irq_uninstall;
+                dev->driver->irq_uninstall = valleyview_irq_reset;
                 dev->driver->enable_vblank = i965_enable_vblank;
                 dev->driver->disable_vblank = i965_disable_vblank;
                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
@@ -4215,7 +4088,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                 dev->driver->irq_handler = gen8_irq_handler;
                 dev->driver->irq_preinstall = gen8_irq_reset;
                 dev->driver->irq_postinstall = gen8_irq_postinstall;
-                dev->driver->irq_uninstall = gen8_irq_uninstall;
+                dev->driver->irq_uninstall = gen8_irq_reset;
                 dev->driver->enable_vblank = gen8_enable_vblank;
                 dev->driver->disable_vblank = gen8_disable_vblank;
                 if (IS_GEN9_LP(dev_priv))
@@ -4229,29 +4102,29 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                 dev->driver->irq_handler = ironlake_irq_handler;
                 dev->driver->irq_preinstall = ironlake_irq_reset;
                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
-                dev->driver->irq_uninstall = ironlake_irq_uninstall;
+                dev->driver->irq_uninstall = ironlake_irq_reset;
                 dev->driver->enable_vblank = ironlake_enable_vblank;
                 dev->driver->disable_vblank = ironlake_disable_vblank;
                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
         } else {
                 if (IS_GEN2(dev_priv)) {
-                        dev->driver->irq_preinstall = i8xx_irq_preinstall;
+                        dev->driver->irq_preinstall = i8xx_irq_reset;
                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
                         dev->driver->irq_handler = i8xx_irq_handler;
-                        dev->driver->irq_uninstall = i8xx_irq_uninstall;
+                        dev->driver->irq_uninstall = i8xx_irq_reset;
                         dev->driver->enable_vblank = i8xx_enable_vblank;
                         dev->driver->disable_vblank = i8xx_disable_vblank;
                 } else if (IS_GEN3(dev_priv)) {
-                        dev->driver->irq_preinstall = i915_irq_preinstall;
+                        dev->driver->irq_preinstall = i915_irq_reset;
                         dev->driver->irq_postinstall = i915_irq_postinstall;
-                        dev->driver->irq_uninstall = i915_irq_uninstall;
+                        dev->driver->irq_uninstall = i915_irq_reset;
                         dev->driver->irq_handler = i915_irq_handler;
                         dev->driver->enable_vblank = i8xx_enable_vblank;
                         dev->driver->disable_vblank = i8xx_disable_vblank;
                 } else {
-                        dev->driver->irq_preinstall = i965_irq_preinstall;
+                        dev->driver->irq_preinstall = i965_irq_reset;
                         dev->driver->irq_postinstall = i965_irq_postinstall;
-                        dev->driver->irq_uninstall = i965_irq_uninstall;
+                        dev->driver->irq_uninstall = i965_irq_reset;
                         dev->driver->irq_handler = i965_irq_handler;
                         dev->driver->enable_vblank = i965_enable_vblank;
                         dev->driver->disable_vblank = i965_disable_vblank;
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.c b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
new file mode 100644
index 000000000000..368c87d7ee9a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.c
@@ -0,0 +1,109 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_cflgt2.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+        { _MMIO(0x2740), 0x00000000 },
+        { _MMIO(0x2744), 0x00800000 },
+        { _MMIO(0x2714), 0xf0800000 },
+        { _MMIO(0x2710), 0x00000000 },
+        { _MMIO(0x2724), 0xf0800000 },
+        { _MMIO(0x2720), 0x00000000 },
+        { _MMIO(0x2770), 0x00000004 },
+        { _MMIO(0x2774), 0x00000000 },
+        { _MMIO(0x2778), 0x00000003 },
+        { _MMIO(0x277c), 0x00000000 },
+        { _MMIO(0x2780), 0x00000007 },
+        { _MMIO(0x2784), 0x00000000 },
+        { _MMIO(0x2788), 0x00100002 },
+        { _MMIO(0x278c), 0x0000fff7 },
+        { _MMIO(0x2790), 0x00100002 },
+        { _MMIO(0x2794), 0x0000ffcf },
+        { _MMIO(0x2798), 0x00100082 },
+        { _MMIO(0x279c), 0x0000ffef },
+        { _MMIO(0x27a0), 0x001000c2 },
+        { _MMIO(0x27a4), 0x0000ffe7 },
+        { _MMIO(0x27a8), 0x00100001 },
+        { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+        { _MMIO(0x9840), 0x00000080 },
+        { _MMIO(0x9888), 0x11810000 },
+        { _MMIO(0x9888), 0x07810013 },
+        { _MMIO(0x9888), 0x1f810000 },
+        { _MMIO(0x9888), 0x1d810000 },
+        { _MMIO(0x9888), 0x1b930040 },
+        { _MMIO(0x9888), 0x07e54000 },
+        { _MMIO(0x9888), 0x1f908000 },
+        { _MMIO(0x9888), 0x11900000 },
+        { _MMIO(0x9888), 0x37900000 },
+        { _MMIO(0x9888), 0x53900000 },
+        { _MMIO(0x9888), 0x45900000 },
+        { _MMIO(0x9888), 0x33900000 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv)
+{
+        strncpy(dev_priv->perf.oa.test_config.uuid,
+                "74fb4902-d3d3-4237-9e90-cbdc68d0a446",
+                UUID_STRING_LEN);
+        dev_priv->perf.oa.test_config.id = 1;
+
+        dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
+        dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
+
+        dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
+        dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
+
+        dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
+        dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
+
+        dev_priv->perf.oa.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
+        dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
+
+        dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
+
+        dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
+        dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
+        dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt2.h b/drivers/gpu/drm/i915/i915_oa_cflgt2.h
new file mode 100644
index 000000000000..1f3268ef2ea2
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt2.h
@@ -0,0 +1,34 @@
+/*
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ *
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_CFLGT2_H__
+#define __I915_OA_CFLGT2_H__
+
+extern void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 8ab003dca113..9dff323a83d3 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -25,235 +25,171 @@
 #include "i915_params.h"
 #include "i915_drv.h"
 
-struct i915_params i915 __read_mostly = {
-        .modeset = -1,
-        .panel_ignore_lid = 1,
-        .semaphores = -1,
-        .lvds_channel_mode = 0,
-        .panel_use_ssc = -1,
-        .vbt_sdvo_panel_type = -1,
-        .enable_rc6 = -1,
-        .enable_dc = -1,
-        .enable_fbc = -1,
-        .enable_execlists = -1,
-        .enable_hangcheck = true,
-        .enable_ppgtt = -1,
-        .enable_psr = -1,
-        .alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT),
-        .disable_power_well = -1,
-        .enable_ips = 1,
-        .fastboot = 0,
-        .prefault_disable = 0,
-        .load_detect_test = 0,
-        .force_reset_modeset_test = 0,
-        .reset = 2,
-        .error_capture = true,
-        .invert_brightness = 0,
-        .disable_display = 0,
-        .enable_cmd_parser = true,
-        .use_mmio_flip = 0,
-        .mmio_debug = 0,
-        .verbose_state_checks = 1,
-        .nuclear_pageflip = 0,
-        .edp_vswing = 0,
-        .enable_guc_loading = 0,
-        .enable_guc_submission = 0,
-        .guc_log_level = -1,
-        .guc_firmware_path = NULL,
-        .huc_firmware_path = NULL,
-        .enable_dp_mst = true,
-        .inject_load_failure = 0,
-        .enable_dpcd_backlight = false,
-        .enable_gvt = false,
+#define i915_param_named(name, T, perm, desc) \
+        module_param_named(name, i915_modparams.name, T, perm); \
+        MODULE_PARM_DESC(name, desc)
+#define i915_param_named_unsafe(name, T, perm, desc) \
+        module_param_named_unsafe(name, i915_modparams.name, T, perm); \
+        MODULE_PARM_DESC(name, desc)
+
+struct i915_params i915_modparams __read_mostly = {
+#define MEMBER(T, member, value) .member = (value),
+        I915_PARAMS_FOR_EACH(MEMBER)
+#undef MEMBER
 };
 
-module_param_named(modeset, i915.modeset, int, 0400);
-MODULE_PARM_DESC(modeset,
+i915_param_named(modeset, int, 0400,
         "Use kernel modesetting [KMS] (0=disable, "
         "1=on, -1=force vga console preference [default])");
 
-module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, 0600);
-MODULE_PARM_DESC(panel_ignore_lid,
+i915_param_named_unsafe(panel_ignore_lid, int, 0600,
         "Override lid status (0=autodetect, 1=autodetect disabled [default], "
         "-1=force lid closed, -2=force lid open)");
 
-module_param_named_unsafe(semaphores, i915.semaphores, int, 0400);
-MODULE_PARM_DESC(semaphores,
+i915_param_named_unsafe(semaphores, int, 0400,
         "Use semaphores for inter-ring sync "
         "(default: -1 (use per-chip defaults))");
 
-module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400);
-MODULE_PARM_DESC(enable_rc6,
+i915_param_named_unsafe(enable_rc6, int, 0400,
         "Enable power-saving render C-state 6. "
         "Different stages can be selected via bitmask values "
         "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
         "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
         "default: -1 (use per-chip default)");
 
-module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400);
-MODULE_PARM_DESC(enable_dc,
+i915_param_named_unsafe(enable_dc, int, 0400,
         "Enable power-saving display C-states. "
         "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
 
-module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
-MODULE_PARM_DESC(enable_fbc,
+i915_param_named_unsafe(enable_fbc, int, 0600,
         "Enable frame buffer compression for power savings "
         "(default: -1 (use per-chip default))");
 
-module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, 0400);
-MODULE_PARM_DESC(lvds_channel_mode,
+i915_param_named_unsafe(lvds_channel_mode, int, 0400,
          "Specify LVDS channel mode "
          "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
 
-module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, 0600);
-MODULE_PARM_DESC(lvds_use_ssc,
+i915_param_named_unsafe(panel_use_ssc, int, 0600,
         "Use Spread Spectrum Clock with panels [LVDS/eDP] "
         "(default: auto from VBT)");
 
-module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, 0400);
-MODULE_PARM_DESC(vbt_sdvo_panel_type,
+i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
         "Override/Ignore selection of SDVO panel mode in the VBT "
         "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
-module_param_named_unsafe(reset, i915.reset, int, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
+i915_param_named_unsafe(reset, int, 0600,
+        "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
 
-module_param_named_unsafe(vbt_firmware, i915.vbt_firmware, charp, 0400);
-MODULE_PARM_DESC(vbt_firmware,
-                 "Load VBT from specified file under /lib/firmware");
+i915_param_named_unsafe(vbt_firmware, charp, 0400,
+        "Load VBT from specified file under /lib/firmware");
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
-module_param_named(error_capture, i915.error_capture, bool, 0600);
-MODULE_PARM_DESC(error_capture,
+i915_param_named(error_capture, bool, 0600,
         "Record the GPU state following a hang. "
         "This information in /sys/class/drm/card<N>/error is vital for "
         "triaging and debugging hangs.");
 #endif
 
-module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644);
-MODULE_PARM_DESC(enable_hangcheck,
+i915_param_named_unsafe(enable_hangcheck, bool, 0644,
         "Periodically check GPU activity for detecting hangs. "
         "WARNING: Disabling this can cause system wide hangs. "
         "(default: true)");
 
-module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
-MODULE_PARM_DESC(enable_ppgtt,
+i915_param_named_unsafe(enable_ppgtt, int, 0400,
         "Override PPGTT usage. "
         "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
 
-module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
-MODULE_PARM_DESC(enable_execlists,
+i915_param_named_unsafe(enable_execlists, int, 0400,
         "Override execlists usage. "
         "(-1=auto [default], 0=disabled, 1=enabled)");
 
-module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
-MODULE_PARM_DESC(enable_psr, "Enable PSR "
-                 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
-                 "Default: -1 (use per-chip default)");
+i915_param_named_unsafe(enable_psr, int, 0600,
+        "Enable PSR "
+        "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
+        "Default: -1 (use per-chip default)");
 
-module_param_named_unsafe(alpha_support, i915.alpha_support, bool, 0400);
-MODULE_PARM_DESC(alpha_support,
+i915_param_named_unsafe(alpha_support, bool, 0400,
         "Enable alpha quality driver support for latest hardware. "
         "See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
 
-module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400);
-MODULE_PARM_DESC(disable_power_well,
+i915_param_named_unsafe(disable_power_well, int, 0400,
         "Disable display power wells when possible "
         "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
 
-module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
-MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
+i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
 
-module_param_named(fastboot, i915.fastboot, bool, 0600);
-MODULE_PARM_DESC(fastboot,
+i915_param_named(fastboot, bool, 0600,
         "Try to skip unnecessary mode sets at boot time (default: false)");
 
-module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600);
-MODULE_PARM_DESC(prefault_disable,
+i915_param_named_unsafe(prefault_disable, bool, 0600,
         "Disable page prefaulting for pread/pwrite/reloc (default:false). "
         "For developers only.");
 
-module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600);
-MODULE_PARM_DESC(load_detect_test,
+i915_param_named_unsafe(load_detect_test, bool, 0600,
         "Force-enable the VGA load detect code for testing (default:false). "
         "For developers only.");
 
-module_param_named_unsafe(force_reset_modeset_test, i915.force_reset_modeset_test, bool, 0600);
-MODULE_PARM_DESC(force_reset_modeset_test,
+i915_param_named_unsafe(force_reset_modeset_test, bool, 0600,
         "Force a modeset during gpu reset for testing (default:false). "
         "For developers only.");
 
-module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, 0600);
-MODULE_PARM_DESC(invert_brightness,
+i915_param_named_unsafe(invert_brightness, int, 0600,
         "Invert backlight brightness "
         "(-1 force normal, 0 machine defaults, 1 force inversion), please "
         "report PCI device ID, subsystem vendor and subsystem device ID "
         "to dri-devel@lists.freedesktop.org, if your machine needs it. "
         "It will then be included in an upcoming module version.");
 
-module_param_named(disable_display, i915.disable_display, bool, 0400);
-MODULE_PARM_DESC(disable_display, "Disable display (default: false)");
+i915_param_named(disable_display, bool, 0400,
+        "Disable display (default: false)");
 
-module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, bool, 0400);
-MODULE_PARM_DESC(enable_cmd_parser,
-                 "Enable command parsing (true=enabled [default], false=disabled)");
+i915_param_named_unsafe(enable_cmd_parser, bool, 0400,
+        "Enable command parsing (true=enabled [default], false=disabled)");
 
-module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600);
-MODULE_PARM_DESC(use_mmio_flip,
-                 "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)");
+i915_param_named_unsafe(use_mmio_flip, int, 0600,
+        "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)");
 
-module_param_named(mmio_debug, i915.mmio_debug, int, 0600);
-MODULE_PARM_DESC(mmio_debug,
+i915_param_named(mmio_debug, int, 0600,
         "Enable the MMIO debug code for the first N failures (default: off). "
         "This may negatively affect performance.");
 
-module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600);
-MODULE_PARM_DESC(verbose_state_checks,
+i915_param_named(verbose_state_checks, bool, 0600,
         "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.");
 
-module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0400);
-MODULE_PARM_DESC(nuclear_pageflip,
-                 "Force enable atomic functionality on platforms that don't have full support yet.");
+i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
+        "Force enable atomic functionality on platforms that don't have full support yet.");
 
 /* WA to get away with the default setting in VBT for early platforms.Will be removed */
-module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400);
-MODULE_PARM_DESC(edp_vswing,
-                 "Ignore/Override vswing pre-emph table selection from VBT "
-                 "(0=use value from vbt [default], 1=low power swing(200mV),"
-                 "2=default swing(400mV))");
-
-module_param_named_unsafe(enable_guc_loading, i915.enable_guc_loading, int, 0400);
-MODULE_PARM_DESC(enable_guc_loading,
-                "Enable GuC firmware loading "
-                "(-1=auto, 0=never [default], 1=if available, 2=required)");
-
-module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, int, 0400);
-MODULE_PARM_DESC(enable_guc_submission,
-                "Enable GuC submission "
-                "(-1=auto, 0=never [default], 1=if available, 2=required)");
-
-module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
-MODULE_PARM_DESC(guc_log_level,
+i915_param_named_unsafe(edp_vswing, int, 0400,
+        "Ignore/Override vswing pre-emph table selection from VBT "
+        "(0=use value from vbt [default], 1=low power swing(200mV),"
+        "2=default swing(400mV))");
+
+i915_param_named_unsafe(enable_guc_loading, int, 0400,
+        "Enable GuC firmware loading "
+        "(-1=auto, 0=never [default], 1=if available, 2=required)");
+
+i915_param_named_unsafe(enable_guc_submission, int, 0400,
+        "Enable GuC submission "
+        "(-1=auto, 0=never [default], 1=if available, 2=required)");
+
+i915_param_named(guc_log_level, int, 0400,
         "GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
 
-module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp, 0400);
-MODULE_PARM_DESC(guc_firmware_path,
+i915_param_named_unsafe(guc_firmware_path, charp, 0400,
         "GuC firmware path to use instead of the default one");
 
-module_param_named_unsafe(huc_firmware_path, i915.huc_firmware_path, charp, 0400);
-MODULE_PARM_DESC(huc_firmware_path,
+i915_param_named_unsafe(huc_firmware_path, charp, 0400,
         "HuC firmware path to use instead of the default one");
 
-module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600);
-MODULE_PARM_DESC(enable_dp_mst,
+i915_param_named_unsafe(enable_dp_mst, bool, 0600,
         "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)");
-module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
-MODULE_PARM_DESC(inject_load_failure,
+
+i915_param_named_unsafe(inject_load_failure, uint, 0400,
         "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
-module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600);
-MODULE_PARM_DESC(enable_dpcd_backlight,
+
+i915_param_named(enable_dpcd_backlight, bool, 0600,
         "Enable support for DPCD backlight control (default:false)");
 
-module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
-MODULE_PARM_DESC(enable_gvt,
+i915_param_named(enable_gvt, bool, 0400,
         "Enable support for Intel GVT-g graphics virtualization host support(default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index ac844709c97e..4f3f8d650194 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -27,56 +27,56 @@
 
 #include <linux/cache.h> /* for __read_mostly */
 
-#define I915_PARAMS_FOR_EACH(func) \
-        func(char *, vbt_firmware); \
-        func(int, modeset); \
-        func(int, panel_ignore_lid); \
-        func(int, semaphores); \
-        func(int, lvds_channel_mode); \
-        func(int, panel_use_ssc); \
-        func(int, vbt_sdvo_panel_type); \
-        func(int, enable_rc6); \
-        func(int, enable_dc); \
-        func(int, enable_fbc); \
-        func(int, enable_ppgtt); \
-        func(int, enable_execlists); \
-        func(int, enable_psr); \
-        func(int, disable_power_well); \
-        func(int, enable_ips); \
-        func(int, invert_brightness); \
-        func(int, enable_guc_loading); \
-        func(int, enable_guc_submission); \
-        func(int, guc_log_level); \
-        func(char *, guc_firmware_path); \
-        func(char *, huc_firmware_path); \
-        func(int, use_mmio_flip); \
-        func(int, mmio_debug); \
-        func(int, edp_vswing); \
-        func(int, reset); \
-        func(unsigned int, inject_load_failure); \
+#define I915_PARAMS_FOR_EACH(param) \
+        param(char *, vbt_firmware, NULL) \
+        param(int, modeset, -1) \
+        param(int, panel_ignore_lid, 1) \
+        param(int, semaphores, -1) \
+        param(int, lvds_channel_mode, 0) \
+        param(int, panel_use_ssc, -1) \
+        param(int, vbt_sdvo_panel_type, -1) \
+        param(int, enable_rc6, -1) \
+        param(int, enable_dc, -1) \
+        param(int, enable_fbc, -1) \
+        param(int, enable_ppgtt, -1) \
+        param(int, enable_execlists, -1) \
+        param(int, enable_psr, -1) \
+        param(int, disable_power_well, -1) \
+        param(int, enable_ips, 1) \
+        param(int, invert_brightness, 0) \
+        param(int, enable_guc_loading, 0) \
+        param(int, enable_guc_submission, 0) \
+        param(int, guc_log_level, -1) \
+        param(char *, guc_firmware_path, NULL) \
+        param(char *, huc_firmware_path, NULL) \
+        param(int, use_mmio_flip, 0) \
+        param(int, mmio_debug, 0) \
+        param(int, edp_vswing, 0) \
+        param(int, reset, 2) \
+        param(unsigned int, inject_load_failure, 0) \
         /* leave bools at the end to not create holes */ \
-        func(bool, alpha_support); \
-        func(bool, enable_cmd_parser); \
-        func(bool, enable_hangcheck); \
-        func(bool, fastboot); \
-        func(bool, prefault_disable); \
-        func(bool, load_detect_test); \
-        func(bool, force_reset_modeset_test); \
-        func(bool, error_capture); \
-        func(bool, disable_display); \
-        func(bool, verbose_state_checks); \
-        func(bool, nuclear_pageflip); \
-        func(bool, enable_dp_mst); \
-        func(bool, enable_dpcd_backlight); \
-        func(bool, enable_gvt)
+        param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
+        param(bool, enable_cmd_parser, true) \
+        param(bool, enable_hangcheck, true) \
+        param(bool, fastboot, false) \
+        param(bool, prefault_disable, false) \
+        param(bool, load_detect_test, false) \
+        param(bool, force_reset_modeset_test, false) \
+        param(bool, error_capture, true) \
+        param(bool, disable_display, false) \
+        param(bool, verbose_state_checks, true) \
+        param(bool, nuclear_pageflip, false) \
+        param(bool, enable_dp_mst, true) \
+        param(bool, enable_dpcd_backlight, false) \
+        param(bool, enable_gvt, false)
 
-#define MEMBER(T, member) T member
+#define MEMBER(T, member, ...) T member;
 struct i915_params {
         I915_PARAMS_FOR_EACH(MEMBER);
 };
 #undef MEMBER
 
-extern struct i915_params i915 __read_mostly;
+extern struct i915_params i915_modparams __read_mostly;
 
 #endif
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 881b5d6708aa..da60866b6628 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -168,6 +168,7 @@ static const struct intel_device_info intel_i965g_info __initconst = {
         .platform = INTEL_I965G,
         .has_overlay = 1,
         .hws_needs_physical = 1,
+        .has_snoop = false,
 };
 
 static const struct intel_device_info intel_i965gm_info __initconst = {
@@ -177,6 +178,7 @@ static const struct intel_device_info intel_i965gm_info __initconst = {
         .has_overlay = 1,
         .supports_tv = 1,
         .hws_needs_physical = 1,
+        .has_snoop = false,
 };
 
 static const struct intel_device_info intel_g45_info __initconst = {
@@ -198,7 +200,6 @@ static const struct intel_device_info intel_gm45_info __initconst = {
 #define GEN5_FEATURES \
         .gen = 5, .num_pipes = 2, \
         .has_hotplug = 1, \
-        .has_gmbus_irq = 1, \
         .ring_mask = RENDER_RING | BSD_RING, \
         .has_snoop = true, \
         GEN_DEFAULT_PIPEOFFSETS, \
@@ -223,7 +224,6 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = {
         .has_llc = 1, \
         .has_rc6 = 1, \
         .has_rc6p = 1, \
-        .has_gmbus_irq = 1, \
         .has_aliasing_ppgtt = 1, \
         GEN_DEFAULT_PIPEOFFSETS, \
         CURSOR_OFFSETS
@@ -266,7 +266,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst =
         .has_llc = 1, \
         .has_rc6 = 1, \
         .has_rc6p = 1, \
-        .has_gmbus_irq = 1, \
         .has_aliasing_ppgtt = 1, \
         .has_full_ppgtt = 1, \
         GEN_DEFAULT_PIPEOFFSETS, \
@@ -319,7 +318,6 @@ static const struct intel_device_info intel_valleyview_info __initconst = {
         .has_psr = 1,
         .has_runtime_pm = 1,
         .has_rc6 = 1,
-        .has_gmbus_irq = 1,
         .has_gmch_display = 1,
         .has_hotplug = 1,
         .has_aliasing_ppgtt = 1,
@@ -410,7 +408,6 @@ static const struct intel_device_info intel_cherryview_info __initconst = {
         .has_runtime_pm = 1,
         .has_resource_streamer = 1,
         .has_rc6 = 1,
-        .has_gmbus_irq = 1,
         .has_logical_ring_contexts = 1,
         .has_gmch_display = 1,
         .has_aliasing_ppgtt = 1,
@@ -472,7 +469,6 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = {
         .has_resource_streamer = 1, \
         .has_rc6 = 1, \
         .has_dp_mst = 1, \
-        .has_gmbus_irq = 1, \
         .has_logical_ring_contexts = 1, \
         .has_guc = 1, \
         .has_aliasing_ppgtt = 1, \
@@ -480,6 +476,7 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = {
         .has_full_48bit_ppgtt = 1, \
         .has_reset_engine = 1, \
         .has_snoop = true, \
+        .has_ipc = 1, \
         GEN_DEFAULT_PIPEOFFSETS, \
         IVB_CURSOR_OFFSETS, \
         BDW_COLORS
@@ -503,6 +500,7 @@ static const struct intel_device_info intel_geminilake_info __initconst = {
         .platform = INTEL_KABYLAKE, \
         .has_csr = 1, \
         .has_guc = 1, \
+        .has_ipc = 1, \
         .ddb_size = 896
 
 static const struct intel_device_info intel_kabylake_gt1_info __initconst = {
@@ -522,12 +520,12 @@ static const struct intel_device_info intel_kabylake_gt3_info __initconst = {
 };
 
 #define CFL_PLATFORM \
-        .is_alpha_support = 1, \
         BDW_FEATURES, \
         .gen = 9, \
         .platform = INTEL_COFFEELAKE, \
         .has_csr = 1, \
         .has_guc = 1, \
+        .has_ipc = 1, \
         .ddb_size = 896
 
 static const struct intel_device_info intel_coffeelake_gt1_info __initconst = {
@@ -554,6 +552,7 @@ static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
         .gt = 2,
         .ddb_size = 1024,
         .has_csr = 1,
+        .has_ipc = 1,
         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 };
 
@@ -632,7 +631,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 (struct intel_device_info *) ent->driver_data;
         int err;
 
-        if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
+        if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
                          "to enable support in this kernel version, or check for kernel updates.\n");
@@ -690,10 +689,10 @@ static int __init i915_init(void)
          * vga_text_mode_force boot option.
          */
 
-        if (i915.modeset == 0)
+        if (i915_modparams.modeset == 0)
                 use_kms = false;
 
-        if (vgacon_text_force() && i915.modeset == -1)
+        if (vgacon_text_force() && i915_modparams.modeset == -1)
                 use_kms = false;
 
         if (!use_kms) {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 94185d610673..1383a2995a69 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -206,6 +206,7 @@
 #include "i915_oa_kblgt2.h"
 #include "i915_oa_kblgt3.h"
 #include "i915_oa_glk.h"
+#include "i915_oa_cflgt2.h"
 
 /* HW requires this to be a power of two, between 128k and 16M, though driver
  * is currently generally designed assuming the largest 16M size is used such
@@ -1213,7 +1214,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 {
         struct drm_i915_private *dev_priv = stream->dev_priv;
 
-        if (i915.enable_execlists)
+        if (i915_modparams.enable_execlists)
                 dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id;
         else {
                 struct intel_engine_cs *engine = dev_priv->engine[RCS];
@@ -1259,7 +1260,7 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
 {
         struct drm_i915_private *dev_priv = stream->dev_priv;
 
-        if (i915.enable_execlists) {
+        if (i915_modparams.enable_execlists) {
                 dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
         } else {
                 struct intel_engine_cs *engine = dev_priv->engine[RCS];
@@ -1850,8 +1851,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
          * be read back from automatically triggered reports, as part of the
          * RPT_ID field.
          */
-        if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
-            IS_KABYLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+        if (IS_GEN9(dev_priv)) {
                 I915_WRITE(GEN8_OA_DEBUG,
                            _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
                                               GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -2927,6 +2927,9 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
                         i915_perf_load_test_config_kblgt3(dev_priv);
         } else if (IS_GEMINILAKE(dev_priv)) {
                 i915_perf_load_test_config_glk(dev_priv);
+        } else if (IS_COFFEELAKE(dev_priv)) {
+                if (IS_CFL_GT2(dev_priv))
+                        i915_perf_load_test_config_cflgt2(dev_priv);
         }
 
         if (dev_priv->perf.oa.test_config.id == 0)
@@ -3405,7 +3408,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                 dev_priv->perf.oa.timestamp_frequency = 12500000;
 
                 dev_priv->perf.oa.oa_formats = hsw_oa_formats;
-        } else if (i915.enable_execlists) {
+        } else if (i915_modparams.enable_execlists) {
                 /* Note: that although we could theoretically also support the
                  * legacy ringbuffer mode on BDW (and earlier iterations of
                  * this driver, before upstreaming did this) it didn't seem
@@ -3453,6 +3456,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                                 break;
                         case INTEL_SKYLAKE:
                         case INTEL_KABYLAKE:
+                        case INTEL_COFFEELAKE:
                                 dev_priv->perf.oa.timestamp_frequency = 12000000;
                                 break;
                         default:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2eff98cdcfad..ee0d4f14ac98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2336,7 +2336,7 @@ enum i915_power_well_id {
 #define DONE_REG                _MMIO(0x40b0)
 #define GEN8_PRIVATE_PAT_LO     _MMIO(0x40e0)
 #define GEN8_PRIVATE_PAT_HI     _MMIO(0x40e0 + 4)
-#define GEN10_PAT_INDEX(index)  _MMIO(0x40e0 + index*4)
+#define GEN10_PAT_INDEX(index)  _MMIO(0x40e0 + (index)*4)
 #define BSD_HWS_PGA_GEN7        _MMIO(0x04180)
 #define BLT_HWS_PGA_GEN7        _MMIO(0x04280)
 #define VEBOX_HWS_PGA_GEN7      _MMIO(0x04380)
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT          20
 #define   GEN9_F2_SS_DIS_MASK           (0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT          22
+#define   GEN10_F2_S_ENA_MASK           (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT         18
+#define   GEN10_F2_SS_DIS_MASK          (0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0                _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK          0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT         24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)          _MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3               _MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK          0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL     _MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
@@ -4047,7 +4055,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
 #define   EDP_PSR2_IDLE_MASK            0xf
-#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
+#define   EDP_PSR2_FRAME_BEFORE_SU(a)   ((a)<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
@@ -6913,7 +6921,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE         (1 << 2)
 
 #define CHICKEN_PAR1_1          _MMIO(0x42080)
-#define  SKL_RC_HASH_OUTSIDE    (1 << 15)
+#define  SKL_DE_COMPRESSED_HASH_MODE    (1 << 15)
 #define  DPA_MASK_VBLANK_SRD    (1 << 15)
 #define  FORCE_ARB_IDLE_PLANES  (1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
@@ -6949,6 +6957,7 @@ enum {
 #define  DISP_FBC_WM_DIS                (1<<15)
 #define DISP_ARB_CTL2   _MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6        (1<<6)
+#define  DISP_IPC_ENABLE                (1<<3)
 #define DBUF_CTL        _MMIO(0x45008)
 #define  DBUF_POWER_REQUEST             (1<<31)
 #define  DBUF_POWER_STATE               (1<<30)
@@ -6990,6 +6999,7 @@ enum {
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
 # define GEN9_RHWO_OPTIMIZATION_DISABLE         (1<<14)
 #define COMMON_SLICE_CHICKEN2                   _MMIO(0x7014)
+# define GEN9_PBE_COMPRESSED_HASH_SELECTION     (1<<13)
 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE   (1<<0)
@@ -7469,6 +7479,8 @@ enum {
 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT      (1 << 12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK  (0xf << 8)
+#define  CHASSIS_CLK_REQ_DURATION(x)    ((x) << 8)
 #define  SPT_PWM_GRANULARITY            (1<<0)
 #define SOUTH_CHICKEN2          _MMIO(0xc2004)
 #define  FDI_MPHY_IOSFSB_RESET_STATUS   (1<<13)
@@ -7953,8 +7965,8 @@ enum {
 #define     GEN7_PCODE_TIMEOUT                  0x2
 #define     GEN7_PCODE_ILLEGAL_DATA             0x3
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define   GEN6_PCODE_WRITE_RC6VIDS              0x4
-#define   GEN6_PCODE_READ_RC6VIDS               0x5
+#define   GEN6_PCODE_WRITE_RC6VIDS              0x4
+#define   GEN6_PCODE_READ_RC6VIDS               0x5
 #define     GEN6_ENCODE_RC6_VID(mv)             (((mv) - 245) / 5)
 #define     GEN6_DECODE_RC6_VID(vids)           (((vids) * 5) + 245)
 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ     0x18
@@ -7973,7 +7985,9 @@ enum {
 #define   GEN6_PCODE_WRITE_D_COMP               0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ           0x17
 #define   DISPLAY_IPS_CONTROL                   0x19
-#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL  0x1A
+            /* See also IPS_CTL */
+#define     IPS_PCODE_CONTROL                   (1 << 30)
+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL  0x1A
 #define   GEN9_PCODE_SAGV_CONTROL               0x21
 #define     GEN9_SAGV_DISABLE                   0x0
 #define     GEN9_SAGV_IS_DISABLED               0x1
@@ -8082,6 +8096,7 @@ enum {
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
 
 #define GEN9_HALF_SLICE_CHICKEN7        _MMIO(0xe194)
+#define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR        (1<<8)
 #define   GEN9_ENABLE_YV12_BUGFIX       (1<<4)
 #define   GEN9_ENABLE_GPGPU_PREEMPTION  (1<<2)
 
@@ -8594,7 +8609,7 @@ enum skl_power_gate {
 #define  DPLL_CFGCR0_LINK_RATE_3240     (6 << 25)
 #define  DPLL_CFGCR0_LINK_RATE_4050     (7 << 25)
 #define  DPLL_CFGCR0_DCO_FRACTION_MASK  (0x7fff << 10)
-#define  DPLL_CFGCR0_DCO_FRAC_SHIFT     (10)
+#define  DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
 #define  DPLL_CFGCR0_DCO_FRACTION(x)    ((x) << 10)
 #define  DPLL_CFGCR0_DCO_INTEGER_MASK   (0x3ff)
 #define CNL_DPLL_CFGCR0(pll)            _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
@@ -8801,6 +8816,15 @@ enum skl_power_gate {
 #define MIPIO_TXESC_CLK_DIV2                    _MMIO(0x160008)
 #define  GLK_TX_ESC_CLK_DIV2_MASK                       0x3FF
 
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP          _MMIO(0x2358)
+#define ILK_TIMESTAMP_HI        _MMIO(0x70070)
+#define IVB_TIMESTAMP_CTR       _MMIO(0x44070)
+
+#define _PIPE_FRMTMSTMP_A               0x70048
+#define PIPE_FRMTMSTMP(pipe)            \
+                        _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
+
 /* BXT MIPI clock controls */
 #define BXT_MAX_VAR_OUTPUT_KHZ                  39500
 
@@ -9382,4 +9406,8 @@ enum skl_power_gate {
 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
 
+#define MMCD_MISC_CTRL          _MMIO(0x4ddc) /* skl+ */
+#define  MMCD_PCLA              (1 << 31)
+#define  MMCD_HOTSPOT_EN        (1 << 27)
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c
index f29540f922af..808ea4d5b962 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -9,6 +9,7 @@
 
 #include <linux/slab.h>
 #include <linux/dma-fence.h>
+#include <linux/irq_work.h>
 #include <linux/reservation.h>
 
 #include "i915_sw_fence.h"
@@ -356,31 +357,44 @@ struct i915_sw_dma_fence_cb {
         struct i915_sw_fence *fence;
         struct dma_fence *dma;
         struct timer_list timer;
+        struct irq_work work;
 };
 
 static void timer_i915_sw_fence_wake(unsigned long data)
 {
         struct i915_sw_dma_fence_cb *cb = (struct i915_sw_dma_fence_cb *)data;
+        struct i915_sw_fence *fence;
+
+        fence = xchg(&cb->fence, NULL);
+        if (!fence)
+                return;
 
         pr_warn("asynchronous wait on fence %s:%s:%x timed out\n",
                 cb->dma->ops->get_driver_name(cb->dma),
                 cb->dma->ops->get_timeline_name(cb->dma),
                 cb->dma->seqno);
-        dma_fence_put(cb->dma);
-        cb->dma = NULL;
 
-        i915_sw_fence_complete(cb->fence);
-        cb->timer.function = NULL;
+        i915_sw_fence_complete(fence);
 }
 
 static void dma_i915_sw_fence_wake(struct dma_fence *dma,
                                    struct dma_fence_cb *data)
 {
         struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base);
+        struct i915_sw_fence *fence;
+
+        fence = xchg(&cb->fence, NULL);
+        if (fence)
+                i915_sw_fence_complete(fence);
+
+        irq_work_queue(&cb->work);
+}
+
+static void irq_i915_sw_fence_work(struct irq_work *wrk)
+{
+        struct i915_sw_dma_fence_cb *cb = container_of(wrk, typeof(*cb), work);
 
         del_timer_sync(&cb->timer);
-        if (cb->timer.function)
-                i915_sw_fence_complete(cb->fence);
         dma_fence_put(cb->dma);
 
         kfree(cb);
@@ -414,6 +428,7 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
         __setup_timer(&cb->timer,
                       timer_i915_sw_fence_wake, (unsigned long)cb,
                       TIMER_IRQSAFE);
+        init_irq_work(&cb->work, irq_i915_sw_fence_work);
         if (timeout) {
                 cb->dma = dma_fence_get(dma);
                 mod_timer(&cb->timer, round_jiffies_up(jiffies + timeout));
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index d805b6e6fe71..27743be5b768 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -606,11 +606,6 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder,
                          connector->encoder->base.id,
                          connector->encoder->name);
 
-        /* ELD Conn_Type */
-        connector->eld[5] &= ~(3 << 2);
-        if (intel_crtc_has_dp_encoder(crtc_state))
-                connector->eld[5] |= (1 << 2);
-
         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 
         if (dev_priv->display.audio_codec_enable)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 5949750a35ee..b881ce8596ee 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -356,7 +356,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
         struct drm_display_mode *panel_fixed_mode;
         int index;
 
-        index = i915.vbt_sdvo_panel_type;
+        index = i915_modparams.vbt_sdvo_panel_type;
         if (index == -2) {
                 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
                 return;
@@ -675,8 +675,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
                 uint8_t vswing;
 
                 /* Don't read from VBT if module parameter has valid value*/
-                if (i915.edp_vswing) {
-                        dev_priv->vbt.edp.low_vswing = i915.edp_vswing == 1;
+                if (i915_modparams.edp_vswing) {
+                        dev_priv->vbt.edp.low_vswing =
+                                i915_modparams.edp_vswing == 1;
                 } else {
                         vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
                         dev_priv->vbt.edp.low_vswing = vswing == 0;
@@ -1162,6 +1163,13 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
         is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
         is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
 
+        if (port == PORT_A && is_dvi) {
+                DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
+                              is_hdmi ? "/HDMI" : "");
+                is_dvi = false;
+                is_hdmi = false;
+        }
+
         info->supports_dvi = is_dvi;
         info->supports_hdmi = is_hdmi;
         info->supports_dp = is_dp;
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 4e00e5cb9fa1..29c62d481cef 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -64,7 +64,7 @@ static unsigned long wait_timeout(void)
 
 static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
 {
-        DRM_DEBUG_DRIVER("%s missed breadcrumb at %pF, irq posted? %s, current seqno=%x, last=%x\n",
+        DRM_DEBUG_DRIVER("%s missed breadcrumb at %pS, irq posted? %s, current seqno=%x, last=%x\n",
                          engine->name, __builtin_return_address(0),
                          yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
                                         &engine->irq_posted)),
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d32911816fc2..87fc42b19336 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -669,8 +669,12 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
         val |= LCPLL_CD_SOURCE_FCLK;
         I915_WRITE(LCPLL_CTL, val);
 
+        /*
+         * According to the spec, it should be enough to poll for this 1 us.
+         * However, extensive testing shows that this can take longer.
+         */
         if (wait_for_us(I915_READ(LCPLL_CTL) &
-                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
+                        LCPLL_CD_SOURCE_FCLK_DONE, 100))
                 DRM_ERROR("Switching to FCLK failed\n");
 
         val = I915_READ(LCPLL_CTL);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a77dd80a97f2..954070255b4d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -712,7 +712,7 @@ intel_crt_detect(struct drm_connector *connector,
          * broken monitor (without edid) to work behind a broken kvm (that fails
          * to have the right resistors for HP detection) needs to fix this up.
          * For now just bail out. */
-        if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
+        if (I915_HAS_HOTPLUG(dev_priv) && !i915_modparams.load_detect_test) {
                 status = connector_status_disconnected;
                 goto out;
         }
@@ -730,7 +730,7 @@ intel_crt_detect(struct drm_connector *connector,
                 else if (INTEL_GEN(dev_priv) < 4)
                         status = intel_crt_load_detect(crt,
                                 to_intel_crtc(connector->state->crtc)->pipe);
-                else if (i915.load_detect_test)
+                else if (i915_modparams.load_detect_test)
                         status = connector_status_disconnected;
                 else
                         status = connector_status_unknown;
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 965988f79a55..cdfb624eb82d 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
         }
 
         fw_size = dev_priv->csr.dmc_fw_size;
+        assert_rpm_wakelock_held(dev_priv);
+
+        preempt_disable();
+
         for (i = 0; i < fw_size; i++)
-                I915_WRITE(CSR_PROGRAM(i), payload[i]);
+                I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+        preempt_enable();
 
         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                 I915_WRITE(dev_priv->csr.mmioaddr[i],
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1da3bb2cc4b4..93cbbcbbc193 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -301,10 +301,10 @@ static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 };
 
 struct bxt_ddi_buf_trans {
-        u32 margin;     /* swing value */
-        u32 scale;      /* scale value */
-        u32 enable;     /* scale enable */
-        u32 deemphasis;
+        u8 margin;      /* swing value */
+        u8 scale;       /* scale value */
+        u8 enable;      /* scale enable */
+        u8 deemphasis;
         bool default_index; /* true if the entry represents default value */
 };
 
@@ -354,11 +354,11 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 };
 
 struct cnl_ddi_buf_trans {
-        u32 dw2_swing_sel;
-        u32 dw7_n_scalar;
-        u32 dw4_cursor_coeff;
-        u32 dw4_post_cursor_2;
-        u32 dw4_post_cursor_1;
+        u8 dw2_swing_sel;
+        u8 dw7_n_scalar;
+        u8 dw4_cursor_coeff;
+        u8 dw4_post_cursor_2;
+        u8 dw4_post_cursor_1;
 };
 
 /* Voltage Swing Programming for VccIO 0.85V for DP */
@@ -1212,7 +1212,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
 
         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
-                      DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
+                      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
 
         return dco_freq / (p0 * p1 * p2 * 5);
 }
@@ -1939,7 +1939,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
         val |= RCOMP_SCALAR(0x98);
         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
 
-        /* Program PORT_TX_DW4 */
+        /* Program PORT_TX_DW4 */
         /* We cannot write to GRP. It would overrite individual loadgen */
         for (ln = 0; ln < 4; ln++) {
                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
@@ -1951,7 +1951,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
         }
 
-        /* Program PORT_TX_DW5 */
+        /* Program PORT_TX_DW5 */
         /* All DW5 values are fixed for every table entry */
         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
         val &= ~RTERM_SELECT_MASK;
@@ -1959,7 +1959,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
         val |= TAP3_DISABLE;
         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
 
-        /* Program PORT_TX_DW7 */
+        /* Program PORT_TX_DW7 */
         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
         val &= ~N_SCALAR_MASK;
         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b17f7045c8f8..875d428ea75f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+        struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+        const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+        sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+                            GEN10_F2_S_ENA_SHIFT;
+        sseu->subslice_mask = (1 << 4) - 1;
+        sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+                                 GEN10_F2_SS_DIS_SHIFT);
+
+        sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+        sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+        sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+        sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+                                     GEN10_EU_DIS_SS_MASK));
+
+        /*
+         * CNL is expected to always have a uniform distribution
+         * of EU across subslices with the exception that any one
+         * EU in any one subslice may be fused off for die
+         * recovery.
+         */
+        sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+                                DIV_ROUND_UP(sseu->eu_total,
+                                             sseu_subslice_total(sseu)) : 0;
+
+        /* No restrictions on Power Gating */
+        sseu->has_slice_pg = 1;
+        sseu->has_subslice_pg = 1;
+        sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -343,7 +376,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                         info->num_sprites[pipe] = 1;
         }
 
-        if (i915.disable_display) {
+        if (i915_modparams.disable_display) {
                 DRM_INFO("Display disabled (module parameter)\n");
                 info->num_pipes = 0;
         } else if (info->num_pipes > 0 &&
@@ -409,10 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                 cherryview_sseu_info_init(dev_priv);
         else if (IS_BROADWELL(dev_priv))
                 broadwell_sseu_info_init(dev_priv);
-        else if (INTEL_INFO(dev_priv)->gen >= 9)
+        else if (INTEL_GEN(dev_priv) == 9)
                 gen9_sseu_info_init(dev_priv);
-
-        WARN_ON(info->has_snoop != !info->has_llc);
+        else if (INTEL_GEN(dev_priv) >= 10)
+                gen10_sseu_info_init(dev_priv);
 
         DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
         DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f780f39e0758..615c58e48613 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3701,7 +3701,7 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
 
 
         /* reset doesn't touch the display */
-        if (!i915.force_reset_modeset_test &&
+        if (!i915_modparams.force_reset_modeset_test &&
             !gpu_reset_clobbers_display(dev_priv))
                 return;
 
@@ -3757,7 +3757,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
         int ret;
 
         /* reset doesn't touch the display */
-        if (!i915.force_reset_modeset_test &&
+        if (!i915_modparams.force_reset_modeset_test &&
             !gpu_reset_clobbers_display(dev_priv))
                 return;
 
@@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
         assert_plane_enabled(dev_priv, crtc->plane);
         if (IS_BROADWELL(dev_priv)) {
                 mutex_lock(&dev_priv->rps.hw_lock);
-                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
+                WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
+                                                IPS_ENABLE | IPS_PCODE_CONTROL));
                 mutex_unlock(&dev_priv->rps.hw_lock);
                 /* Quoting Art Runyan: "its not safe to expect any particular
                  * value in IPS_CTL bit 31 after enabling IPS through the
@@ -6312,7 +6313,7 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
 
-        pipe_config->ips_enabled = i915.enable_ips &&
+        pipe_config->ips_enabled = i915_modparams.enable_ips &&
                 hsw_crtc_supports_ips(crtc) &&
                 pipe_config_supports_ips(dev_priv, pipe_config);
 }
@@ -6493,8 +6494,8 @@ intel_link_compute_m_n(int bits_per_pixel, int nlanes,
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 {
-        if (i915.panel_use_ssc >= 0)
-                return i915.panel_use_ssc != 0;
+        if (i915_modparams.panel_use_ssc >= 0)
+                return i915_modparams.panel_use_ssc != 0;
         return dev_priv->vbt.lvds_use_ssc
                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
@@ -9309,11 +9310,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
         pipe_config->gamma_mode =
                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
-        if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
+        if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
 
-                if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
+                if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
                         bool blend_mode_420 = tmp &
                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
 
@@ -10223,7 +10224,7 @@ int intel_dotclock_calculate(int link_freq,
         if (!m_n->link_n)
                 return 0;
 
-        return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
+        return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
 }
 
 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -12083,7 +12084,7 @@ static int intel_atomic_check(struct drm_device *dev,
                         return ret;
                 }
 
-                if (i915.fastboot &&
+                if (i915_modparams.fastboot &&
                     intel_pipe_config_compare(dev_priv,
                                         to_intel_crtc_state(old_crtc_state),
                                         pipe_config, true)) {
@@ -12298,7 +12299,6 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
         struct drm_crtc *crtc;
         struct intel_crtc_state *intel_cstate;
-        bool hw_check = intel_state->modeset;
         u64 put_domains[I915_MAX_PIPES] = {};
         int i;
 
@@ -12314,7 +12314,6 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
                 if (needs_modeset(new_crtc_state) ||
                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
-                        hw_check = true;
 
                         put_domains[to_intel_crtc(crtc)->pipe] =
                                 modeset_get_crtc_power_domains(crtc,
@@ -13511,7 +13510,7 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
         struct drm_crtc *drmmode_crtc;
         struct intel_crtc *crtc;
 
-        drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
+        drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
         if (!drmmode_crtc)
                 return -ENOENT;
 
@@ -14218,7 +14217,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
         }
 
-        if (dev_priv->info.gen >= 9)
+        if (INTEL_GEN(dev_priv) >= 9)
                 dev_priv->display.update_crtcs = skl_update_crtcs;
         else
                 dev_priv->display.update_crtcs = intel_update_crtcs;
@@ -15192,6 +15191,7 @@ void intel_display_resume(struct drm_device *dev)
         if (!ret)
                 ret = __intel_display_resume(dev, state, &ctx);
 
+        intel_enable_ipc(dev_priv);
         drm_modeset_drop_locks(&ctx);
         drm_modeset_acquire_fini(&ctx);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 887953c0f495..90e756c76f10 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -42,6 +42,7 @@
 #include "i915_drv.h"
 
 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
+#define DP_DPRX_ESI_LEN 14
 
 /* Compliance test status bits  */
 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
@@ -2692,24 +2693,46 @@ static void intel_disable_dp(struct intel_encoder *encoder,
                              const struct drm_connector_state *old_conn_state)
 {
         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
         if (old_crtc_state->has_audio)
                 intel_audio_codec_disable(encoder);
 
-        if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
-                intel_psr_disable(intel_dp, old_crtc_state);
-
         /* Make sure the panel is off before trying to change the mode. But also
          * ensure that we have vdd while we switch off the panel. */
         intel_edp_panel_vdd_on(intel_dp);
         intel_edp_backlight_off(old_conn_state);
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
         intel_edp_panel_off(intel_dp);
+}
+
+static void g4x_disable_dp(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *old_crtc_state,
+                           const struct drm_connector_state *old_conn_state)
+{
+        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+        intel_disable_dp(encoder, old_crtc_state, old_conn_state);
 
         /* disable the port before the pipe on g4x */
-        if (INTEL_GEN(dev_priv) < 5)
-                intel_dp_link_down(intel_dp);
+        intel_dp_link_down(intel_dp);
+}
+
+static void ilk_disable_dp(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *old_crtc_state,
+                           const struct drm_connector_state *old_conn_state)
+{
+        intel_disable_dp(encoder, old_crtc_state, old_conn_state);
+}
+
+static void vlv_disable_dp(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *old_crtc_state,
+                           const struct drm_connector_state *old_conn_state)
+{
+        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+        intel_psr_disable(intel_dp, old_crtc_state);
+
+        intel_disable_dp(encoder, old_crtc_state, old_conn_state);
 }
 
 static void ilk_post_disable_dp(struct intel_encoder *encoder,
@@ -3826,7 +3849,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
 {
         u8 mstm_cap;
 
-        if (!i915.enable_dp_mst)
+        if (!i915_modparams.enable_dp_mst)
                 return false;
 
         if (!intel_dp->can_mst)
@@ -3844,7 +3867,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
 static void
 intel_dp_configure_mst(struct intel_dp *intel_dp)
 {
-        if (!i915.enable_dp_mst)
+        if (!i915_modparams.enable_dp_mst)
                 return;
 
         if (!intel_dp->can_mst)
@@ -3991,15 +4014,9 @@ intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 static bool
 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 {
-        int ret;
-
-        ret = drm_dp_dpcd_read(&intel_dp->aux,
-                                             DP_SINK_COUNT_ESI,
-                                             sink_irq_vector, 14);
-        if (ret != 14)
-                return false;
-
-        return true;
+        return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
+                                sink_irq_vector, DP_DPRX_ESI_LEN) ==
+                DP_DPRX_ESI_LEN;
 }
 
 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
@@ -4199,7 +4216,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
         bool bret;
 
         if (intel_dp->is_mst) {
-                u8 esi[16] = { 0 };
+                u8 esi[DP_DPRX_ESI_LEN] = { 0 };
                 int ret = 0;
                 int retry;
                 bool handled;
@@ -4736,10 +4753,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
         if (intel_encoder->type != INTEL_OUTPUT_EDP)
                 intel_encoder->type = INTEL_OUTPUT_DP;
 
-        DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
-                      yesno(intel_dp_source_supports_hbr2(intel_dp)),
-                      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
-
         if (intel_dp->reset_link_params) {
                 /* Initial max link lane count */
                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
@@ -5467,11 +5480,6 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
                 return;
         }
 
-        /*
-         * FIXME: This needs proper synchronization with psr state for some
-         * platforms that cannot have PSR and DRRS enabled at the same time.
-         */
-
         dig_port = dp_to_dig_port(intel_dp);
         encoder = &dig_port->base;
         intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -5555,6 +5563,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
                 return;
         }
 
+        if (dev_priv->psr.enabled) {
+                DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
+                return;
+        }
+
         mutex_lock(&dev_priv->drrs.mutex);
         if (WARN_ON(dev_priv->drrs.dp)) {
                 DRM_ERROR("DRRS already enabled\n");
@@ -6145,7 +6158,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
                 goto err_encoder_init;
 
         intel_encoder->compute_config = intel_dp_compute_config;
-        intel_encoder->disable = intel_disable_dp;
         intel_encoder->get_hw_state = intel_dp_get_hw_state;
         intel_encoder->get_config = intel_dp_get_config;
         intel_encoder->suspend = intel_dp_encoder_suspend;
@@ -6153,18 +6165,24 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
                 intel_encoder->pre_enable = chv_pre_enable_dp;
                 intel_encoder->enable = vlv_enable_dp;
+                intel_encoder->disable = vlv_disable_dp;
                 intel_encoder->post_disable = chv_post_disable_dp;
                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
         } else if (IS_VALLEYVIEW(dev_priv)) {
                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
                 intel_encoder->pre_enable = vlv_pre_enable_dp;
                 intel_encoder->enable = vlv_enable_dp;
+                intel_encoder->disable = vlv_disable_dp;
                 intel_encoder->post_disable = vlv_post_disable_dp;
+        } else if (INTEL_GEN(dev_priv) >= 5) {
+                intel_encoder->pre_enable = g4x_pre_enable_dp;
+                intel_encoder->enable = g4x_enable_dp;
+                intel_encoder->disable = ilk_disable_dp;
+                intel_encoder->post_disable = ilk_post_disable_dp;
         } else {
                 intel_encoder->pre_enable = g4x_pre_enable_dp;
                 intel_encoder->enable = g4x_enable_dp;
-                if (INTEL_GEN(dev_priv) >= 5)
-                        intel_encoder->post_disable = ilk_post_disable_dp;
+                intel_encoder->disable = g4x_disable_dp;
         }
 
         intel_dig_port->port = port;
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index d2830ba3162e..2bb2ceb9d463 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -264,7 +264,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
 {
         struct intel_panel *panel = &intel_connector->panel;
 
-        if (!i915.enable_dpcd_backlight)
+        if (!i915_modparams.enable_dpcd_backlight)
                 return -ENODEV;
 
         if (!intel_dp_aux_display_control_capable(intel_connector))
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 8e3aad0ea60b..9a396f483f8b 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -133,7 +133,7 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder,
                 to_intel_connector(old_conn_state->connector);
         int ret;
 
-        DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
         drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
 
@@ -155,8 +155,6 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
         struct intel_connector *connector =
                 to_intel_connector(old_conn_state->connector);
 
-        DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
-
         /* this can fail */
         drm_dp_check_act_status(&intel_dp->mst_mgr);
         /* and this can also fail */
@@ -173,6 +171,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
 
                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
         }
+        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 }
 
 static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
@@ -195,7 +194,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
         connector->encoder = encoder;
         intel_mst->connector = connector;
 
-        DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
         if (intel_dp->active_mst_links == 0)
                 intel_dig_port->base.pre_enable(&intel_dig_port->base,
@@ -229,7 +228,7 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
         enum port port = intel_dig_port->port;
         int ret;
 
-        DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
         if (intel_wait_for_register(dev_priv,
                                     DP_TP_STATUS(port),
@@ -494,6 +493,7 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
         struct intel_connector *intel_connector = to_intel_connector(connector);
         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 
+        DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);
         drm_connector_unregister(connector);
 
         if (dev_priv->fbdev)
@@ -505,7 +505,6 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
         drm_modeset_unlock(&connector->dev->mode_config.connection_mutex);
 
         drm_connector_unreference(connector);
-        DRM_DEBUG_KMS("\n");
 }
 
 static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 463ed152e6b1..0cab667fff57 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -494,6 +494,8 @@ struct intel_crtc_scaler_state {
 
 /* drm_mode->private_flags */
 #define I915_MODE_FLAG_INHERITED 1
+/* Flag to get scanline using frame time stamps */
+#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 
 struct intel_pipe_wm {
         struct intel_wm_level wm[5];
@@ -1898,9 +1900,11 @@ bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
                                   struct intel_crtc_state *cstate);
+void intel_init_ipc(struct drm_i915_private *dev_priv);
+void intel_enable_ipc(struct drm_i915_private *dev_priv);
 static inline int intel_enable_rc6(void)
 {
-        return i915.enable_rc6;
+        return i915_modparams.enable_rc6;
 }
 
 /* intel_sdvo.c */
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fc25d7d2d942..20a7b004ffd7 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -263,7 +263,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 
         /* XXX: old code skips write if control unchanged */
         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
-                DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
+                DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 
         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 
@@ -330,6 +330,10 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
         adjusted_mode->flags = 0;
 
         if (IS_GEN9_LP(dev_priv)) {
+                /* Enable Frame time stamp based scanline reporting */
+                adjusted_mode->private_flags |=
+                        I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
+
                 /* Dual link goes to DSI transcoder A. */
                 if (intel_dsi->ports == BIT(PORT_C))
                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -1102,6 +1106,10 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
                                 pixel_format_from_register_bits(fmt));
         bpp = pipe_config->pipe_bpp;
 
+        /* Enable Frame time stamo based scanline reporting */
+        adjusted_mode->private_flags |=
+                        I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
+
         /* In terms of pixels */
         adjusted_mode->crtc_hdisplay =
                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index b8e9a234af2d..a28e2a864cf1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -39,6 +39,7 @@
 
 #define GEN8_LR_CONTEXT_RENDER_SIZE     (20 * PAGE_SIZE)
 #define GEN9_LR_CONTEXT_RENDER_SIZE     (22 * PAGE_SIZE)
+#define GEN10_LR_CONTEXT_RENDER_SIZE    (19 * PAGE_SIZE)
 
 #define GEN8_LR_CONTEXT_OTHER_SIZE      ( 2 * PAGE_SIZE)
 
@@ -150,10 +151,11 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
                 default:
                         MISSING_CASE(INTEL_GEN(dev_priv));
                 case 10:
+                        return GEN10_LR_CONTEXT_RENDER_SIZE;
                 case 9:
                         return GEN9_LR_CONTEXT_RENDER_SIZE;
                 case 8:
-                        return i915.enable_execlists ?
+                        return i915_modparams.enable_execlists ?
                                GEN8_LR_CONTEXT_RENDER_SIZE :
                                GEN8_CXT_TOTAL_SIZE;
                 case 7:
@@ -301,7 +303,7 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
                         &intel_engine_classes[engine->class];
                 int (*init)(struct intel_engine_cs *engine);
 
-                if (i915.enable_execlists)
+                if (i915_modparams.enable_execlists)
                         init = class_info->init_execlists;
                 else
                         init = class_info->init_legacy;
@@ -380,6 +382,37 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
         engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
 }
 
+static bool csb_force_mmio(struct drm_i915_private *i915)
+{
+        /* GVT emulation depends upon intercepting CSB mmio */
+        if (intel_vgpu_active(i915))
+                return true;
+
+        /*
+         * IOMMU adds unpredictable latency causing the CSB write (from the
+         * GPU into the HWSP) to only be visible some time after the interrupt
+         * (missed breadcrumb syndrome).
+         */
+        if (intel_vtd_active())
+                return true;
+
+        return false;
+}
+
+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
+{
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+
+        execlists->csb_use_mmio = csb_force_mmio(engine->i915);
+
+        execlists->port_mask = 1;
+        BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
+        GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
+
+        execlists->queue = RB_ROOT;
+        execlists->first = NULL;
+}
+
 /**
  * intel_engines_setup_common - setup engine state not requiring hw access
  * @engine: Engine to setup.
@@ -391,8 +424,7 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
  */
 void intel_engine_setup_common(struct intel_engine_cs *engine)
 {
-        engine->execlist_queue = RB_ROOT;
-        engine->execlist_first = NULL;
+        intel_engine_init_execlist(engine);
 
         intel_engine_init_timeline(engine);
         intel_engine_init_hangcheck(engine);
@@ -442,6 +474,116 @@ static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
         i915_vma_unpin_and_release(&engine->scratch);
 }
 
+static void cleanup_phys_status_page(struct intel_engine_cs *engine)
+{
+        struct drm_i915_private *dev_priv = engine->i915;
+
+        if (!dev_priv->status_page_dmah)
+                return;
+
+        drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
+        engine->status_page.page_addr = NULL;
+}
+
+static void cleanup_status_page(struct intel_engine_cs *engine)
+{
+        struct i915_vma *vma;
+        struct drm_i915_gem_object *obj;
+
+        vma = fetch_and_zero(&engine->status_page.vma);
+        if (!vma)
+                return;
+
+        obj = vma->obj;
+
+        i915_vma_unpin(vma);
+        i915_vma_close(vma);
+
+        i915_gem_object_unpin_map(obj);
+        __i915_gem_object_release_unless_active(obj);
+}
+
+static int init_status_page(struct intel_engine_cs *engine)
+{
+        struct drm_i915_gem_object *obj;
+        struct i915_vma *vma;
+        unsigned int flags;
+        void *vaddr;
+        int ret;
+
+        obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+        if (IS_ERR(obj)) {
+                DRM_ERROR("Failed to allocate status page\n");
+                return PTR_ERR(obj);
+        }
+
+        ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+        if (ret)
+                goto err;
+
+        vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
+        if (IS_ERR(vma)) {
+                ret = PTR_ERR(vma);
+                goto err;
+        }
+
+        flags = PIN_GLOBAL;
+        if (!HAS_LLC(engine->i915))
+                /* On g33, we cannot place HWS above 256MiB, so
+                 * restrict its pinning to the low mappable arena.
+                 * Though this restriction is not documented for
+                 * gen4, gen5, or byt, they also behave similarly
+                 * and hang if the HWS is placed at the top of the
+                 * GTT. To generalise, it appears that all !llc
+                 * platforms have issues with us placing the HWS
+                 * above the mappable region (even though we never
+                 * actually map it).
+                 */
+                flags |= PIN_MAPPABLE;
+        else
+                flags |= PIN_HIGH;
+        ret = i915_vma_pin(vma, 0, 4096, flags);
+        if (ret)
+                goto err;
+
+        vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+        if (IS_ERR(vaddr)) {
+                ret = PTR_ERR(vaddr);
+                goto err_unpin;
+        }
+
+        engine->status_page.vma = vma;
+        engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
+        engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
+
+        DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
+                         engine->name, i915_ggtt_offset(vma));
+        return 0;
+
+err_unpin:
+        i915_vma_unpin(vma);
+err:
+        i915_gem_object_put(obj);
+        return ret;
+}
+
+static int init_phys_status_page(struct intel_engine_cs *engine)
+{
+        struct drm_i915_private *dev_priv = engine->i915;
+
+        GEM_BUG_ON(engine->id != RCS);
+
+        dev_priv->status_page_dmah =
+                drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
+        if (!dev_priv->status_page_dmah)
+                return -ENOMEM;
+
+        engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
+        memset(engine->status_page.page_addr, 0, PAGE_SIZE);
+
+        return 0;
+}
+
 /**
  * intel_engines_init_common - initialize cengine state which might require hw access
  * @engine: Engine to initialize.
@@ -477,10 +619,21 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
 
         ret = i915_gem_render_state_init(engine);
         if (ret)
-                goto err_unpin;
+                goto err_breadcrumbs;
+
+        if (HWS_NEEDS_PHYSICAL(engine->i915))
+                ret = init_phys_status_page(engine);
+        else
+                ret = init_status_page(engine);
+        if (ret)
+                goto err_rs_fini;
 
         return 0;
 
+err_rs_fini:
+        i915_gem_render_state_fini(engine);
+err_breadcrumbs:
+        intel_engine_fini_breadcrumbs(engine);
 err_unpin:
         engine->context_unpin(engine, engine->i915->kernel_context);
         return ret;
@@ -497,6 +650,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 {
         intel_engine_cleanup_scratch(engine);
 
+        if (HWS_NEEDS_PHYSICAL(engine->i915))
+                cleanup_phys_status_page(engine);
+        else
+                cleanup_status_page(engine);
+
         i915_gem_render_state_fini(engine);
         intel_engine_fini_breadcrumbs(engine);
         intel_engine_cleanup_cmd_parser(engine);
@@ -812,6 +970,19 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
                            ECOCHK_DIS_TLB);
 
+        if (HAS_LLC(dev_priv)) {
+                /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
+                 *
+                 * Must match Display Engine. See
+                 * WaCompressedResourceDisplayNewHashMode.
+                 */
+                WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+                                  GEN9_PBE_COMPRESSED_HASH_SELECTION);
+                WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
+                                  GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
+                WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN);
+        }
+
         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -981,12 +1152,14 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
 
         /* WaDisableGafsUnitClkGating:skl */
-        WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+        I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
         /* WaInPlaceDecompressionHang:skl */
         if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
-                WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                           GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+                I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                           (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
         /* WaDisableLSQCROPERFforOCL:skl */
         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1022,8 +1195,8 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 
         /* WaDisablePooledEuLoadBalancingFix:bxt */
         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
-                WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
-                                  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+                I915_WRITE(FF_SLICE_CS_CHICKEN2,
+                           _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
         }
 
         /* WaDisableSbeCacheDispatchPortSharing:bxt */
@@ -1059,8 +1232,9 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 
         /* WaInPlaceDecompressionHang:bxt */
         if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
-                WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                           GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+                I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                           (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                            GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
         return 0;
 }
@@ -1070,10 +1244,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
         struct drm_i915_private *dev_priv = engine->i915;
         int ret;
 
-        /* WaDisableI2mCycleOnWRPort: cnl (pre-prod) */
+        /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
         if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
-                WA_SET_BIT(GAMT_CHKN_BIT_REG,
-                           GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
+                I915_WRITE(GAMT_CHKN_BIT_REG,
+                           (I915_READ(GAMT_CHKN_BIT_REG) |
+                            GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
 
         /* WaForceContextSaveRestoreNonCoherent:cnl */
         WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
@@ -1093,11 +1268,12 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
                                   GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
 
         /* WaInPlaceDecompressionHang:cnl */
-        WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+        I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
         /* WaPushConstantDereferenceHoldDisable:cnl */
-        WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
+        WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 
         /* FtrEnableFastAnisoL1BankingFix: cnl */
         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
@@ -1125,8 +1301,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
 
         /* WaDisableDynamicCreditSharing:kbl */
         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
-                WA_SET_BIT(GAMT_CHKN_BIT_REG,
-                           GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+                I915_WRITE(GAMT_CHKN_BIT_REG,
+                           (I915_READ(GAMT_CHKN_BIT_REG) |
+                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING));
 
         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
@@ -1139,7 +1316,8 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
         /* WaDisableGafsUnitClkGating:kbl */
-        WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+        I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
         /* WaDisableSbeCacheDispatchPortSharing:kbl */
         WA_SET_BIT_MASKED(
@@ -1147,8 +1325,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
         /* WaInPlaceDecompressionHang:kbl */
-        WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+        I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
         /* WaDisableLSQCROPERFforOCL:kbl */
         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1192,7 +1371,8 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
         /* WaDisableGafsUnitClkGating:cfl */
-        WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+        I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
+                                  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
 
         /* WaDisableSbeCacheDispatchPortSharing:cfl */
         WA_SET_BIT_MASKED(
@@ -1200,8 +1380,9 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine)
                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
         /* WaInPlaceDecompressionHang:cfl */
-        WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+        I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
         return 0;
 }
@@ -1324,11 +1505,11 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
                 return false;
 
         /* Both ports drained, no more ELSP submission? */
-        if (port_request(&engine->execlist_port[0]))
+        if (port_request(&engine->execlists.port[0]))
                 return false;
 
         /* ELSP is empty, but there are ready requests? */
-        if (READ_ONCE(engine->execlist_first))
+        if (READ_ONCE(engine->execlists.first))
                 return false;
 
         /* Ring stopped? */
@@ -1377,8 +1558,8 @@ void intel_engines_mark_idle(struct drm_i915_private *i915)
         for_each_engine(engine, i915, id) {
                 intel_engine_disarm_breadcrumbs(engine);
                 i915_gem_batch_pool_fini(&engine->batch_pool);
-                tasklet_kill(&engine->irq_tasklet);
-                engine->no_priolist = false;
+                tasklet_kill(&engine->execlists.irq_tasklet);
+                engine->execlists.no_priolist = false;
         }
 }
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 58a772de6672..8e3a05505f49 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -859,7 +859,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
                 return false;
         }
 
-        if (!i915.enable_fbc) {
+        if (!i915_modparams.enable_fbc) {
                 fbc->no_fbc_reason = "disabled per module param or by default";
                 return false;
         }
@@ -1310,8 +1310,8 @@ void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
  */
 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
 {
-        if (i915.enable_fbc >= 0)
-                return !!i915.enable_fbc;
+        if (i915_modparams.enable_fbc >= 0)
+                return !!i915_modparams.enable_fbc;
 
         if (!HAS_FBC(dev_priv))
                 return 0;
@@ -1355,8 +1355,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
         if (need_fbc_vtd_wa(dev_priv))
                 mkwrite_device_info(dev_priv)->has_fbc = false;
 
-        i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
-        DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
+        i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
+        DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
+                      i915_modparams.enable_fbc);
 
         if (!HAS_FBC(dev_priv)) {
                 fbc->no_fbc_reason = "unsupported by this chipset";
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 04689600e337..77c123cc8817 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -88,14 +88,15 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 {
         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
         i915_reg_t reg = PIPESTAT(crtc->pipe);
-        u32 pipestat = I915_READ(reg) & 0xffff0000;
+        u32 enable_mask;
 
         lockdep_assert_held(&dev_priv->irq_lock);
 
-        if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
+        if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
                 return;
 
-        I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
+        enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
+        I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
         POSTING_READ(reg);
 
         trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
@@ -108,15 +109,16 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
         i915_reg_t reg = PIPESTAT(pipe);
-        u32 pipestat = I915_READ(reg) & 0xffff0000;
 
         lockdep_assert_held(&dev_priv->irq_lock);
 
         if (enable) {
-                I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
+                u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
+
+                I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
                 POSTING_READ(reg);
         } else {
-                if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
+                if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
         }
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5fa286074811..7eb6b4fa1d6f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -56,10 +56,6 @@
 #define WQ_LEN_SHIFT                    16
 #define WQ_NO_WCFLUSH_WAIT              (1 << 27)
 #define WQ_PRESENT_WORKLOAD             (1 << 28)
-#define WQ_WORKLOAD_SHIFT               29
-#define   WQ_WORKLOAD_GENERAL           (0 << WQ_WORKLOAD_SHIFT)
-#define   WQ_WORKLOAD_GPGPU             (1 << WQ_WORKLOAD_SHIFT)
-#define   WQ_WORKLOAD_TOUCH             (2 << WQ_WORKLOAD_SHIFT)
 
 #define WQ_RING_TAIL_SHIFT              20
 #define WQ_RING_TAIL_MAX                0x7FF   /* 2^11 QWords */
@@ -388,7 +384,11 @@ struct guc_ct_buffer_desc {
 /* Preempt to idle on quantum expiry */
 #define POLICY_PREEMPT_TO_IDLE          (1<<1)
 
-#define POLICY_MAX_NUM_WI               15
+#define POLICY_MAX_NUM_WI 15
+#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
+#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
+#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
+#define POLICY_DEFAULT_FAULT_TIME_US 250000
 
 struct guc_policy {
         /* Time for one workload to execute. (in micro seconds) */
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8b0ae7fce7f2..c9e25be4db40 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -131,14 +131,14 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
 
         params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
-        if (i915.guc_log_level >= 0) {
+        if (i915_modparams.guc_log_level >= 0) {
                 params[GUC_CTL_DEBUG] =
-                        i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
+                        i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
         } else
                 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 
         /* If GuC submission is enabled, set up additional parameters here */
-        if (i915.enable_guc_submission) {
+        if (i915_modparams.enable_guc_submission) {
                 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
                 u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
                 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
@@ -368,7 +368,8 @@ int intel_guc_init_hw(struct intel_guc *guc)
         guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
 
         DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
-                 i915.enable_guc_submission ? "submission enabled" : "loaded",
+                 i915_modparams.enable_guc_submission ? "submission enabled" :
+                                                        "loaded",
                  guc->fw.path,
                  guc->fw.major_ver_found, guc->fw.minor_ver_found);
 
@@ -390,8 +391,8 @@ int intel_guc_select_fw(struct intel_guc *guc)
         guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
         guc->fw.type = INTEL_UC_FW_TYPE_GUC;
 
-        if (i915.guc_firmware_path) {
-                guc->fw.path = i915.guc_firmware_path;
+        if (i915_modparams.guc_firmware_path) {
+                guc->fw.path = i915_modparams.guc_firmware_path;
                 guc->fw.major_ver_wanted = 0;
                 guc->fw.minor_ver_wanted = 0;
         } else if (IS_SKYLAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b8719cab..6571d96704ad 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -144,7 +144,7 @@ static int guc_log_relay_file_create(struct intel_guc *guc)
         struct dentry *log_dir;
         int ret;
 
-        if (i915.guc_log_level < 0)
+        if (i915_modparams.guc_log_level < 0)
                 return 0;
 
         /* For now create the log file in /sys/kernel/debug/dri/0 dir */
@@ -480,7 +480,7 @@ err_runtime:
         guc_log_runtime_destroy(guc);
 err:
         /* logging will remain off */
-        i915.guc_log_level = -1;
+        i915_modparams.guc_log_level = -1;
         return ret;
 }
 
@@ -502,7 +502,8 @@ static void guc_flush_logs(struct intel_guc *guc)
 {
         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 
-        if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
+        if (!i915_modparams.enable_guc_submission ||
+            (i915_modparams.guc_log_level < 0))
                 return;
 
         /* First disable the interrupts, will be renabled afterwards */
@@ -529,8 +530,8 @@ int intel_guc_log_create(struct intel_guc *guc)
 
         GEM_BUG_ON(guc->log.vma);
 
-        if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
-                i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
+        if (i915_modparams.guc_log_level > GUC_LOG_VERBOSITY_MAX)
+                i915_modparams.guc_log_level = GUC_LOG_VERBOSITY_MAX;
 
         /* The first page is to save log buffer state. Allocate one
          * extra page for others in case for overlap */
@@ -555,7 +556,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 
         guc->log.vma = vma;
 
-        if (i915.guc_log_level >= 0) {
+        if (i915_modparams.guc_log_level >= 0) {
                 ret = guc_log_runtime_create(guc);
                 if (ret < 0)
                         goto err_vma;
@@ -576,7 +577,7 @@ err_vma:
         i915_vma_unpin_and_release(&guc->log.vma);
 err:
         /* logging will be off */
-        i915.guc_log_level = -1;
+        i915_modparams.guc_log_level = -1;
         return ret;
 }
 
@@ -600,7 +601,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
                 return -EINVAL;
 
         /* This combination doesn't make sense & won't have any effect */
-        if (!log_param.logging_enabled && (i915.guc_log_level < 0))
+        if (!log_param.logging_enabled && (i915_modparams.guc_log_level < 0))
                 return 0;
 
         ret = guc_log_control(guc, log_param.value);
@@ -610,7 +611,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
         }
 
         if (log_param.logging_enabled) {
-                i915.guc_log_level = log_param.verbosity;
+                i915_modparams.guc_log_level = log_param.verbosity;
 
                 /* If log_level was set as -1 at boot time, then the relay channel file
                  * wouldn't have been created by now and interrupts also would not have
@@ -633,7 +634,7 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
                 guc_flush_logs(guc);
 
                 /* As logging is disabled, update log level to reflect that */
-                i915.guc_log_level = -1;
+                i915_modparams.guc_log_level = -1;
         }
 
         return ret;
@@ -641,7 +642,8 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 
 void i915_guc_log_register(struct drm_i915_private *dev_priv)
 {
-        if (!i915.enable_guc_submission || i915.guc_log_level < 0)
+        if (!i915_modparams.enable_guc_submission ||
+            (i915_modparams.guc_log_level < 0))
                 return;
 
         mutex_lock(&dev_priv->drm.struct_mutex);
@@ -651,7 +653,7 @@ void i915_guc_log_register(struct drm_i915_private *dev_priv)
 
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-        if (!i915.enable_guc_submission)
+        if (!i915_modparams.enable_guc_submission)
                 return;
 
         mutex_lock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index c17ed0e62b67..b4a7f31f0214 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -58,7 +58,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv)
  */
 void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
 {
-        if (!i915.enable_gvt)
+        if (!i915_modparams.enable_gvt)
                 return;
 
         if (intel_vgpu_active(dev_priv)) {
@@ -73,7 +73,7 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
 
         return;
 bail:
-        i915.enable_gvt = 0;
+        i915_modparams.enable_gvt = 0;
 }
 
 /**
@@ -90,17 +90,17 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
 {
         int ret;
 
-        if (!i915.enable_gvt) {
+        if (!i915_modparams.enable_gvt) {
                 DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
                 return 0;
         }
 
-        if (!i915.enable_execlists) {
+        if (!i915_modparams.enable_execlists) {
                 DRM_ERROR("i915 GVT-g loading failed due to disabled execlists mode\n");
                 return -EIO;
         }
 
-        if (i915.enable_guc_submission) {
+        if (i915_modparams.enable_guc_submission) {
                 DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
                 return -EIO;
         }
@@ -123,7 +123,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
         return 0;
 
 bail:
-        i915.enable_gvt = 0;
+        i915_modparams.enable_gvt = 0;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index d9d87d96fb69..12ac270a5f93 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -428,7 +428,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
         unsigned int hung = 0, stuck = 0;
         int busy_count = 0;
 
-        if (!i915.enable_hangcheck)
+        if (!i915_modparams.enable_hangcheck)
                 return;
 
         if (!READ_ONCE(dev_priv->gt.awake))
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0d6773..8b4b53525422 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -155,8 +155,8 @@ void intel_huc_select_fw(struct intel_huc *huc)
         huc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
         huc->fw.type = INTEL_UC_FW_TYPE_HUC;
 
-        if (i915.huc_firmware_path) {
-                huc->fw.path = i915.huc_firmware_path;
+        if (i915_modparams.huc_firmware_path) {
+                huc->fw.path = i915_modparams.huc_firmware_path;
                 huc->fw.major_ver_wanted = 0;
                 huc->fw.minor_ver_wanted = 0;
         } else if (IS_SKYLAKE(dev_priv)) {
@@ -225,19 +225,22 @@ void intel_huc_init_hw(struct intel_huc *huc)
 }
 
 /**
- * intel_guc_auth_huc() - authenticate ucode
- * @dev_priv: the drm_i915_device
+ * intel_huc_auth() - Authenticate HuC uCode
+ * @huc: intel_huc structure
+ *
+ * Called after HuC and GuC firmware loading during intel_uc_init_hw().
  *
- * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
- * authenticate_huc interface.
+ * This function pins HuC firmware image object into GGTT.
+ * Then it invokes GuC action to authenticate passing the offset to RSA
+ * signature through intel_guc_auth_huc(). It then waits for 50ms for
+ * firmware verification ACK and unpins the object.
  */
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
+void intel_huc_auth(struct intel_huc *huc)
 {
-        struct intel_guc *guc = &dev_priv->guc;
-        struct intel_huc *huc = &dev_priv->huc;
+        struct drm_i915_private *i915 = huc_to_i915(huc);
+        struct intel_guc *guc = &i915->guc;
         struct i915_vma *vma;
         int ret;
-        u32 data[2];
 
         if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
                 return;
@@ -250,23 +253,19 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
                 return;
         }
 
-        /* Specify auth action and where public signature is. */
-        data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
-        data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
-
-        ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
+        ret = intel_guc_auth_huc(guc,
+                                 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
         if (ret) {
                 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
                 goto out;
         }
 
         /* Check authentication status, it should be done by now */
-        ret = intel_wait_for_register(dev_priv,
-                                HUC_STATUS2,
-                                HUC_FW_VERIFIED,
-                                HUC_FW_VERIFIED,
-                                50);
-
+        ret = intel_wait_for_register(i915,
+                                      HUC_STATUS2,
+                                      HUC_FW_VERIFIED,
+                                      HUC_FW_VERIFIED,
+                                      50);
         if (ret) {
                 DRM_ERROR("HuC: Authentication failed %d\n", ret);
                 goto out;
@@ -275,4 +274,3 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
 out:
         i915_vma_unpin(vma);
 }
-
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d89e1b8e1cc5..61cac26a8b05 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -244,7 +244,7 @@ int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enabl
 
         if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
             USES_PPGTT(dev_priv) &&
-            i915.use_mmio_flip >= 0)
+            i915_modparams.use_mmio_flip >= 0)
                 return 1;
 
         return 0;
@@ -279,17 +279,73 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
         BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
 
         desc = ctx->desc_template;                              /* bits  0-11 */
-        desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
+        desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
                                                                 /* bits 12-31 */
         desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;           /* bits 32-52 */
 
         ce->lrc_desc = desc;
 }
 
-uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-                                     struct intel_engine_cs *engine)
+static struct i915_priolist *
+lookup_priolist(struct intel_engine_cs *engine,
+                struct i915_priotree *pt,
+                int prio)
 {
-        return ctx->engine[engine->id].lrc_desc;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct i915_priolist *p;
+        struct rb_node **parent, *rb;
+        bool first = true;
+
+        if (unlikely(execlists->no_priolist))
+                prio = I915_PRIORITY_NORMAL;
+
+find_priolist:
+        /* most positive priority is scheduled first, equal priorities fifo */
+        rb = NULL;
+        parent = &execlists->queue.rb_node;
+        while (*parent) {
+                rb = *parent;
+                p = rb_entry(rb, typeof(*p), node);
+                if (prio > p->priority) {
+                        parent = &rb->rb_left;
+                } else if (prio < p->priority) {
+                        parent = &rb->rb_right;
+                        first = false;
+                } else {
+                        return p;
+                }
+        }
+
+        if (prio == I915_PRIORITY_NORMAL) {
+                p = &execlists->default_priolist;
+        } else {
+                p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
+                /* Convert an allocation failure to a priority bump */
+                if (unlikely(!p)) {
+                        prio = I915_PRIORITY_NORMAL; /* recurses just once */
+
+                        /* To maintain ordering with all rendering, after an
+                         * allocation failure we have to disable all scheduling.
+                         * Requests will then be executed in fifo, and schedule
+                         * will ensure that dependencies are emitted in fifo.
+                         * There will be still some reordering with existing
+                         * requests, so if userspace lied about their
+                         * dependencies that reordering may be visible.
+                         */
+                        execlists->no_priolist = true;
+                        goto find_priolist;
+                }
+        }
+
+        p->priority = prio;
+        INIT_LIST_HEAD(&p->requests);
+        rb_link_node(&p->node, rb, parent);
+        rb_insert_color(&p->node, &execlists->queue);
+
+        if (first)
+                execlists->first = &p->node;
+
+        return ptr_pack_bits(p, first, 1);
 }
 
 static inline void
@@ -338,12 +394,12 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
 
 static void execlists_submit_ports(struct intel_engine_cs *engine)
 {
-        struct execlist_port *port = engine->execlist_port;
+        struct execlist_port *port = engine->execlists.port;
         u32 __iomem *elsp =
                 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
         unsigned int n;
 
-        for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
+        for (n = execlists_num_ports(&engine->execlists); n--; ) {
                 struct drm_i915_gem_request *rq;
                 unsigned int count;
                 u64 desc;
@@ -398,7 +454,10 @@ static void port_assign(struct execlist_port *port,
 static void execlists_dequeue(struct intel_engine_cs *engine)
 {
         struct drm_i915_gem_request *last;
-        struct execlist_port *port = engine->execlist_port;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct execlist_port *port = execlists->port;
+        const struct execlist_port * const last_port =
+                &execlists->port[execlists->port_mask];
         struct rb_node *rb;
         bool submit = false;
 
@@ -412,8 +471,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
                  */
                 last->tail = last->wa_tail;
 
-        GEM_BUG_ON(port_isset(&port[1]));
-
         /* Hardware submission is through 2 ports. Conceptually each port
          * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
          * static for a context, and unique to each, so we only execute
@@ -436,8 +493,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
          */
 
         spin_lock_irq(&engine->timeline->lock);
-        rb = engine->execlist_first;
-        GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
+        rb = execlists->first;
+        GEM_BUG_ON(rb_first(&execlists->queue) != rb);
         while (rb) {
                 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
                 struct drm_i915_gem_request *rq, *rn;
@@ -460,7 +517,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
                                  * combine this request with the last, then we
                                  * are done.
                                  */
-                                if (port != engine->execlist_port) {
+                                if (port == last_port) {
                                         __list_del_many(&p->requests,
                                                         &rq->priotree.link);
                                         goto done;
@@ -485,25 +542,27 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
                                 if (submit)
                                         port_assign(port, last);
                                 port++;
+
+                                GEM_BUG_ON(port_isset(port));
                         }
 
                         INIT_LIST_HEAD(&rq->priotree.link);
                         rq->priotree.priority = INT_MAX;
 
                         __i915_gem_request_submit(rq);
-                        trace_i915_gem_request_in(rq, port_index(port, engine));
+                        trace_i915_gem_request_in(rq, port_index(port, execlists));
                         last = rq;
                         submit = true;
                 }
 
                 rb = rb_next(rb);
-                rb_erase(&p->node, &engine->execlist_queue);
+                rb_erase(&p->node, &execlists->queue);
                 INIT_LIST_HEAD(&p->requests);
                 if (p->priority != I915_PRIORITY_NORMAL)
                         kmem_cache_free(engine->i915->priorities, p);
         }
 done:
-        engine->execlist_first = rb;
+        execlists->first = rb;
         if (submit)
                 port_assign(port, last);
         spin_unlock_irq(&engine->timeline->lock);
@@ -512,9 +571,83 @@ done:
                 execlists_submit_ports(engine);
 }
 
+static void
+execlist_cancel_port_requests(struct intel_engine_execlists *execlists)
+{
+        struct execlist_port *port = execlists->port;
+        unsigned int num_ports = ARRAY_SIZE(execlists->port);
+
+        while (num_ports-- && port_isset(port)) {
+                struct drm_i915_gem_request *rq = port_request(port);
+
+                execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
+                i915_gem_request_put(rq);
+
+                memset(port, 0, sizeof(*port));
+                port++;
+        }
+}
+
+static void execlists_cancel_requests(struct intel_engine_cs *engine)
+{
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct drm_i915_gem_request *rq, *rn;
+        struct rb_node *rb;
+        unsigned long flags;
+
+        spin_lock_irqsave(&engine->timeline->lock, flags);
+
+        /* Cancel the requests on the HW and clear the ELSP tracker. */
+        execlist_cancel_port_requests(execlists);
+
+        /* Mark all executing requests as skipped. */
+        list_for_each_entry(rq, &engine->timeline->requests, link) {
+                GEM_BUG_ON(!rq->global_seqno);
+                if (!i915_gem_request_completed(rq))
+                        dma_fence_set_error(&rq->fence, -EIO);
+        }
+
+        /* Flush the queued requests to the timeline list (for retiring). */
+        rb = execlists->first;
+        while (rb) {
+                struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
+
+                list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
+                        INIT_LIST_HEAD(&rq->priotree.link);
+                        rq->priotree.priority = INT_MAX;
+
+                        dma_fence_set_error(&rq->fence, -EIO);
+                        __i915_gem_request_submit(rq);
+                }
+
+                rb = rb_next(rb);
+                rb_erase(&p->node, &execlists->queue);
+                INIT_LIST_HEAD(&p->requests);
+                if (p->priority != I915_PRIORITY_NORMAL)
+                        kmem_cache_free(engine->i915->priorities, p);
+        }
+
+        /* Remaining _unready_ requests will be nop'ed when submitted */
+
+
+        execlists->queue = RB_ROOT;
+        execlists->first = NULL;
+        GEM_BUG_ON(port_isset(execlists->port));
+
+        /*
+         * The port is checked prior to scheduling a tasklet, but
+         * just in case we have suspended the tasklet to do the
+         * wedging make sure that when it wakes, it decides there
+         * is no work to do by clearing the irq_posted bit.
+         */
+        clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+
+        spin_unlock_irqrestore(&engine->timeline->lock, flags);
+}
+
 static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
 {
-        const struct execlist_port *port = engine->execlist_port;
+        const struct execlist_port *port = engine->execlists.port;
 
         return port_count(&port[0]) + port_count(&port[1]) < 2;
 }
@@ -525,8 +658,9 @@ static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
  */
 static void intel_lrc_irq_handler(unsigned long data)
 {
-        struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
-        struct execlist_port *port = engine->execlist_port;
+        struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct execlist_port *port = execlists->port;
         struct drm_i915_private *dev_priv = engine->i915;
 
         /* We can skip acquiring intel_runtime_pm_get() here as it was taken
@@ -538,19 +672,25 @@ static void intel_lrc_irq_handler(unsigned long data)
          */
         GEM_BUG_ON(!dev_priv->gt.awake);
 
-        intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
+        intel_uncore_forcewake_get(dev_priv, execlists->fw_domains);
 
         /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
          * imposing the cost of a locked atomic transaction when submitting a
          * new request (outside of the context-switch interrupt).
          */
         while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
-                u32 __iomem *csb_mmio =
-                        dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
-                u32 __iomem *buf =
-                        dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
+                /* The HWSP contains a (cacheable) mirror of the CSB */
+                const u32 *buf =
+                        &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
                 unsigned int head, tail;
 
+                /* However GVT emulation depends upon intercepting CSB mmio */
+                if (unlikely(execlists->csb_use_mmio)) {
+                        buf = (u32 * __force)
+                                (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+                        execlists->csb_head = -1; /* force mmio read of CSB ptrs */
+                }
+
                 /* The write will be ordered by the uncached read (itself
                  * a memory barrier), so we do not need another in the form
                  * of a locked instruction. The race between the interrupt
@@ -562,9 +702,20 @@ static void intel_lrc_irq_handler(unsigned long data)
                  * is set and we do a new loop.
                  */
                 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-                head = readl(csb_mmio);
-                tail = GEN8_CSB_WRITE_PTR(head);
-                head = GEN8_CSB_READ_PTR(head);
+                if (unlikely(execlists->csb_head == -1)) { /* following a reset */
+                        head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+                        tail = GEN8_CSB_WRITE_PTR(head);
+                        head = GEN8_CSB_READ_PTR(head);
+                        execlists->csb_head = head;
+                } else {
+                        const int write_idx =
+                                intel_hws_csb_write_index(dev_priv) -
+                                I915_HWS_CSB_BUF0_INDEX;
+
+                        head = execlists->csb_head;
+                        tail = READ_ONCE(buf[write_idx]);
+                }
+
                 while (head != tail) {
                         struct drm_i915_gem_request *rq;
                         unsigned int status;
@@ -590,13 +741,12 @@ static void intel_lrc_irq_handler(unsigned long data)
                          * status notifier.
                          */
 
-                        status = readl(buf + 2 * head);
+                        status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
                         if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
                                 continue;
 
                         /* Check the context/desc id for this event matches */
-                        GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) !=
-                                         port->context_id);
+                        GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
 
                         rq = port_unpack(port, &count);
                         GEM_BUG_ON(count == 0);
@@ -608,8 +758,7 @@ static void intel_lrc_irq_handler(unsigned long data)
                                 trace_i915_gem_request_out(rq);
                                 i915_gem_request_put(rq);
 
-                                port[0] = port[1];
-                                memset(&port[1], 0, sizeof(port[1]));
+                                execlists_port_complete(execlists, port);
                         } else {
                                 port_set(port, port_pack(rq, count));
                         }
@@ -619,78 +768,28 @@ static void intel_lrc_irq_handler(unsigned long data)
                                    !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
                 }
 
-                writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
-                       csb_mmio);
+                if (head != execlists->csb_head) {
+                        execlists->csb_head = head;
+                        writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
+                               dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+                }
         }
 
         if (execlists_elsp_ready(engine))
                 execlists_dequeue(engine);
 
-        intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
+        intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
 }
 
-static bool
-insert_request(struct intel_engine_cs *engine,
-               struct i915_priotree *pt,
-               int prio)
+static void insert_request(struct intel_engine_cs *engine,
+                           struct i915_priotree *pt,
+                           int prio)
 {
-        struct i915_priolist *p;
-        struct rb_node **parent, *rb;
-        bool first = true;
+        struct i915_priolist *p = lookup_priolist(engine, pt, prio);
 
-        if (unlikely(engine->no_priolist))
-                prio = I915_PRIORITY_NORMAL;
-
-find_priolist:
-        /* most positive priority is scheduled first, equal priorities fifo */
-        rb = NULL;
-        parent = &engine->execlist_queue.rb_node;
-        while (*parent) {
-                rb = *parent;
-                p = rb_entry(rb, typeof(*p), node);
-                if (prio > p->priority) {
-                        parent = &rb->rb_left;
-                } else if (prio < p->priority) {
-                        parent = &rb->rb_right;
-                        first = false;
-                } else {
-                        list_add_tail(&pt->link, &p->requests);
-                        return false;
-                }
-        }
-
-        if (prio == I915_PRIORITY_NORMAL) {
-                p = &engine->default_priolist;
-        } else {
-                p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
-                /* Convert an allocation failure to a priority bump */
-                if (unlikely(!p)) {
-                        prio = I915_PRIORITY_NORMAL; /* recurses just once */
-
-                        /* To maintain ordering with all rendering, after an
-                         * allocation failure we have to disable all scheduling.
-                         * Requests will then be executed in fifo, and schedule
-                         * will ensure that dependencies are emitted in fifo.
-                         * There will be still some reordering with existing
-                         * requests, so if userspace lied about their
-                         * dependencies that reordering may be visible.
-                         */
-                        engine->no_priolist = true;
-                        goto find_priolist;
-                }
-        }
-
-        p->priority = prio;
-        rb_link_node(&p->node, rb, parent);
-        rb_insert_color(&p->node, &engine->execlist_queue);
-
-        INIT_LIST_HEAD(&p->requests);
-        list_add_tail(&pt->link, &p->requests);
-
-        if (first)
-                engine->execlist_first = &p->node;
-
-        return first;
+        list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
+        if (ptr_unmask_bits(p, 1) && execlists_elsp_ready(engine))
+                tasklet_hi_schedule(&engine->execlists.irq_tasklet);
 }
 
 static void execlists_submit_request(struct drm_i915_gem_request *request)
@@ -701,14 +800,9 @@ static void execlists_submit_request(struct drm_i915_gem_request *request)
         /* Will be called from irq-context when using foreign fences. */
         spin_lock_irqsave(&engine->timeline->lock, flags);
 
-        if (insert_request(engine,
-                           &request->priotree,
-                           request->priotree.priority)) {
-                if (execlists_elsp_ready(engine))
-                        tasklet_hi_schedule(&engine->irq_tasklet);
-        }
+        insert_request(engine, &request->priotree, request->priotree.priority);
 
-        GEM_BUG_ON(!engine->execlist_first);
+        GEM_BUG_ON(!engine->execlists.first);
         GEM_BUG_ON(list_empty(&request->priotree.link));
 
         spin_unlock_irqrestore(&engine->timeline->lock, flags);
@@ -914,27 +1008,14 @@ static int execlists_request_alloc(struct drm_i915_gem_request *request)
          */
         request->reserved_space += EXECLISTS_REQUEST_SIZE;
 
-        if (i915.enable_guc_submission) {
-                /*
-                 * Check that the GuC has space for the request before
-                 * going any further, as the i915_add_request() call
-                 * later on mustn't fail ...
-                 */
-                ret = i915_guc_wq_reserve(request);
-                if (ret)
-                        goto err;
-        }
-
         cs = intel_ring_begin(request, 0);
-        if (IS_ERR(cs)) {
-                ret = PTR_ERR(cs);
-                goto err_unreserve;
-        }
+        if (IS_ERR(cs))
+                return PTR_ERR(cs);
 
         if (!ce->initialised) {
                 ret = engine->init_context(request);
                 if (ret)
-                        goto err_unreserve;
+                        return ret;
 
                 ce->initialised = true;
         }
@@ -948,12 +1029,6 @@ static int execlists_request_alloc(struct drm_i915_gem_request *request)
 
         request->reserved_space -= EXECLISTS_REQUEST_SIZE;
         return 0;
-
-err_unreserve:
-        if (i915.enable_guc_submission)
-                i915_guc_wq_unreserve(request);
-err:
-        return ret;
 }
 
 /*
@@ -1116,13 +1191,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
         return batch;
 }
 
-static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
-{
-        *batch++ = MI_BATCH_BUFFER_END;
-
-        return batch;
-}
-
 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
 
 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
@@ -1179,7 +1247,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
                 return 0;
         case 9:
                 wa_bb_fn[0] = gen9_init_indirectctx_bb;
-                wa_bb_fn[1] = gen9_init_perctx_bb;
+                wa_bb_fn[1] = NULL;
                 break;
         case 8:
                 wa_bb_fn[0] = gen8_init_indirectctx_bb;
@@ -1210,7 +1278,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
                         ret = -EINVAL;
                         break;
                 }
-                batch_ptr = wa_bb_fn[i](engine, batch_ptr);
+                if (wa_bb_fn[i])
+                        batch_ptr = wa_bb_fn[i](engine, batch_ptr);
                 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
         }
 
@@ -1234,9 +1303,7 @@ static u8 gtiir[] = {
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
         struct drm_i915_private *dev_priv = engine->i915;
-        struct execlist_port *port = engine->execlist_port;
-        unsigned int n;
-        bool submit;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
         int ret;
 
         ret = intel_mocs_init_engine(engine);
@@ -1269,24 +1336,11 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
         I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
                    GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
         clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+        execlists->csb_head = -1;
 
         /* After a GPU reset, we may have requests to replay */
-        submit = false;
-        for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
-                if (!port_isset(&port[n]))
-                        break;
-
-                DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
-                                 engine->name, n,
-                                 port_request(&port[n])->global_seqno);
-
-                /* Discard the current inflight count */
-                port_set(&port[n], port_request(&port[n]));
-                submit = true;
-        }
-
-        if (submit && !i915.enable_guc_submission)
-                execlists_submit_ports(engine);
+        if (!i915_modparams.enable_guc_submission && execlists->first)
+                tasklet_schedule(&execlists->irq_tasklet);
 
         return 0;
 }
@@ -1327,9 +1381,12 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
 static void reset_common_ring(struct intel_engine_cs *engine,
                               struct drm_i915_gem_request *request)
 {
-        struct execlist_port *port = engine->execlist_port;
+        struct intel_engine_execlists * const execlists = &engine->execlists;
+        struct drm_i915_gem_request *rq, *rn;
         struct intel_context *ce;
-        unsigned int n;
+        unsigned long flags;
+
+        spin_lock_irqsave(&engine->timeline->lock, flags);
 
         /*
          * Catch up with any missed context-switch interrupts.
@@ -1340,20 +1397,26 @@ static void reset_common_ring(struct intel_engine_cs *engine,
          * guessing the missed context-switch events by looking at what
          * requests were completed.
          */
-        if (!request) {
-                for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
-                        i915_gem_request_put(port_request(&port[n]));
-                memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
-                return;
-        }
+        execlist_cancel_port_requests(execlists);
 
-        if (request->ctx != port_request(port)->ctx) {
-                i915_gem_request_put(port_request(port));
-                port[0] = port[1];
-                memset(&port[1], 0, sizeof(port[1]));
+        /* Push back any incomplete requests for replay after the reset. */
+        list_for_each_entry_safe_reverse(rq, rn,
+                                         &engine->timeline->requests, link) {
+                struct i915_priolist *p;
+
+                if (i915_gem_request_completed(rq))
+                        break;
+
+                __i915_gem_request_unsubmit(rq);
+
+                p = lookup_priolist(engine,
+                                    &rq->priotree,
+                                    rq->priotree.priority);
+                list_add(&rq->priotree.link,
+                         &ptr_mask_bits(p, 1)->requests);
         }
 
-        GEM_BUG_ON(request->ctx != port_request(port)->ctx);
+        spin_unlock_irqrestore(&engine->timeline->lock, flags);
 
         /* If the request was innocent, we leave the request in the ELSP
          * and will try to replay it on restarting. The context image may
@@ -1365,7 +1428,7 @@ static void reset_common_ring(struct intel_engine_cs *engine,
          * and have to at least restore the RING register in the context
          * image back to the expected values to skip over the guilty request.
          */
-        if (request->fence.error != -EIO)
+        if (!request || request->fence.error != -EIO)
                 return;
 
         /* We want a simple context + ring to execute the breadcrumb update.
@@ -1668,8 +1731,8 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
          * Tasklet cannot be active at this point due intel_mark_active/idle
          * so this is just for documentation.
          */
-        if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
-                tasklet_kill(&engine->irq_tasklet);
+        if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state)))
+                tasklet_kill(&engine->execlists.irq_tasklet);
 
         dev_priv = engine->i915;
 
@@ -1680,11 +1743,6 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
         if (engine->cleanup)
                 engine->cleanup(engine);
 
-        if (engine->status_page.vma) {
-                i915_gem_object_unpin_map(engine->status_page.vma->obj);
-                engine->status_page.vma = NULL;
-        }
-
         intel_engine_cleanup_common(engine);
 
         lrc_destroy_wa_ctx(engine);
@@ -1696,8 +1754,9 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
 static void execlists_set_default_submission(struct intel_engine_cs *engine)
 {
         engine->submit_request = execlists_submit_request;
+        engine->cancel_requests = execlists_cancel_requests;
         engine->schedule = execlists_schedule;
-        engine->irq_tasklet.func = intel_lrc_irq_handler;
+        engine->execlists.irq_tasklet.func = intel_lrc_irq_handler;
 }
 
 static void
@@ -1731,24 +1790,6 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
         engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
 }
 
-static int
-lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
-{
-        const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
-        void *hws;
-
-        /* The HWSP is part of the default context object in LRC mode. */
-        hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
-        if (IS_ERR(hws))
-                return PTR_ERR(hws);
-
-        engine->status_page.page_addr = hws + hws_offset;
-        engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
-        engine->status_page.vma = vma;
-
-        return 0;
-}
-
 static void
 logical_ring_setup(struct intel_engine_cs *engine)
 {
@@ -1772,32 +1813,23 @@ logical_ring_setup(struct intel_engine_cs *engine)
                                                      RING_CONTEXT_STATUS_BUF_BASE(engine),
                                                      FW_REG_READ);
 
-        engine->fw_domains = fw_domains;
+        engine->execlists.fw_domains = fw_domains;
 
-        tasklet_init(&engine->irq_tasklet,
+        tasklet_init(&engine->execlists.irq_tasklet,
                      intel_lrc_irq_handler, (unsigned long)engine);
 
         logical_ring_default_vfuncs(engine);
         logical_ring_default_irqs(engine);
 }
 
-static int
-logical_ring_init(struct intel_engine_cs *engine)
+static int logical_ring_init(struct intel_engine_cs *engine)
 {
-        struct i915_gem_context *dctx = engine->i915->kernel_context;
         int ret;
 
         ret = intel_engine_init_common(engine);
         if (ret)
                 goto error;
 
-        /* And setup the hardware status page. */
-        ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
-        if (ret) {
-                DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
-                goto error;
-        }
-
         return 0;
 
 error:
@@ -1955,13 +1987,12 @@ static void execlists_init_reg_state(u32 *regs,
         CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
         CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
         if (rcs) {
-                CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
+                struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
+
                 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
                 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
                         RING_INDIRECT_CTX_OFFSET(base), 0);
-
-                if (engine->wa_ctx.vma) {
-                        struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
+                if (wa_ctx->indirect_ctx.size) {
                         u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
 
                         regs[CTX_RCS_INDIRECT_CTX + 1] =
@@ -1970,6 +2001,11 @@ static void execlists_init_reg_state(u32 *regs,
 
                         regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
                                 intel_lr_indirect_ctx_offset(engine) << 6;
+                }
+
+                CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
+                if (wa_ctx->per_ctx.size) {
+                        u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
 
                         regs[CTX_BB_PER_CTX_PTR + 1] =
                                 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
@@ -2054,8 +2090,11 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
 
         context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
 
-        /* One extra page as the sharing data between driver and GuC */
-        context_size += PAGE_SIZE * LRC_PPHWSP_PN;
+        /*
+         * Before the actual start of the context image, we insert a few pages
+         * for our own use and for sharing with the GuC.
+         */
+        context_size += LRC_HEADER_PAGES * PAGE_SIZE;
 
         ctx_obj = i915_gem_object_create(ctx->i915, context_size);
         if (IS_ERR(ctx_obj)) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 57ef5833c427..314adee7127a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -25,6 +25,7 @@
 #define _INTEL_LRC_H_
 
 #include "intel_ringbuffer.h"
+#include "i915_gem_context.h"
 
 #define GEN8_LR_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
 
@@ -69,17 +70,42 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine);
 
 /* Logical Ring Contexts */
 
-/* One extra page is added before LRC for GuC as shared data */
+/*
+ * We allocate a header at the start of the context image for our own
+ * use, therefore the actual location of the logical state is offset
+ * from the start of the VMA. The layout is
+ *
+ * | [guc]          | [hwsp] [logical state] |
+ * |<- our header ->|<- context image      ->|
+ *
+ */
+/* The first page is used for sharing data with the GuC */
 #define LRC_GUCSHR_PN   (0)
-#define LRC_PPHWSP_PN   (LRC_GUCSHR_PN + 1)
-#define LRC_STATE_PN    (LRC_PPHWSP_PN + 1)
+#define LRC_GUCSHR_SZ   (1)
+/* At the start of the context image is its per-process HWS page */
+#define LRC_PPHWSP_PN   (LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
+#define LRC_PPHWSP_SZ   (1)
+/* Finally we have the logical state for the context */
+#define LRC_STATE_PN    (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
+
+/*
+ * Currently we include the PPHWSP in __intel_engine_context_size() so
+ * the size of the header is synonymous with the start of the PPHWSP.
+ */
+#define LRC_HEADER_PAGES LRC_PPHWSP_PN
 
 struct drm_i915_private;
 struct i915_gem_context;
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
-uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-                                     struct intel_engine_cs *engine);
+
+static inline uint64_t
+intel_lr_context_descriptor(struct i915_gem_context *ctx,
+                            struct intel_engine_cs *engine)
+{
+        return ctx->engine[engine->id].lrc_desc;
+}
+
 
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index a9813aea89d8..a55954a89148 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -880,8 +880,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
         struct drm_i915_private *dev_priv = to_i915(dev);
 
         /* use the module option value if specified */
-        if (i915.lvds_channel_mode > 0)
-                return i915.lvds_channel_mode == 2;
+        if (i915_modparams.lvds_channel_mode > 0)
+                return i915_modparams.lvds_channel_mode == 2;
 
         /* single channel LVDS is limited to 112 MHz */
         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 951e834dd274..28a778b785ac 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -30,6 +30,21 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+static void intel_connector_update_eld_conn_type(struct drm_connector *connector)
+{
+        u8 conn_type;
+
+        if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+            connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+                conn_type = DRM_ELD_CONN_TYPE_DP;
+        } else {
+                conn_type = DRM_ELD_CONN_TYPE_HDMI;
+        }
+
+        connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] &= ~DRM_ELD_CONN_TYPE_MASK;
+        connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= conn_type;
+}
+
 /**
  * intel_connector_update_modes - update connector from edid
  * @connector: DRM connector device to use
@@ -44,6 +59,8 @@ int intel_connector_update_modes(struct drm_connector *connector,
         ret = drm_add_edid_modes(connector, edid);
         drm_edid_to_eld(connector, edid);
 
+        intel_connector_update_eld_conn_type(connector);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 98154efcb2f4..1d946240e55f 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -921,7 +921,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
 {
         struct intel_opregion *opregion = &dev_priv->opregion;
         const struct firmware *fw = NULL;
-        const char *name = i915.vbt_firmware;
+        const char *name = i915_modparams.vbt_firmware;
         int ret;
 
         if (!name || !*name)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index aace22e7ccac..1b397b41cb4f 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1134,7 +1134,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
         if (!params)
                 return -ENOMEM;
 
-        drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
+        drmmode_crtc = drm_crtc_find(dev, file_priv, put_image_rec->crtc_id);
         if (!drmmode_crtc) {
                 ret = -ENOENT;
                 goto out_free;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 3b1c5d783ee7..adc51e452e3e 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -379,13 +379,13 @@ enum drm_connector_status
 intel_panel_detect(struct drm_i915_private *dev_priv)
 {
         /* Assume that the BIOS does not lie through the OpRegion... */
-        if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) {
+        if (!i915_modparams.panel_ignore_lid && dev_priv->opregion.lid_state) {
                 return *dev_priv->opregion.lid_state & 0x1 ?
                         connector_status_connected :
                         connector_status_disconnected;
         }
 
-        switch (i915.panel_ignore_lid) {
+        switch (i915_modparams.panel_ignore_lid) {
         case -2:
                 return connector_status_connected;
         case -1:
@@ -465,10 +465,10 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector,
 
         WARN_ON(panel->backlight.max == 0);
 
-        if (i915.invert_brightness < 0)
+        if (i915_modparams.invert_brightness < 0)
                 return val;
 
-        if (i915.invert_brightness > 0 ||
+        if (i915_modparams.invert_brightness > 0 ||
             dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
                 return panel->backlight.max - val + panel->backlight.min;
         }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0201816a4229..c66af09e27a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,23 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+        if (HAS_LLC(dev_priv)) {
+                /*
+                 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+                 * Display WA#0390: skl,kbl
+                 *
+                 * Must match Sampler, Pixel Back End, and Media. See
+                 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+                 */
+                I915_WRITE(CHICKEN_PAR1_1,
+                           I915_READ(CHICKEN_PAR1_1) |
+                           SKL_DE_COMPRESSED_HASH_MODE);
+        }
+
         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
         I915_WRITE(CHICKEN_PAR1_1,
                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
-        /*
-         * Display WA#0390: skl,bxt,kbl,glk
-         *
-         * Must match Sampler, Pixel Back End, and Media
-         * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31).
-         *
-         * Including bits outside the page in the hash would
-         * require 2 (or 4?) MiB alignment of resources. Just
-         * assume the defaul hashing mode which only uses bits
-         * within the page.
-         */
-        I915_WRITE(CHICKEN_PAR1_1,
-                   I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE);
-
         I915_WRITE(GEN8_CONFIG0,
                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
@@ -4376,134 +4375,147 @@ skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
                                             downscale_amount);
 }
 
-static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
-                                struct intel_crtc_state *cstate,
-                                const struct intel_plane_state *intel_pstate,
-                                uint16_t ddb_allocation,
-                                int level,
-                                uint16_t *out_blocks, /* out */
-                                uint8_t *out_lines, /* out */
-                                bool *enabled /* out */)
+static int
+skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
+                            struct intel_crtc_state *cstate,
+                            const struct intel_plane_state *intel_pstate,
+                            struct skl_wm_params *wp)
 {
         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
         const struct drm_plane_state *pstate = &intel_pstate->base;
         const struct drm_framebuffer *fb = pstate->fb;
-        uint32_t latency = dev_priv->wm.skl_latency[level];
-        uint_fixed_16_16_t method1, method2;
-        uint_fixed_16_16_t plane_blocks_per_line;
-        uint_fixed_16_16_t selected_result;
         uint32_t interm_pbpl;
-        uint32_t plane_bytes_per_line;
-        uint32_t res_blocks, res_lines;
-        uint8_t cpp;
-        uint32_t width = 0;
-        uint32_t plane_pixel_rate;
-        uint_fixed_16_16_t y_tile_minimum;
-        uint32_t y_min_scanlines;
         struct intel_atomic_state *state =
                 to_intel_atomic_state(cstate->base.state);
         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
-        bool y_tiled, x_tiled;
 
-        if (latency == 0 ||
-            !intel_wm_plane_visible(cstate, intel_pstate)) {
-                *enabled = false;
+        if (!intel_wm_plane_visible(cstate, intel_pstate))
                 return 0;
-        }
 
-        y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-                  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-                  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-                  fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-        x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
-
-        /* Display WA #1141: kbl,cfl */
-        if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
-            dev_priv->ipc_enabled)
-                latency += 4;
-
-        if (apply_memory_bw_wa && x_tiled)
-                latency += 15;
+        wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+                      fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
+                      fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+        wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
+        wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+                         fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 
         if (plane->id == PLANE_CURSOR) {
-                width = intel_pstate->base.crtc_w;
+                wp->width = intel_pstate->base.crtc_w;
         } else {
                 /*
                  * Src coordinates are already rotated by 270 degrees for
                  * the 90/270 degree plane rotation cases (to match the
                  * GTT mapping), hence no need to account for rotation here.
                  */
-                width = drm_rect_width(&intel_pstate->base.src) >> 16;
+                wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
         }
 
-        cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
-                                                        fb->format->cpp[0];
-        plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
+        wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
+                                                            fb->format->cpp[0];
+        wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
+                                                             intel_pstate);
 
         if (drm_rotation_90_or_270(pstate->rotation)) {
 
-                switch (cpp) {
+                switch (wp->cpp) {
                 case 1:
-                        y_min_scanlines = 16;
+                        wp->y_min_scanlines = 16;
                         break;
                 case 2:
-                        y_min_scanlines = 8;
+                        wp->y_min_scanlines = 8;
                         break;
                 case 4:
-                        y_min_scanlines = 4;
+                        wp->y_min_scanlines = 4;
                         break;
                 default:
-                        MISSING_CASE(cpp);
+                        MISSING_CASE(wp->cpp);
                         return -EINVAL;
                 }
         } else {
-                y_min_scanlines = 4;
+                wp->y_min_scanlines = 4;
         }
 
         if (apply_memory_bw_wa)
-                y_min_scanlines *= 2;
+                wp->y_min_scanlines *= 2;
 
-        plane_bytes_per_line = width * cpp;
-        if (y_tiled) {
-                interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
-                                           y_min_scanlines, 512);
+        wp->plane_bytes_per_line = wp->width * wp->cpp;
+        if (wp->y_tiled) {
+                interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
+                                           wp->y_min_scanlines, 512);
 
                 if (INTEL_GEN(dev_priv) >= 10)
                         interm_pbpl++;
 
-                plane_blocks_per_line = div_fixed16(interm_pbpl,
-                                                        y_min_scanlines);
-        } else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
-                interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
-                plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+                wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
+                                                        wp->y_min_scanlines);
+        } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
+                interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
+                wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
         } else {
-                interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
-                plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+                interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
+                wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
+        }
+
+        wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
+                                             wp->plane_blocks_per_line);
+        wp->linetime_us = fixed16_to_u32_round_up(
+                                        intel_get_linetime_us(cstate));
+
+        return 0;
+}
+
+static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
+                                struct intel_crtc_state *cstate,
+                                const struct intel_plane_state *intel_pstate,
+                                uint16_t ddb_allocation,
+                                int level,
+                                const struct skl_wm_params *wp,
+                                uint16_t *out_blocks, /* out */
+                                uint8_t *out_lines, /* out */
+                                bool *enabled /* out */)
+{
+        const struct drm_plane_state *pstate = &intel_pstate->base;
+        uint32_t latency = dev_priv->wm.skl_latency[level];
+        uint_fixed_16_16_t method1, method2;
+        uint_fixed_16_16_t selected_result;
+        uint32_t res_blocks, res_lines;
+        struct intel_atomic_state *state =
+                to_intel_atomic_state(cstate->base.state);
+        bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+
+        if (latency == 0 ||
+            !intel_wm_plane_visible(cstate, intel_pstate)) {
+                *enabled = false;
+                return 0;
         }
 
-        method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
-        method2 = skl_wm_method2(plane_pixel_rate,
+        /* Display WA #1141: kbl,cfl */
+        if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
+            IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
+            dev_priv->ipc_enabled)
+                latency += 4;
+
+        if (apply_memory_bw_wa && wp->x_tiled)
+                latency += 15;
+
+        method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
+                                 wp->cpp, latency);
+        method2 = skl_wm_method2(wp->plane_pixel_rate,
                                  cstate->base.adjusted_mode.crtc_htotal,
                                  latency,
-                                 plane_blocks_per_line);
+                                 wp->plane_blocks_per_line);
 
-        y_tile_minimum = mul_u32_fixed16(y_min_scanlines,
-                                         plane_blocks_per_line);
-
-        if (y_tiled) {
-                selected_result = max_fixed16(method2, y_tile_minimum);
+        if (wp->y_tiled) {
+                selected_result = max_fixed16(method2, wp->y_tile_minimum);
         } else {
-                uint32_t linetime_us;
-
-                linetime_us = fixed16_to_u32_round_up(
-                                intel_get_linetime_us(cstate));
-                if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
-                    (plane_bytes_per_line / 512 < 1))
+                if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
+                     512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
                         selected_result = method2;
                 else if (ddb_allocation >=
-                         fixed16_to_u32_round_up(plane_blocks_per_line))
+                         fixed16_to_u32_round_up(wp->plane_blocks_per_line))
                         selected_result = min_fixed16(method1, method2);
-                else if (latency >= linetime_us)
+                else if (latency >= wp->linetime_us)
                         selected_result = min_fixed16(method1, method2);
                 else
                         selected_result = method1;
@@ -4511,19 +4523,18 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
         res_lines = div_round_up_fixed16(selected_result,
-                                         plane_blocks_per_line);
+                                         wp->plane_blocks_per_line);
 
         /* Display WA #1125: skl,bxt,kbl,glk */
-        if (level == 0 &&
-            (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
-                res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
+        if (level == 0 && wp->rc_surface)
+                res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
 
         /* Display WA #1126: skl,bxt,kbl,glk */
         if (level >= 1 && level <= 7) {
-                if (y_tiled) {
-                        res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
-                        res_lines += y_min_scanlines;
+                if (wp->y_tiled) {
+                        res_blocks += fixed16_to_u32_round_up(
+                                                        wp->y_tile_minimum);
+                        res_lines += wp->y_min_scanlines;
                 } else {
                         res_blocks++;
                 }
@@ -4561,6 +4572,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
                       struct skl_ddb_allocation *ddb,
                       struct intel_crtc_state *cstate,
                       const struct intel_plane_state *intel_pstate,
+                      const struct skl_wm_params *wm_params,
                       struct skl_plane_wm *wm)
 {
         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
@@ -4584,6 +4596,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
                                            intel_pstate,
                                            ddb_blocks,
                                            level,
+                                           wm_params,
                                            &result->plane_res_b,
                                            &result->plane_res_l,
                                            &result->plane_en);
@@ -4609,20 +4622,65 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
 
         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
 
-        /* Display WA #1135: bxt. */
-        if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
-                linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
+        /* Display WA #1135: bxt:ALL GLK:ALL */
+        if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
+            dev_priv->ipc_enabled)
+                linetime_wm /= 2;
 
         return linetime_wm;
 }
 
 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
+                                      struct skl_wm_params *wp,
+                                      struct skl_wm_level *wm_l0,
+                                      uint16_t ddb_allocation,
                                       struct skl_wm_level *trans_wm /* out */)
 {
+        struct drm_device *dev = cstate->base.crtc->dev;
+        const struct drm_i915_private *dev_priv = to_i915(dev);
+        uint16_t trans_min, trans_y_tile_min;
+        const uint16_t trans_amount = 10; /* This is configurable amount */
+        uint16_t trans_offset_b, res_blocks;
+
         if (!cstate->base.active)
+                goto exit;
+
+        /* Transition WM are not recommended by HW team for GEN9 */
+        if (INTEL_GEN(dev_priv) <= 9)
+                goto exit;
+
+        /* Transition WM don't make any sense if ipc is disabled */
+        if (!dev_priv->ipc_enabled)
+                goto exit;
+
+        if (INTEL_GEN(dev_priv) >= 10)
+                trans_min = 4;
+
+        trans_offset_b = trans_min + trans_amount;
+
+        if (wp->y_tiled) {
+                trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
+                                                        wp->y_tile_minimum);
+                res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
+                                trans_offset_b;
+        } else {
+                res_blocks = wm_l0->plane_res_b + trans_offset_b;
+
+                /* WA BUG:1938466 add one block for non y-tile planes */
+                if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+                        res_blocks += 1;
+
+        }
+
+        res_blocks += 1;
+
+        if (res_blocks < ddb_allocation) {
+                trans_wm->plane_res_b = res_blocks;
+                trans_wm->plane_en = true;
                 return;
+        }
 
-        /* Until we know more, just disable transition WMs */
+exit:
         trans_wm->plane_en = false;
 }
 
@@ -4648,14 +4706,25 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
                 const struct intel_plane_state *intel_pstate =
                                                 to_intel_plane_state(pstate);
                 enum plane_id plane_id = to_intel_plane(plane)->id;
+                struct skl_wm_params wm_params;
+                enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
+                uint16_t ddb_blocks;
 
                 wm = &pipe_wm->planes[plane_id];
+                ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+                memset(&wm_params, 0, sizeof(struct skl_wm_params));
+
+                ret = skl_compute_plane_wm_params(dev_priv, cstate,
+                                                  intel_pstate, &wm_params);
+                if (ret)
+                        return ret;
 
                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
-                                            intel_pstate, wm);
+                                            intel_pstate, &wm_params, wm);
                 if (ret)
                         return ret;
-                skl_compute_transition_wm(cstate, &wm->trans_wm);
+                skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
+                                          ddb_blocks, &wm->trans_wm);
         }
         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
 
@@ -5754,6 +5823,30 @@ void intel_update_watermarks(struct intel_crtc *crtc)
                 dev_priv->display.update_wm(crtc);
 }
 
+void intel_enable_ipc(struct drm_i915_private *dev_priv)
+{
+        u32 val;
+
+        val = I915_READ(DISP_ARB_CTL2);
+
+        if (dev_priv->ipc_enabled)
+                val |= DISP_IPC_ENABLE;
+        else
+                val &= ~DISP_IPC_ENABLE;
+
+        I915_WRITE(DISP_ARB_CTL2, val);
+}
+
+void intel_init_ipc(struct drm_i915_private *dev_priv)
+{
+        dev_priv->ipc_enabled = false;
+        if (!HAS_IPC(dev_priv))
+                return;
+
+        dev_priv->ipc_enabled = true;
+        intel_enable_ipc(dev_priv);
+}
+
 /*
  * Lock protecting IPS related data structures
  */
@@ -7732,7 +7825,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
          * requirement.
          */
-        if (!i915.enable_rc6) {
+        if (!i915_modparams.enable_rc6) {
                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
                 intel_runtime_pm_get(dev_priv);
         }
@@ -7789,7 +7882,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
         if (IS_VALLEYVIEW(dev_priv))
                 valleyview_cleanup_gt_powersave(dev_priv);
 
-        if (!i915.enable_rc6)
+        if (!i915_modparams.enable_rc6)
                 intel_runtime_pm_put(dev_priv);
 }
 
@@ -7911,7 +8004,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
         if (IS_ERR(req))
                 goto unlock;
 
-        if (!i915.enable_execlists && i915_switch_context(req) == 0)
+        if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
                 rcs->init_context(req);
 
         /* Mark the device busy, calling intel_enable_gt_powersave() */
@@ -8276,7 +8369,8 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
                 return;
 
         /* Wa #1181 */
-        I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+        I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
+                   CNP_PWM_CGE_GATING_DISABLE);
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f62ab05d3d62..5419cda83ba8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -117,46 +117,41 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp,
         I915_WRITE(VLV_VSCSDP(crtc->pipe), val);
 }
 
-static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp,
-                                 const struct intel_crtc_state *crtc_state)
+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
+                              const struct intel_crtc_state *crtc_state)
 {
         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
         struct edp_vsc_psr psr_vsc;
 
-        /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-        memset(&psr_vsc, 0, sizeof(psr_vsc));
-        psr_vsc.sdp_header.HB0 = 0;
-        psr_vsc.sdp_header.HB1 = 0x7;
-        if (dev_priv->psr.colorimetry_support &&
-                dev_priv->psr.y_cord_support) {
-                psr_vsc.sdp_header.HB2 = 0x5;
-                psr_vsc.sdp_header.HB3 = 0x13;
-        } else if (dev_priv->psr.y_cord_support) {
-                psr_vsc.sdp_header.HB2 = 0x4;
-                psr_vsc.sdp_header.HB3 = 0xe;
+        if (dev_priv->psr.psr2_support) {
+                /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
+                memset(&psr_vsc, 0, sizeof(psr_vsc));
+                psr_vsc.sdp_header.HB0 = 0;
+                psr_vsc.sdp_header.HB1 = 0x7;
+                if (dev_priv->psr.colorimetry_support &&
+                    dev_priv->psr.y_cord_support) {
+                        psr_vsc.sdp_header.HB2 = 0x5;
+                        psr_vsc.sdp_header.HB3 = 0x13;
+                } else if (dev_priv->psr.y_cord_support) {
+                        psr_vsc.sdp_header.HB2 = 0x4;
+                        psr_vsc.sdp_header.HB3 = 0xe;
+                } else {
+                        psr_vsc.sdp_header.HB2 = 0x3;
+                        psr_vsc.sdp_header.HB3 = 0xc;
+                }
         } else {
-                psr_vsc.sdp_header.HB2 = 0x3;
-                psr_vsc.sdp_header.HB3 = 0xc;
+                /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
+                memset(&psr_vsc, 0, sizeof(psr_vsc));
+                psr_vsc.sdp_header.HB0 = 0;
+                psr_vsc.sdp_header.HB1 = 0x7;
+                psr_vsc.sdp_header.HB2 = 0x2;
+                psr_vsc.sdp_header.HB3 = 0x8;
         }
 
         intel_psr_write_vsc(intel_dp, &psr_vsc);
 }
 
-static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
-                              const struct intel_crtc_state *crtc_state)
-{
-        struct edp_vsc_psr psr_vsc;
-
-        /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-        memset(&psr_vsc, 0, sizeof(psr_vsc));
-        psr_vsc.sdp_header.HB0 = 0;
-        psr_vsc.sdp_header.HB1 = 0x7;
-        psr_vsc.sdp_header.HB2 = 0x2;
-        psr_vsc.sdp_header.HB3 = 0x8;
-        intel_psr_write_vsc(intel_dp, &psr_vsc);
-}
-
 static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 {
         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
@@ -239,7 +234,7 @@ static void vlv_psr_enable_source(struct intel_dp *intel_dp,
         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 
-        /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
+        /* Transition from PSR_state 0 (disabled) to PSR_state 1 (inactive) */
         I915_WRITE(VLV_PSRCTL(crtc->pipe),
                    VLV_EDP_PSR_MODE_SW_TIMER |
                    VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
@@ -254,16 +249,17 @@ static void vlv_psr_activate(struct intel_dp *intel_dp)
         struct drm_crtc *crtc = dig_port->base.base.crtc;
         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 
-        /* Let's do the transition from PSR_state 1 to PSR_state 2
-         * that is PSR transition to active - static frame transmission.
-         * Then Hardware is responsible for the transition to PSR_state 3
-         * that is PSR active - no Remote Frame Buffer (RFB) update.
+        /*
+         * Let's do the transition from PSR_state 1 (inactive) to
+         * PSR_state 2 (transition to active - static frame transmission).
+         * Then Hardware is responsible for the transition to
+         * PSR_state 3 (active - no Remote Frame Buffer (RFB) update).
          */
         I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
                    VLV_EDP_PSR_ACTIVE_ENTRY);
 }
 
-static void intel_enable_source_psr1(struct intel_dp *intel_dp)
+static void hsw_activate_psr1(struct intel_dp *intel_dp)
 {
         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
         struct drm_device *dev = dig_port->base.base.dev;
@@ -317,7 +313,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
         I915_WRITE(EDP_PSR_CTL, val);
 }
 
-static void intel_enable_source_psr2(struct intel_dp *intel_dp)
+static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
         struct drm_device *dev = dig_port->base.base.dev;
@@ -331,6 +327,7 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
          */
         uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
         uint32_t val;
+        uint8_t sink_latency;
 
         val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
@@ -338,8 +335,16 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
          * mesh at all with our frontbuffer tracking. And the hw alone isn't
          * good enough. */
         val |= EDP_PSR2_ENABLE |
-                EDP_SU_TRACK_ENABLE |
-                EDP_FRAMES_BEFORE_SU_ENTRY;
+                EDP_SU_TRACK_ENABLE;
+
+        if (drm_dp_dpcd_readb(&intel_dp->aux,
+                                DP_SYNCHRONIZATION_LATENCY_IN_SINK,
+                                &sink_latency) == 1) {
+                sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
+        } else {
+                sink_latency = 0;
+        }
+        val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
 
         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
                 val |= EDP_PSR2_TP2_TIME_2500;
@@ -353,17 +358,22 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
         I915_WRITE(EDP_PSR2_CTL, val);
 }
 
-static void hsw_psr_enable_source(struct intel_dp *intel_dp)
+static void hsw_psr_activate(struct intel_dp *intel_dp)
 {
         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
         struct drm_device *dev = dig_port->base.base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
 
+        /* On HSW+ after we enable PSR on source it will activate it
+         * as soon as it match configure idle_frame count. So
+         * we just actually enable it here on activation time.
+         */
+
         /* psr1 and psr2 are mutually exclusive.*/
         if (dev_priv->psr.psr2_support)
-                intel_enable_source_psr2(intel_dp);
+                hsw_activate_psr2(intel_dp);
         else
-                intel_enable_source_psr1(intel_dp);
+                hsw_activate_psr1(intel_dp);
 }
 
 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
@@ -395,7 +405,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
                 return false;
         }
 
-        if (!i915.enable_psr) {
+        if (!i915_modparams.enable_psr) {
                 DRM_DEBUG_KMS("PSR disable by flag\n");
                 return false;
         }
@@ -467,19 +477,46 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
         WARN_ON(dev_priv->psr.active);
         lockdep_assert_held(&dev_priv->psr.lock);
 
-        /* Enable/Re-enable PSR on the host */
-        if (HAS_DDI(dev_priv))
-                /* On HSW+ after we enable PSR on source it will activate it
-                 * as soon as it match configure idle_frame count. So
-                 * we just actually enable it here on activation time.
-                 */
-                hsw_psr_enable_source(intel_dp);
-        else
-                vlv_psr_activate(intel_dp);
-
+        dev_priv->psr.activate(intel_dp);
         dev_priv->psr.active = true;
 }
 
+static void hsw_psr_enable_source(struct intel_dp *intel_dp,
+                                  const struct intel_crtc_state *crtc_state)
+{
+        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+        struct drm_device *dev = dig_port->base.base.dev;
+        struct drm_i915_private *dev_priv = to_i915(dev);
+        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+        u32 chicken;
+
+        if (dev_priv->psr.psr2_support) {
+                chicken = PSR2_VSC_ENABLE_PROG_HEADER;
+                if (dev_priv->psr.y_cord_support)
+                        chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
+                I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
+
+                I915_WRITE(EDP_PSR_DEBUG_CTL,
+                           EDP_PSR_DEBUG_MASK_MEMUP |
+                           EDP_PSR_DEBUG_MASK_HPD |
+                           EDP_PSR_DEBUG_MASK_LPSP |
+                           EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+                           EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
+        } else {
+                /*
+                 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+                 * and HPD. also mask LPSP to avoid dependency on other
+                 * drivers that might block runtime_pm besides
+                 * preventing  other hw tracking issues now we can rely
+                 * on frontbuffer tracking.
+                 */
+                I915_WRITE(EDP_PSR_DEBUG_CTL,
+                           EDP_PSR_DEBUG_MASK_MEMUP |
+                           EDP_PSR_DEBUG_MASK_HPD |
+                           EDP_PSR_DEBUG_MASK_LPSP);
+        }
+}
+
 /**
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
@@ -493,19 +530,16 @@ void intel_psr_enable(struct intel_dp *intel_dp,
         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
         struct drm_device *dev = intel_dig_port->base.base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
-        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-        u32 chicken;
 
-        if (!HAS_PSR(dev_priv)) {
-                DRM_DEBUG_KMS("PSR not supported on this platform\n");
+        if (!HAS_PSR(dev_priv))
                 return;
-        }
 
         if (!is_edp_psr(intel_dp)) {
                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
                 return;
         }
 
+        WARN_ON(dev_priv->drrs.dp);
         mutex_lock(&dev_priv->psr.lock);
         if (dev_priv->psr.enabled) {
                 DRM_DEBUG_KMS("PSR already in use\n");
@@ -517,72 +551,28 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 
         dev_priv->psr.busy_frontbuffer_bits = 0;
 
-        if (HAS_DDI(dev_priv)) {
-                if (dev_priv->psr.psr2_support) {
-                        skl_psr_setup_su_vsc(intel_dp, crtc_state);
-
-                        chicken = PSR2_VSC_ENABLE_PROG_HEADER;
-                        if (dev_priv->psr.y_cord_support)
-                                chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
-                        I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
-                        I915_WRITE(EDP_PSR_DEBUG_CTL,
-                                   EDP_PSR_DEBUG_MASK_MEMUP |
-                                   EDP_PSR_DEBUG_MASK_HPD |
-                                   EDP_PSR_DEBUG_MASK_LPSP |
-                                   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
-                                   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
-                } else {
-                        /* set up vsc header for psr1 */
-                        hsw_psr_setup_vsc(intel_dp, crtc_state);
-
-                        /*
-                         * Per Spec: Avoid continuous PSR exit by masking MEMUP
-                         * and HPD. also mask LPSP to avoid dependency on other
-                         * drivers that might block runtime_pm besides
-                         * preventing  other hw tracking issues now we can rely
-                         * on frontbuffer tracking.
-                         */
-                        I915_WRITE(EDP_PSR_DEBUG_CTL,
-                                   EDP_PSR_DEBUG_MASK_MEMUP |
-                                   EDP_PSR_DEBUG_MASK_HPD |
-                                   EDP_PSR_DEBUG_MASK_LPSP);
-                }
-
-                /* Enable PSR on the panel */
-                hsw_psr_enable_sink(intel_dp);
+        dev_priv->psr.setup_vsc(intel_dp, crtc_state);
+        dev_priv->psr.enable_sink(intel_dp);
+        dev_priv->psr.enable_source(intel_dp, crtc_state);
+        dev_priv->psr.enabled = intel_dp;
 
-                if (INTEL_GEN(dev_priv) >= 9)
-                        intel_psr_activate(intel_dp);
+        if (INTEL_GEN(dev_priv) >= 9) {
+                intel_psr_activate(intel_dp);
         } else {
-                vlv_psr_setup_vsc(intel_dp, crtc_state);
-
-                /* Enable PSR on the panel */
-                vlv_psr_enable_sink(intel_dp);
-
-                /* On HSW+ enable_source also means go to PSR entry/active
-                 * state as soon as idle_frame achieved and here would be
-                 * to soon. However on VLV enable_source just enable PSR
-                 * but let it on inactive state. So we might do this prior
-                 * to active transition, i.e. here.
+                /*
+                 * FIXME: Activation should happen immediately since this
+                 * function is just called after pipe is fully trained and
+                 * enabled.
+                 * However on some platforms we face issues when first
+                 * activation follows a modeset so quickly.
+                 *     - On VLV/CHV we get bank screen on first activation
+                 *     - On HSW/BDW we get a recoverable frozen screen until
+                 *       next exit-activate sequence.
                  */
-                vlv_psr_enable_source(intel_dp, crtc_state);
-        }
-
-        /*
-         * FIXME: Activation should happen immediately since this function
-         * is just called after pipe is fully trained and enabled.
-         * However on every platform we face issues when first activation
-         * follows a modeset so quickly.
-         *     - On VLV/CHV we get bank screen on first activation
-         *     - On HSW/BDW we get a recoverable frozen screen until next
-         *       exit-activate sequence.
-         */
-        if (INTEL_GEN(dev_priv) < 9)
                 schedule_delayed_work(&dev_priv->psr.work,
                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
+        }
 
-        dev_priv->psr.enabled = intel_dp;
 unlock:
         mutex_unlock(&dev_priv->psr.lock);
 }
@@ -597,7 +587,7 @@ static void vlv_psr_disable(struct intel_dp *intel_dp,
         uint32_t val;
 
         if (dev_priv->psr.active) {
-                /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
+                /* Put VLV PSR back to PSR_state 0 (disabled). */
                 if (intel_wait_for_register(dev_priv,
                                             VLV_PSRSTAT(crtc->pipe),
                                             VLV_EDP_PSR_IN_TRANS,
@@ -678,17 +668,16 @@ void intel_psr_disable(struct intel_dp *intel_dp,
         struct drm_device *dev = intel_dig_port->base.base.dev;
         struct drm_i915_private *dev_priv = to_i915(dev);
 
+        if (!HAS_PSR(dev_priv))
+                return;
+
         mutex_lock(&dev_priv->psr.lock);
         if (!dev_priv->psr.enabled) {
                 mutex_unlock(&dev_priv->psr.lock);
                 return;
         }
 
-        /* Disable PSR on Source */
-        if (HAS_DDI(dev_priv))
-                hsw_psr_disable(intel_dp, old_crtc_state);
-        else
-                vlv_psr_disable(intel_dp, old_crtc_state);
+        dev_priv->psr.disable_source(intel_dp, old_crtc_state);
 
         /* Disable PSR on Sink */
         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
@@ -788,17 +777,20 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
         } else {
                 val = I915_READ(VLV_PSRCTL(pipe));
 
-                /* Here we do the transition from PSR_state 3 to PSR_state 5
-                 * directly once PSR State 4 that is active with single frame
-                 * update can be skipped. PSR_state 5 that is PSR exit then
-                 * Hardware is responsible to transition back to PSR_state 1
-                 * that is PSR inactive. Same state after
-                 * vlv_edp_psr_enable_source.
+                /*
+                 * Here we do the transition drirectly from
+                 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to
+                 * PSR_state 5 (exit).
+                 * PSR State 4 (active with single frame update) can be skipped.
+                 * On PSR_state 5 (exit) Hardware is responsible to transition
+                 * back to PSR_state 1 (inactive).
+                 * Now we are at Same state after vlv_psr_enable_source.
                  */
                 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
                 I915_WRITE(VLV_PSRCTL(pipe), val);
 
-                /* Send AUX wake up - Spec says after transitioning to PSR
+                /*
+                 * Send AUX wake up - Spec says after transitioning to PSR
                  * active we have to send AUX wake up by writing 01h in DPCD
                  * 600h of sink device.
                  * XXX: This might slow down the transition, but without this
@@ -829,6 +821,9 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
         enum pipe pipe;
         u32 val;
 
+        if (!HAS_PSR(dev_priv))
+                return;
+
         /*
          * Single frame update is already supported on BDW+ but it requires
          * many W/A and it isn't really needed.
@@ -875,6 +870,9 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
         struct drm_crtc *crtc;
         enum pipe pipe;
 
+        if (!HAS_PSR(dev_priv))
+                return;
+
         mutex_lock(&dev_priv->psr.lock);
         if (!dev_priv->psr.enabled) {
                 mutex_unlock(&dev_priv->psr.lock);
@@ -912,6 +910,9 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
         struct drm_crtc *crtc;
         enum pipe pipe;
 
+        if (!HAS_PSR(dev_priv))
+                return;
+
         mutex_lock(&dev_priv->psr.lock);
         if (!dev_priv->psr.enabled) {
                 mutex_unlock(&dev_priv->psr.lock);
@@ -944,12 +945,15 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
  */
 void intel_psr_init(struct drm_i915_private *dev_priv)
 {
+        if (!HAS_PSR(dev_priv))
+                return;
+
         dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
                 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 
         /* Per platform default: all disabled. */
-        if (i915.enable_psr == -1)
-                i915.enable_psr = 0;
+        if (i915_modparams.enable_psr == -1)
+                i915_modparams.enable_psr = 0;
 
         /* Set link_standby x link_off defaults */
         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -963,15 +967,29 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
 
         /* Override link_standby x link_off defaults */
-        if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
+        if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) {
                 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
                 dev_priv->psr.link_standby = true;
         }
-        if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
+        if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) {
                 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
                 dev_priv->psr.link_standby = false;
         }
 
         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
         mutex_init(&dev_priv->psr.lock);
+
+        if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+                dev_priv->psr.enable_source = vlv_psr_enable_source;
+                dev_priv->psr.disable_source = vlv_psr_disable;
+                dev_priv->psr.enable_sink = vlv_psr_enable_sink;
+                dev_priv->psr.activate = vlv_psr_activate;
+                dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
+        } else {
+                dev_priv->psr.enable_source = hsw_psr_enable_source;
+                dev_priv->psr.disable_source = hsw_psr_disable;
+                dev_priv->psr.enable_sink = hsw_psr_enable_sink;
+                dev_priv->psr.activate = hsw_psr_activate;
+                dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
+        }
 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cdf084ef5aae..05c08b0bc172 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -402,17 +402,18 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
          */
         if (IS_GEN7(dev_priv)) {
                 switch (engine->id) {
+                /*
+                 * No more rings exist on Gen7. Default case is only to shut up
+                 * gcc switch check warning.
+                 */
+                default:
+                        GEM_BUG_ON(engine->id);
                 case RCS:
                         mmio = RENDER_HWS_PGA_GEN7;
                         break;
                 case BCS:
                         mmio = BLT_HWS_PGA_GEN7;
                         break;
-                /*
-                 * VCS2 actually doesn't exist on Gen7. Only shut up
-                 * gcc switch check warning
-                 */
-                case VCS2:
                 case VCS:
                         mmio = BSD_HWS_PGA_GEN7;
                         break;
@@ -427,6 +428,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
                 mmio = RING_HWS_PGA(engine->mmio_base);
         }
 
+        if (INTEL_GEN(dev_priv) >= 6)
+                I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
+
         I915_WRITE(mmio, engine->status_page.ggtt_offset);
         POSTING_READ(mmio);
 
@@ -778,6 +782,24 @@ static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs)
         return cs;
 }
 
+static void cancel_requests(struct intel_engine_cs *engine)
+{
+        struct drm_i915_gem_request *request;
+        unsigned long flags;
+
+        spin_lock_irqsave(&engine->timeline->lock, flags);
+
+        /* Mark all submitted requests as skipped. */
+        list_for_each_entry(request, &engine->timeline->requests, link) {
+                GEM_BUG_ON(!request->global_seqno);
+                if (!i915_gem_request_completed(request))
+                        dma_fence_set_error(&request->fence, -EIO);
+        }
+        /* Remaining _unready_ requests will be nop'ed when submitted */
+
+        spin_unlock_irqrestore(&engine->timeline->lock, flags);
+}
+
 static void i9xx_submit_request(struct drm_i915_gem_request *request)
 {
         struct drm_i915_private *dev_priv = request->i915;
@@ -1174,113 +1196,7 @@ i915_emit_bb_start(struct drm_i915_gem_request *req,
         return 0;
 }
 
-static void cleanup_phys_status_page(struct intel_engine_cs *engine)
-{
-        struct drm_i915_private *dev_priv = engine->i915;
-
-        if (!dev_priv->status_page_dmah)
-                return;
-
-        drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
-        engine->status_page.page_addr = NULL;
-}
-
-static void cleanup_status_page(struct intel_engine_cs *engine)
-{
-        struct i915_vma *vma;
-        struct drm_i915_gem_object *obj;
-
-        vma = fetch_and_zero(&engine->status_page.vma);
-        if (!vma)
-                return;
-
-        obj = vma->obj;
-
-        i915_vma_unpin(vma);
-        i915_vma_close(vma);
-
-        i915_gem_object_unpin_map(obj);
-        __i915_gem_object_release_unless_active(obj);
-}
-
-static int init_status_page(struct intel_engine_cs *engine)
-{
-        struct drm_i915_gem_object *obj;
-        struct i915_vma *vma;
-        unsigned int flags;
-        void *vaddr;
-        int ret;
-
-        obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
-        if (IS_ERR(obj)) {
-                DRM_ERROR("Failed to allocate status page\n");
-                return PTR_ERR(obj);
-        }
 
-        ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
-        if (ret)
-                goto err;
-
-        vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
-        if (IS_ERR(vma)) {
-                ret = PTR_ERR(vma);
-                goto err;
-        }
-
-        flags = PIN_GLOBAL;
-        if (!HAS_LLC(engine->i915))
-                /* On g33, we cannot place HWS above 256MiB, so
-                 * restrict its pinning to the low mappable arena.
-                 * Though this restriction is not documented for
-                 * gen4, gen5, or byt, they also behave similarly
-                 * and hang if the HWS is placed at the top of the
-                 * GTT. To generalise, it appears that all !llc
-                 * platforms have issues with us placing the HWS
-                 * above the mappable region (even though we never
-                 * actualy map it).
-                 */
-                flags |= PIN_MAPPABLE;
-        ret = i915_vma_pin(vma, 0, 4096, flags);
-        if (ret)
-                goto err;
-
-        vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
-        if (IS_ERR(vaddr)) {
-                ret = PTR_ERR(vaddr);
-                goto err_unpin;
-        }
-
-        engine->status_page.vma = vma;
-        engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
-        engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
-
-        DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
-                         engine->name, i915_ggtt_offset(vma));
-        return 0;
-
-err_unpin:
-        i915_vma_unpin(vma);
-err:
-        i915_gem_object_put(obj);
-        return ret;
-}
-
-static int init_phys_status_page(struct intel_engine_cs *engine)
-{
-        struct drm_i915_private *dev_priv = engine->i915;
-
-        GEM_BUG_ON(engine->id != RCS);
-
-        dev_priv->status_page_dmah =
-                drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
-        if (!dev_priv->status_page_dmah)
-                return -ENOMEM;
-
-        engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
-        memset(engine->status_page.page_addr, 0, PAGE_SIZE);
-
-        return 0;
-}
 
 int intel_ring_pin(struct intel_ring *ring,
                    struct drm_i915_private *i915,
@@ -1567,17 +1483,10 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
         if (err)
                 goto err;
 
-        if (HWS_NEEDS_PHYSICAL(engine->i915))
-                err = init_phys_status_page(engine);
-        else
-                err = init_status_page(engine);
-        if (err)
-                goto err;
-
         ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
         if (IS_ERR(ring)) {
                 err = PTR_ERR(ring);
-                goto err_hws;
+                goto err;
         }
 
         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
@@ -1592,11 +1501,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 
 err_ring:
         intel_ring_free(ring);
-err_hws:
-        if (HWS_NEEDS_PHYSICAL(engine->i915))
-                cleanup_phys_status_page(engine);
-        else
-                cleanup_status_page(engine);
 err:
         intel_engine_cleanup_common(engine);
         return err;
@@ -1615,11 +1519,6 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
         if (engine->cleanup)
                 engine->cleanup(engine);
 
-        if (HWS_NEEDS_PHYSICAL(dev_priv))
-                cleanup_phys_status_page(engine);
-        else
-                cleanup_status_page(engine);
-
         intel_engine_cleanup_common(engine);
 
         dev_priv->engine[engine->id] = NULL;
@@ -1983,7 +1882,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
         struct drm_i915_gem_object *obj;
         int ret, i;
 
-        if (!i915.semaphores)
+        if (!i915_modparams.semaphores)
                 return;
 
         if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
@@ -2083,7 +1982,7 @@ err_obj:
         i915_gem_object_put(obj);
 err:
         DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
-        i915.semaphores = 0;
+        i915_modparams.semaphores = 0;
 }
 
 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
@@ -2115,11 +2014,13 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
 {
         engine->submit_request = i9xx_submit_request;
+        engine->cancel_requests = cancel_requests;
 }
 
 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
 {
         engine->submit_request = gen6_bsd_submit_request;
+        engine->cancel_requests = cancel_requests;
 }
 
 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
@@ -2138,7 +2039,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 
         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
-        if (i915.semaphores) {
+        if (i915_modparams.semaphores) {
                 int num_rings;
 
                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
@@ -2182,7 +2083,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
                 engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
                 engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
                 engine->emit_flush = gen8_render_ring_flush;
-                if (i915.semaphores) {
+                if (i915_modparams.semaphores) {
                         int num_rings;
 
                         engine->semaphore.signal = gen8_rcs_signal;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 79c0021f3700..56d7ae9f298b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -184,6 +184,91 @@ struct i915_priolist {
         int priority;
 };
 
+/**
+ * struct intel_engine_execlists - execlist submission queue and port state
+ *
+ * The struct intel_engine_execlists represents the combined logical state of
+ * driver and the hardware state for execlist mode of submission.
+ */
+struct intel_engine_execlists {
+        /**
+         * @irq_tasklet: softirq tasklet for bottom handler
+         */
+        struct tasklet_struct irq_tasklet;
+
+        /**
+         * @default_priolist: priority list for I915_PRIORITY_NORMAL
+         */
+        struct i915_priolist default_priolist;
+
+        /**
+         * @no_priolist: priority lists disabled
+         */
+        bool no_priolist;
+
+        /**
+         * @port: execlist port states
+         *
+         * For each hardware ELSP (ExecList Submission Port) we keep
+         * track of the last request and the number of times we submitted
+         * that port to hw. We then count the number of times the hw reports
+         * a context completion or preemption. As only one context can
+         * be active on hw, we limit resubmission of context to port[0]. This
+         * is called Lite Restore, of the context.
+         */
+        struct execlist_port {
+                /**
+                 * @request_count: combined request and submission count
+                 */
+                struct drm_i915_gem_request *request_count;
+#define EXECLIST_COUNT_BITS 2
+#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
+#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
+#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
+#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
+#define port_set(p, packed) ((p)->request_count = (packed))
+#define port_isset(p) ((p)->request_count)
+#define port_index(p, execlists) ((p) - (execlists)->port)
+
+                /**
+                 * @context_id: context ID for port
+                 */
+                GEM_DEBUG_DECL(u32 context_id);
+
+#define EXECLIST_MAX_PORTS 2
+        } port[EXECLIST_MAX_PORTS];
+
+        /**
+         * @port_mask: number of execlist ports - 1
+         */
+        unsigned int port_mask;
+
+        /**
+         * @queue: queue of requests, in priority lists
+         */
+        struct rb_root queue;
+
+        /**
+         * @first: leftmost level in priority @queue
+         */
+        struct rb_node *first;
+
+        /**
+         * @fw_domains: forcewake domains for irq tasklet
+         */
+        unsigned int fw_domains;
+
+        /**
+         * @csb_head: context status buffer head
+         */
+        unsigned int csb_head;
+
+        /**
+         * @csb_use_mmio: access csb through mmio, instead of hwsp
+         */
+        bool csb_use_mmio;
+};
+
 #define INTEL_ENGINE_CS_MAX_NAME 8
 
 struct intel_engine_cs {
@@ -306,6 +391,14 @@ struct intel_engine_cs {
         void            (*schedule)(struct drm_i915_gem_request *request,
                                     int priority);
 
+        /*
+         * Cancel all requests on the hardware, or queued for execution.
+         * This should only cancel the ready requests that have been
+         * submitted to the engine (via the engine->submit_request callback).
+         * This is called when marking the device as wedged.
+         */
+        void            (*cancel_requests)(struct intel_engine_cs *engine);
+
         /* Some chipsets are not quite as coherent as advertised and need
          * an expensive kick to force a true read of the up-to-date seqno.
          * However, the up-to-date seqno is not always required and the last
@@ -372,25 +465,7 @@ struct intel_engine_cs {
                 u32     *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
         } semaphore;
 
-        /* Execlists */
-        struct tasklet_struct irq_tasklet;
-        struct i915_priolist default_priolist;
-        bool no_priolist;
-        struct execlist_port {
-                struct drm_i915_gem_request *request_count;
-#define EXECLIST_COUNT_BITS 2
-#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
-#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
-#define port_set(p, packed) ((p)->request_count = (packed))
-#define port_isset(p) ((p)->request_count)
-#define port_index(p, e) ((p) - (e)->execlist_port)
-                GEM_DEBUG_DECL(u32 context_id);
-        } execlist_port[2];
-        struct rb_root execlist_queue;
-        struct rb_node *execlist_first;
-        unsigned int fw_domains;
+        struct intel_engine_execlists execlists;
 
         /* Contexts are pinned whilst they are active on the GPU. The last
          * context executed remains active whilst the GPU is idle - the
@@ -444,6 +519,24 @@ struct intel_engine_cs {
 };
 
 static inline unsigned int
+execlists_num_ports(const struct intel_engine_execlists * const execlists)
+{
+        return execlists->port_mask + 1;
+}
+
+static inline void
+execlists_port_complete(struct intel_engine_execlists * const execlists,
+                        struct execlist_port * const port)
+{
+        const unsigned int m = execlists->port_mask;
+
+        GEM_BUG_ON(port_index(port, execlists) != 0);
+
+        memmove(port, port + 1, m * sizeof(struct execlist_port));
+        memset(port + m, 0, sizeof(struct execlist_port));
+}
+
+static inline unsigned int
 intel_engine_flag(const struct intel_engine_cs *engine)
 {
         return BIT(engine->id);
@@ -496,6 +589,10 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 #define I915_GEM_HWS_SCRATCH_INDEX      0x40
 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
+#define I915_HWS_CSB_BUF0_INDEX         0x10
+#define I915_HWS_CSB_WRITE_INDEX        0x1f
+#define CNL_HWS_CSB_WRITE_INDEX         0x2f
+
 struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
 int intel_ring_pin(struct intel_ring *ring,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a3bfb9f27e7a..7933d1bc6a1c 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2413,7 +2413,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
                 mask = 0;
         }
 
-        if (!i915.disable_power_well)
+        if (!i915_modparams.disable_power_well)
                 max_dc = 0;
 
         if (enable_dc >= 0 && enable_dc <= max_dc) {
@@ -2471,10 +2471,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 {
         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 
-        i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
-                                                     i915.disable_power_well);
-        dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
-                                                            i915.enable_dc);
+        i915_modparams.disable_power_well =
+                sanitize_disable_power_well_option(dev_priv,
+                                                   i915_modparams.disable_power_well);
+        dev_priv->csr.allowed_dc_mask =
+                get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
 
         BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
 
@@ -2535,7 +2536,7 @@ void intel_power_domains_fini(struct drm_i915_private *dev_priv)
         intel_display_set_init_power(dev_priv, true);
 
         /* Remove the refcount we took to keep power well support disabled. */
-        if (!i915.disable_power_well)
+        if (!i915_modparams.disable_power_well)
                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
         /*
@@ -2995,7 +2996,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
         /* For now, we need the power well to be always enabled. */
         intel_display_set_init_power(dev_priv, true);
         /* Disable power support if the user asked so. */
-        if (!i915.disable_power_well)
+        if (!i915_modparams.disable_power_well)
                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
         intel_power_domains_sync_hw(dev_priv);
         power_domains->initializing = false;
@@ -3014,7 +3015,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
          * Even if power well support was disabled we still want to disable
          * power wells while we are system suspended.
          */
-        if (!i915.disable_power_well)
+        if (!i915_modparams.disable_power_well)
                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
         if (IS_CANNONLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index b0d6e3e28d07..28a1209d87e2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -994,7 +994,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
             set->flags & I915_SET_COLORKEY_DESTINATION)
                 return -EINVAL;
 
-        plane = drm_plane_find(dev, set->plane_id);
+        plane = drm_plane_find(dev, file_priv, set->plane_id);
         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
                 return -ENOENT;
 
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 0cc999fa09c5..a79a7591b2cf 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1385,7 +1385,7 @@ intel_tv_get_modes(struct drm_connector *connector)
                         mode_ptr->vsync_end = mode_ptr->vsync_start  + 1;
                 mode_ptr->vtotal = vactive_s + 33;
 
-                tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
+                tmp = mul_u32_u32(tv_mode->refresh, mode_ptr->vtotal);
                 tmp *= mode_ptr->htotal;
                 tmp = div_u64(tmp, 1000000);
                 mode_ptr->clock = (int) tmp;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba42a0e5..277477890240 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,35 +63,35 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
 {
         if (!HAS_GUC(dev_priv)) {
-                if (i915.enable_guc_loading > 0 ||
-                    i915.enable_guc_submission > 0)
+                if (i915_modparams.enable_guc_loading > 0 ||
+                    i915_modparams.enable_guc_submission > 0)
                         DRM_INFO("Ignoring GuC options, no hardware\n");
 
-                i915.enable_guc_loading = 0;
-                i915.enable_guc_submission = 0;
+                i915_modparams.enable_guc_loading = 0;
+                i915_modparams.enable_guc_submission = 0;
                 return;
         }
 
         /* A negative value means "use platform default" */
-        if (i915.enable_guc_loading < 0)
-                i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
+        if (i915_modparams.enable_guc_loading < 0)
+                i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
 
         /* Verify firmware version */
-        if (i915.enable_guc_loading) {
+        if (i915_modparams.enable_guc_loading) {
                 if (HAS_HUC_UCODE(dev_priv))
                         intel_huc_select_fw(&dev_priv->huc);
 
                 if (intel_guc_select_fw(&dev_priv->guc))
-                        i915.enable_guc_loading = 0;
+                        i915_modparams.enable_guc_loading = 0;
         }
 
         /* Can't enable guc submission without guc loaded */
-        if (!i915.enable_guc_loading)
-                i915.enable_guc_submission = 0;
+        if (!i915_modparams.enable_guc_loading)
+                i915_modparams.enable_guc_submission = 0;
 
         /* A negative value means "use platform default" */
-        if (i915.enable_guc_submission < 0)
-                i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
+        if (i915_modparams.enable_guc_submission < 0)
+                i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
 }
 
 static void gen8_guc_raise_irq(struct intel_guc *guc)
@@ -290,7 +290,7 @@ static void guc_init_send_regs(struct intel_guc *guc)
 
 static void guc_capture_load_err_log(struct intel_guc *guc)
 {
-        if (!guc->log.vma || i915.guc_log_level < 0)
+        if (!guc->log.vma || i915_modparams.guc_log_level < 0)
                 return;
 
         if (!guc->load_err_log)
@@ -328,12 +328,33 @@ static void guc_disable_communication(struct intel_guc *guc)
         guc->send = intel_guc_send_nop;
 }
 
+/**
+ * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
+ * @guc: intel_guc structure
+ * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
+ *
+ * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
+ * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
+ * intel_huc_auth().
+ *
+ * Return:      non-zero code on error
+ */
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
+{
+        u32 action[] = {
+                INTEL_GUC_ACTION_AUTHENTICATE_HUC,
+                rsa_offset
+        };
+
+        return intel_guc_send(guc, action, ARRAY_SIZE(action));
+}
+
 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 {
         struct intel_guc *guc = &dev_priv->guc;
         int ret, attempts;
 
-        if (!i915.enable_guc_loading)
+        if (!i915_modparams.enable_guc_loading)
                 return 0;
 
         guc_disable_communication(guc);
@@ -342,7 +363,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
         /* We need to notify the guc whenever we change the GGTT */
         i915_ggtt_enable_guc(dev_priv);
 
-        if (i915.enable_guc_submission) {
+        if (i915_modparams.enable_guc_submission) {
                 /*
                  * This is stuff we need to have available at fw load time
                  * if we are planning to enable submission later
@@ -390,9 +411,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
         if (ret)
                 goto err_log_capture;
 
-        intel_guc_auth_huc(dev_priv);
-        if (i915.enable_guc_submission) {
-                if (i915.guc_log_level >= 0)
+        intel_huc_auth(&dev_priv->huc);
+        if (i915_modparams.enable_guc_submission) {
+                if (i915_modparams.guc_log_level >= 0)
                         gen9_enable_guc_interrupts(dev_priv);
 
                 ret = i915_guc_submission_enable(dev_priv);
@@ -417,23 +438,24 @@ err_interrupts:
 err_log_capture:
         guc_capture_load_err_log(guc);
 err_submission:
-        if (i915.enable_guc_submission)
+        if (i915_modparams.enable_guc_submission)
                 i915_guc_submission_fini(dev_priv);
 err_guc:
         i915_ggtt_disable_guc(dev_priv);
 
         DRM_ERROR("GuC init failed\n");
-        if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1)
+        if (i915_modparams.enable_guc_loading > 1 ||
+            i915_modparams.enable_guc_submission > 1)
                 ret = -EIO;
         else
                 ret = 0;
 
-        if (i915.enable_guc_submission) {
-                i915.enable_guc_submission = 0;
+        if (i915_modparams.enable_guc_submission) {
+                i915_modparams.enable_guc_submission = 0;
                 DRM_NOTE("Falling back from GuC submission to execlist mode\n");
         }
 
-        i915.enable_guc_loading = 0;
+        i915_modparams.enable_guc_loading = 0;
         DRM_NOTE("GuC firmware loading disabled\n");
 
         return ret;
@@ -443,15 +465,15 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
         guc_free_load_err_log(&dev_priv->guc);
 
-        if (!i915.enable_guc_loading)
+        if (!i915_modparams.enable_guc_loading)
                 return;
 
-        if (i915.enable_guc_submission)
+        if (i915_modparams.enable_guc_submission)
                 i915_guc_submission_disable(dev_priv);
 
         guc_disable_communication(&dev_priv->guc);
 
-        if (i915.enable_guc_submission) {
+        if (i915_modparams.enable_guc_submission) {
                 gen9_disable_guc_interrupts(dev_priv);
                 i915_guc_submission_fini(dev_priv);
         }
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b17b0f..6966349ed737 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -52,17 +52,6 @@ struct drm_i915_gem_request;
  * GuC). The subsequent  pages of the client object constitute the work
  * queue (a circular array of work items), again described in the process
  * descriptor. Work queue pages are mapped momentarily as required.
- *
- * We also keep a few statistics on failures. Ideally, these should all
- * be zero!
- *   no_wq_space: times that the submission pre-check found no space was
- *                available in the work queue (note, the queue is shared,
- *                not per-engine). It is OK for this to be nonzero, but
- *                it should not be huge!
- *   b_fail: failed to ring the doorbell. This should never happen, unless
- *           somehow the hardware misbehaves, or maybe if the GuC firmware
- *           crashes? We probably need to reset the GPU to recover.
- *   retcode: errno from last guc_submit()
  */
 struct i915_guc_client {
         struct i915_vma *vma;
@@ -77,15 +66,8 @@ struct i915_guc_client {
 
         u16 doorbell_id;
         unsigned long doorbell_offset;
-        u32 doorbell_cookie;
 
         spinlock_t wq_lock;
-        uint32_t wq_offset;
-        uint32_t wq_size;
-        uint32_t wq_tail;
-        uint32_t wq_rsvd;
-        uint32_t no_wq_space;
-
         /* Per-engine counts of GuC submissions */
         uint64_t submissions[I915_NUM_ENGINES];
 };
@@ -229,6 +211,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 
 static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
 {
@@ -250,8 +233,6 @@ u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
-int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
@@ -274,6 +255,6 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 /* intel_huc.c */
 void intel_huc_select_fw(struct intel_huc *huc);
 void intel_huc_init_hw(struct intel_huc *huc);
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
+void intel_huc_auth(struct intel_huc *huc);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0529af7cfbb8..b3c3f94fc7e4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -436,7 +436,8 @@ void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
 
 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 {
-        i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
+        i915_modparams.enable_rc6 =
+                sanitize_rc6_option(dev_priv, i915_modparams.enable_rc6);
 
         /* BIOS often leaves RC6 enabled, but disable it for hw init */
         intel_sanitize_gt_powersave(dev_priv);
@@ -490,6 +491,57 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 }
 
 /**
+ * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
+ * @dev_priv: i915 device instance
+ *
+ * This function is a wrapper around intel_uncore_forcewake_get() to acquire
+ * the GT powerwell and in the process disable our debugging for the
+ * duration of userspace's bypass.
+ */
+void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
+{
+        spin_lock_irq(&dev_priv->uncore.lock);
+        if (!dev_priv->uncore.user_forcewake.count++) {
+                intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
+
+                /* Save and disable mmio debugging for the user bypass */
+                dev_priv->uncore.user_forcewake.saved_mmio_check =
+                        dev_priv->uncore.unclaimed_mmio_check;
+                dev_priv->uncore.user_forcewake.saved_mmio_debug =
+                        i915_modparams.mmio_debug;
+
+                dev_priv->uncore.unclaimed_mmio_check = 0;
+                i915_modparams.mmio_debug = 0;
+        }
+        spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
+/**
+ * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
+ * @dev_priv: i915 device instance
+ *
+ * This function complements intel_uncore_forcewake_user_get() and releases
+ * the GT powerwell taken on behalf of the userspace bypass.
+ */
+void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
+{
+        spin_lock_irq(&dev_priv->uncore.lock);
+        if (!--dev_priv->uncore.user_forcewake.count) {
+                if (intel_uncore_unclaimed_mmio(dev_priv))
+                        dev_info(dev_priv->drm.dev,
+                                 "Invalid mmio detected during user access\n");
+
+                dev_priv->uncore.unclaimed_mmio_check =
+                        dev_priv->uncore.user_forcewake.saved_mmio_check;
+                i915_modparams.mmio_debug =
+                        dev_priv->uncore.user_forcewake.saved_mmio_debug;
+
+                intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
+        }
+        spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
+/**
  * intel_uncore_forcewake_get__locked - grab forcewake domain references
  * @dev_priv: i915 device instance
  * @fw_domains: forcewake domains to get reference on
@@ -790,7 +842,8 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
                  "Unclaimed %s register 0x%x\n",
                  read ? "read from" : "write to",
                  i915_mmio_reg_offset(reg)))
-                i915.mmio_debug--; /* Only report the first N failures */
+                /* Only report the first N failures */
+                i915_modparams.mmio_debug--;
 }
 
 static inline void
@@ -799,7 +852,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
                     const bool read,
                     const bool before)
 {
-        if (likely(!i915.mmio_debug))
+        if (likely(!i915_modparams.mmio_debug))
                 return;
 
         __unclaimed_reg_debug(dev_priv, reg, read, before);
@@ -1241,102 +1294,101 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
         intel_uncore_forcewake_reset(dev_priv, false);
 }
 
-#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
-
-static const struct register_whitelist {
-        i915_reg_t offset_ldw, offset_udw;
-        uint32_t size;
-        /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
-        uint32_t gen_bitmask;
-} whitelist[] = {
-        { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
-          .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
-          .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
-};
+static const struct reg_whitelist {
+        i915_reg_t offset_ldw;
+        i915_reg_t offset_udw;
+        u16 gen_mask;
+        u8 size;
+} reg_read_whitelist[] = { {
+        .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+        .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
+        .gen_mask = INTEL_GEN_MASK(4, 10),
+        .size = 8
+} };
 
 int i915_reg_read_ioctl(struct drm_device *dev,
                         void *data, struct drm_file *file)
 {
         struct drm_i915_private *dev_priv = to_i915(dev);
         struct drm_i915_reg_read *reg = data;
-        struct register_whitelist const *entry = whitelist;
-        unsigned size;
-        i915_reg_t offset_ldw, offset_udw;
-        int i, ret = 0;
-
-        for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-                if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
-                    (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
+        struct reg_whitelist const *entry;
+        unsigned int flags;
+        int remain;
+        int ret = 0;
+
+        entry = reg_read_whitelist;
+        remain = ARRAY_SIZE(reg_read_whitelist);
+        while (remain) {
+                u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+
+                GEM_BUG_ON(!is_power_of_2(entry->size));
+                GEM_BUG_ON(entry->size > 8);
+                GEM_BUG_ON(entry_offset & (entry->size - 1));
+
+                if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
+                    entry_offset == (reg->offset & -entry->size))
                         break;
+                entry++;
+                remain--;
         }
 
-        if (i == ARRAY_SIZE(whitelist))
+        if (!remain)
                 return -EINVAL;
 
-        /* We use the low bits to encode extra flags as the register should
-         * be naturally aligned (and those that are not so aligned merely
-         * limit the available flags for that register).
-         */
-        offset_ldw = entry->offset_ldw;
-        offset_udw = entry->offset_udw;
-        size = entry->size;
-        size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
+        flags = reg->offset & (entry->size - 1);
 
         intel_runtime_pm_get(dev_priv);
-
-        switch (size) {
-        case 8 | 1:
-                reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
-                break;
-        case 8:
-                reg->val = I915_READ64(offset_ldw);
-                break;
-        case 4:
-                reg->val = I915_READ(offset_ldw);
-                break;
-        case 2:
-                reg->val = I915_READ16(offset_ldw);
-                break;
-        case 1:
-                reg->val = I915_READ8(offset_ldw);
-                break;
-        default:
+        if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
+                reg->val = I915_READ64_2x32(entry->offset_ldw,
+                                            entry->offset_udw);
+        else if (entry->size == 8 && flags == 0)
+                reg->val = I915_READ64(entry->offset_ldw);
+        else if (entry->size == 4 && flags == 0)
+                reg->val = I915_READ(entry->offset_ldw);
+        else if (entry->size == 2 && flags == 0)
+                reg->val = I915_READ16(entry->offset_ldw);
+        else if (entry->size == 1 && flags == 0)
+                reg->val = I915_READ8(entry->offset_ldw);
+        else
                 ret = -EINVAL;
-                goto out;
-        }
-
-out:
         intel_runtime_pm_put(dev_priv);
+
         return ret;
 }
 
-static void gen3_stop_rings(struct drm_i915_private *dev_priv)
+static void gen3_stop_engine(struct intel_engine_cs *engine)
+{
+        struct drm_i915_private *dev_priv = engine->i915;
+        const u32 base = engine->mmio_base;
+        const i915_reg_t mode = RING_MI_MODE(base);
+
+        I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
+        if (intel_wait_for_register_fw(dev_priv,
+                                       mode,
+                                       MODE_IDLE,
+                                       MODE_IDLE,
+                                       500))
+                DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
+                                 engine->name);
+
+        I915_WRITE_FW(RING_CTL(base), 0);
+        I915_WRITE_FW(RING_HEAD(base), 0);
+        I915_WRITE_FW(RING_TAIL(base), 0);
+
+        /* Check acts as a post */
+        if (I915_READ_FW(RING_HEAD(base)) != 0)
+                DRM_DEBUG_DRIVER("%s: ring head not parked\n",
+                                 engine->name);
+}
+
+static void i915_stop_engines(struct drm_i915_private *dev_priv,
+                              unsigned engine_mask)
 {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
 
-        for_each_engine(engine, dev_priv, id) {
-                const u32 base = engine->mmio_base;
-                const i915_reg_t mode = RING_MI_MODE(base);
-
-                I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
-                if (intel_wait_for_register_fw(dev_priv,
-                                               mode,
-                                               MODE_IDLE,
-                                               MODE_IDLE,
-                                               500))
-                        DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
-                                         engine->name);
-
-                I915_WRITE_FW(RING_CTL(base), 0);
-                I915_WRITE_FW(RING_HEAD(base), 0);
-                I915_WRITE_FW(RING_TAIL(base), 0);
-
-                /* Check acts as a post */
-                if (I915_READ_FW(RING_HEAD(base)) != 0)
-                        DRM_DEBUG_DRIVER("%s: ring head not parked\n",
-                                         engine->name);
-        }
+        for_each_engine_masked(engine, dev_priv, engine_mask, id)
+                gen3_stop_engine(engine);
 }
 
 static bool i915_reset_complete(struct pci_dev *pdev)
@@ -1371,9 +1423,6 @@ static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
 {
         struct pci_dev *pdev = dev_priv->drm.pdev;
 
-        /* Stop engines before we reset; see g4x_do_reset() below for why. */
-        gen3_stop_rings(dev_priv);
-
         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
         return wait_for(g4x_reset_complete(pdev), 500);
 }
@@ -1388,12 +1437,6 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
                    I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
         POSTING_READ(VDECCLK_GATE_D);
 
-        /* We stop engines, otherwise we might get failed reset and a
-         * dead gpu (on elk).
-         * WaMediaResetMainRingCleanup:ctg,elk (presumably)
-         */
-        gen3_stop_rings(dev_priv);
-
         pci_write_config_byte(pdev, I915_GDRST,
                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
         ret =  wait_for(g4x_reset_complete(pdev), 500);
@@ -1662,7 +1705,7 @@ typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
 
 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 {
-        if (!i915.reset)
+        if (!i915_modparams.reset)
                 return NULL;
 
         if (INTEL_INFO(dev_priv)->gen >= 8)
@@ -1698,6 +1741,20 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
          */
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
         for (retry = 0; retry < 3; retry++) {
+
+                /* We stop engines, otherwise we might get failed reset and a
+                 * dead gpu (on elk). Also as modern gpu as kbl can suffer
+                 * from system hang if batchbuffer is progressing when
+                 * the reset is issued, regardless of READY_TO_RESET ack.
+                 * Thus assume it is best to stop engines on all gens
+                 * where we have a gpu reset.
+                 *
+                 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
+                 *
+                 * FIXME: Wa for more modern gens needs to be validated
+                 */
+                i915_stop_engines(dev_priv, engine_mask);
+
                 ret = reset(dev_priv, engine_mask);
                 if (ret != -ETIMEDOUT)
                         break;
@@ -1722,7 +1779,7 @@ bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
 {
         return (dev_priv->info.has_reset_engine &&
                 !dev_priv->guc.execbuf_client &&
-                i915.reset >= 2);
+                i915_modparams.reset >= 2);
 }
 
 int intel_guc_reset(struct drm_i915_private *dev_priv)
@@ -1747,7 +1804,7 @@ bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
 bool
 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
 {
-        if (unlikely(i915.mmio_debug ||
+        if (unlikely(i915_modparams.mmio_debug ||
                      dev_priv->uncore.unclaimed_mmio_check <= 0))
                 return false;
 
@@ -1755,7 +1812,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
                 DRM_DEBUG("Unclaimed register detected, "
                           "enabling oneshot unclaimed register reporting. "
                           "Please use i915.mmio_debug=N for more information.\n");
-                i915.mmio_debug++;
+                i915_modparams.mmio_debug++;
                 dev_priv->uncore.unclaimed_mmio_check--;
                 return true;
         }
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 5f90278da461..03786f931905 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -102,6 +102,13 @@ struct intel_uncore {
                 i915_reg_t reg_ack;
         } fw_domain[FW_DOMAIN_ID_COUNT];
 
+        struct {
+                unsigned int count;
+
+                int saved_mmio_check;
+                int saved_mmio_debug;
+        } user_forcewake;
+
         int unclaimed_mmio_check;
 };
 
@@ -144,6 +151,9 @@ void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
                                         enum forcewake_domains domains);
 
+void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
+void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
+
 int intel_wait_for_register(struct drm_i915_private *dev_priv,
                             i915_reg_t reg,
                             u32 mask,
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c b/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c
index 7a44dab631b8..4795877abe56 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c
@@ -121,7 +121,7 @@ out:
 
 static unsigned int random_engine(struct rnd_state *rnd)
 {
-        return ((u64)prandom_u32_state(rnd) * I915_NUM_ENGINES) >> 32;
+        return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
 }
 
 static int bench_sync(void *arg)
diff --git a/drivers/gpu/drm/i915/selftests/i915_random.c b/drivers/gpu/drm/i915/selftests/i915_random.c
index 222c511bea49..b85872cc7fbe 100644
--- a/drivers/gpu/drm/i915/selftests/i915_random.c
+++ b/drivers/gpu/drm/i915/selftests/i915_random.c
@@ -41,11 +41,6 @@ u64 i915_prandom_u64_state(struct rnd_state *rnd)
         return x;
 }
 
-static inline u32 i915_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
-{
-        return upper_32_bits((u64)prandom_u32_state(state) * ep_ro);
-}
-
 void i915_random_reorder(unsigned int *order, unsigned int count,
                          struct rnd_state *state)
 {
diff --git a/drivers/gpu/drm/i915/selftests/i915_random.h b/drivers/gpu/drm/i915/selftests/i915_random.h
index 6c9379871384..7dffedc501ca 100644
--- a/drivers/gpu/drm/i915/selftests/i915_random.h
+++ b/drivers/gpu/drm/i915/selftests/i915_random.h
@@ -43,6 +43,11 @@
 
 u64 i915_prandom_u64_state(struct rnd_state *rnd);
 
+static inline u32 i915_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
+{
+        return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));
+}
+
 unsigned int *i915_random_order(unsigned int count,
                                 struct rnd_state *state);
 void i915_random_reorder(unsigned int *order,
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 02e52a146ed8..377c1de766ce 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -621,7 +621,12 @@ static int igt_wait_reset(void *arg)
         __i915_add_request(rq, true);
 
         if (!wait_for_hang(&h, rq)) {
-                pr_err("Failed to start request %x\n", rq->fence.seqno);
+                pr_err("Failed to start request %x, at %x\n",
+                       rq->fence.seqno, hws_seqno(&h, rq));
+
+                i915_reset(i915, 0);
+                i915_gem_set_wedged(i915);
+
                 err = -EIO;
                 goto out_rq;
         }
@@ -708,10 +713,14 @@ static int igt_reset_queue(void *arg)
                         __i915_add_request(rq, true);
 
                         if (!wait_for_hang(&h, prev)) {
-                                pr_err("Failed to start request %x\n",
-                                       prev->fence.seqno);
+                                pr_err("Failed to start request %x, at %x\n",
+                                       prev->fence.seqno, hws_seqno(&h, prev));
                                 i915_gem_request_put(rq);
                                 i915_gem_request_put(prev);
+
+                                i915_reset(i915, 0);
+                                i915_gem_set_wedged(i915);
+
                                 err = -EIO;
                                 goto fini;
                         }
@@ -806,7 +815,12 @@ static int igt_handle_error(void *arg)
         __i915_add_request(rq, true);
 
         if (!wait_for_hang(&h, rq)) {
-                pr_err("Failed to start request %x\n", rq->fence.seqno);
+                pr_err("Failed to start request %x, at %x\n",
+                       rq->fence.seqno, hws_seqno(&h, rq));
+
+                i915_reset(i915, 0);
+                i915_gem_set_wedged(i915);
+
                 err = -EIO;
                 goto err_request;
         }
@@ -843,8 +857,8 @@ err_unlock:
 int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
 {
         static const struct i915_subtest tests[] = {
+                SUBTEST(igt_global_reset), /* attempt to recover GPU first */
                 SUBTEST(igt_hang_sanitycheck),
-                SUBTEST(igt_global_reset),
                 SUBTEST(igt_reset_engine),
                 SUBTEST(igt_reset_active_engines),
                 SUBTEST(igt_wait_reset),
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 678723430d78..2388424a14da 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -146,6 +146,11 @@ struct drm_i915_private *mock_gem_device(void)
         dev_set_name(&pdev->dev, "mock");
         dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 
+#if IS_ENABLED(CONFIG_IOMMU_API)
+        /* hack to disable iommu for the fake device; force identity mapping */
+        pdev->dev.archdata.iommu = (void *)-1;
+#endif
+
         dev_pm_domain_set(&pdev->dev, &pm_domain);
         pm_runtime_enable(&pdev->dev);
         pm_runtime_dont_use_autosuspend(&pdev->dev);
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 5e9cd4c0e8b6..68e5d9c94475 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1670,7 +1670,7 @@ static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
         int enc_id = connector->encoder_ids[0];
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index f7c0698fec40..7e829a8d1cb1 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -599,7 +599,7 @@ static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
         struct drm_crtc *crtc;
         struct drm_encoder *encoder;
 
-        if (pipe < 0 || pipe >= priv->num_crtcs)
+        if (pipe >= priv->num_crtcs)
                 return 0;
 
         crtc = priv->crtcs[pipe];
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 70d8e0d69ad5..69d6e61a01ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -373,7 +373,7 @@ find_encoder(struct drm_connector *connector, int type)
                 if (!id)
                         break;
 
-                enc = drm_encoder_find(dev, id);
+                enc = drm_encoder_find(dev, NULL, id);
                 if (!enc)
                         continue;
                 nv_encoder = nouveau_encoder(enc);
@@ -441,7 +441,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector)
                 if (id == 0)
                         break;
 
-                encoder = drm_encoder_find(dev, id);
+                encoder = drm_encoder_find(dev, NULL, id);
                 if (!encoder)
                         continue;
                 nv_encoder = nouveau_encoder(encoder);
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
index d9d25df6fc1b..4600d3841c25 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
@@ -165,11 +165,15 @@ static bool hdmic_detect(struct omap_dss_device *dssdev)
 {
         struct panel_drv_data *ddata = to_panel_data(dssdev);
         struct omap_dss_device *in = ddata->in;
+        bool connected;
 
         if (gpio_is_valid(ddata->hpd_gpio))
-                return gpio_get_value_cansleep(ddata->hpd_gpio);
+                connected = gpio_get_value_cansleep(ddata->hpd_gpio);
         else
-                return in->ops.hdmi->detect(in);
+                connected = in->ops.hdmi->detect(in);
+        if (!connected && in->ops.hdmi->lost_hotplug)
+                in->ops.hdmi->lost_hotplug(in);
+        return connected;
 }
 
 static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev,
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
index a9e9d667c55e..e3d98d78fc40 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
@@ -51,6 +51,8 @@ static int tpd_connect(struct omap_dss_device *dssdev,
         dssdev->dst = dst;
 
         gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
+        gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
+
         /* DC-DC converter needs at max 300us to get to 90% of 5V */
         udelay(300);
 
@@ -69,6 +71,7 @@ static void tpd_disconnect(struct omap_dss_device *dssdev,
                 return;
 
         gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
+        gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
 
         dst->src = NULL;
         dssdev->dst = NULL;
@@ -146,25 +149,22 @@ static int tpd_read_edid(struct omap_dss_device *dssdev,
 {
         struct panel_drv_data *ddata = to_panel_data(dssdev);
         struct omap_dss_device *in = ddata->in;
-        int r;
 
         if (!gpiod_get_value_cansleep(ddata->hpd_gpio))
                 return -ENODEV;
 
-        gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
-
-        r = in->ops.hdmi->read_edid(in, edid, len);
-
-        gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
-
-        return r;
+        return in->ops.hdmi->read_edid(in, edid, len);
 }
 
 static bool tpd_detect(struct omap_dss_device *dssdev)
 {
         struct panel_drv_data *ddata = to_panel_data(dssdev);
+        struct omap_dss_device *in = ddata->in;
+        bool connected = gpiod_get_value_cansleep(ddata->hpd_gpio);
 
-        return gpiod_get_value_cansleep(ddata->hpd_gpio);
+        if (!connected && in->ops.hdmi->lost_hotplug)
+                in->ops.hdmi->lost_hotplug(in);
+        return connected;
 }
 
 static int tpd_register_hpd_cb(struct omap_dss_device *dssdev,
diff --git a/drivers/gpu/drm/omapdrm/dss/Kconfig b/drivers/gpu/drm/omapdrm/dss/Kconfig
index 8b87d5cf45fc..f24ebf7f61dd 100644
--- a/drivers/gpu/drm/omapdrm/dss/Kconfig
+++ b/drivers/gpu/drm/omapdrm/dss/Kconfig
@@ -65,6 +65,14 @@ config OMAP4_DSS_HDMI
         help
           HDMI support for OMAP4 based SoCs.
 
+config OMAP4_DSS_HDMI_CEC
+        bool "Enable HDMI CEC support for OMAP4"
+        depends on OMAP4_DSS_HDMI
+        select CEC_CORE
+        default y
+        ---help---
+          When selected the HDMI transmitter will support the CEC feature.
+
 config OMAP5_DSS_HDMI
         bool "HDMI support for OMAP5"
         default n
diff --git a/drivers/gpu/drm/omapdrm/dss/Makefile b/drivers/gpu/drm/omapdrm/dss/Makefile
index 142ce5a02542..3c5644c3fc38 100644
--- a/drivers/gpu/drm/omapdrm/dss/Makefile
+++ b/drivers/gpu/drm/omapdrm/dss/Makefile
@@ -14,5 +14,6 @@ omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
 omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
         hdmi_phy.o
 omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
+omapdss-$(CONFIG_OMAP4_DSS_HDMI_CEC) += hdmi4_cec.o
 omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
 ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi.h b/drivers/gpu/drm/omapdrm/dss/hdmi.h
index a820b394af09..c2609c448ddc 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi.h
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <linux/hdmi.h>
 #include <sound/omap-hdmi-audio.h>
+#include <media/cec.h>
 
 #include "omapdss.h"
 #include "dss.h"
@@ -264,6 +265,10 @@ struct hdmi_core_data {
         void __iomem *base;
         bool cts_swmode;
         bool audio_use_mclk;
+
+        struct hdmi_wp_data *wp;
+        unsigned int core_pwr_cnt;
+        struct cec_adapter *adap;
 };
 
 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
@@ -373,7 +378,7 @@ struct omap_hdmi {
         bool audio_configured;
         struct omap_dss_audio audio_config;
 
-        /* This lock should be taken when booleans bellow are touched. */
+        /* This lock should be taken when booleans below are touched. */
         spinlock_t audio_playing_lock;
         bool audio_playing;
         bool display_enabled;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index f169348da377..a598dfdeb585 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -36,9 +36,11 @@
 #include <linux/of.h>
 #include <linux/of_graph.h>
 #include <sound/omap-hdmi-audio.h>
+#include <media/cec.h>
 
 #include "omapdss.h"
 #include "hdmi4_core.h"
+#include "hdmi4_cec.h"
 #include "dss.h"
 #include "hdmi.h"
 
@@ -70,7 +72,8 @@ static void hdmi_runtime_put(void)
 
 static irqreturn_t hdmi_irq_handler(int irq, void *data)
 {
-        struct hdmi_wp_data *wp = data;
+        struct omap_hdmi *hdmi = data;
+        struct hdmi_wp_data *wp = &hdmi->wp;
         u32 irqstatus;
 
         irqstatus = hdmi_wp_get_irqstatus(wp);
@@ -95,6 +98,13 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
         } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
         }
+        if (irqstatus & HDMI_IRQ_CORE) {
+                u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4);
+
+                hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4);
+                if (intr4 & 8)
+                        hdmi4_cec_irq(&hdmi->core);
+        }
 
         return IRQ_HANDLED;
 }
@@ -123,14 +133,19 @@ static int hdmi_power_on_core(struct omap_dss_device *dssdev)
 {
         int r;
 
+        if (hdmi.core.core_pwr_cnt++)
+                return 0;
+
         r = regulator_enable(hdmi.vdda_reg);
         if (r)
-                return r;
+                goto err_reg_enable;
 
         r = hdmi_runtime_get();
         if (r)
                 goto err_runtime_get;
 
+        hdmi4_core_powerdown_disable(&hdmi.core);
+
         /* Make selection of HDMI in DSS */
         dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
 
@@ -140,12 +155,17 @@ static int hdmi_power_on_core(struct omap_dss_device *dssdev)
 
 err_runtime_get:
         regulator_disable(hdmi.vdda_reg);
+err_reg_enable:
+        hdmi.core.core_pwr_cnt--;
 
         return r;
 }
 
 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
 {
+        if (--hdmi.core.core_pwr_cnt)
+                return;
+
         hdmi.core_enabled = false;
 
         hdmi_runtime_put();
@@ -166,8 +186,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
                 return r;
 
         /* disable and clear irqs */
-        hdmi_wp_clear_irqenable(wp, 0xffffffff);
-        hdmi_wp_set_irqstatus(wp, 0xffffffff);
+        hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);
+        hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);
 
         vm = &hdmi.cfg.vm;
 
@@ -242,7 +262,7 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
 {
         enum omap_channel channel = dssdev->dispc_channel;
 
-        hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
+        hdmi_wp_clear_irqenable(&hdmi.wp, ~HDMI_IRQ_CORE);
 
         hdmi_wp_video_stop(&hdmi.wp);
 
@@ -393,11 +413,11 @@ static void hdmi_display_disable(struct omap_dss_device *dssdev)
         mutex_unlock(&hdmi.lock);
 }
 
-static int hdmi_core_enable(struct omap_dss_device *dssdev)
+int hdmi4_core_enable(struct omap_dss_device *dssdev)
 {
         int r = 0;
 
-        DSSDBG("ENTER omapdss_hdmi_core_enable\n");
+        DSSDBG("ENTER omapdss_hdmi4_core_enable\n");
 
         mutex_lock(&hdmi.lock);
 
@@ -415,9 +435,9 @@ err0:
         return r;
 }
 
-static void hdmi_core_disable(struct omap_dss_device *dssdev)
+void hdmi4_core_disable(struct omap_dss_device *dssdev)
 {
-        DSSDBG("Enter omapdss_hdmi_core_disable\n");
+        DSSDBG("Enter omapdss_hdmi4_core_disable\n");
 
         mutex_lock(&hdmi.lock);
 
@@ -475,19 +495,28 @@ static int hdmi_read_edid(struct omap_dss_device *dssdev,
         need_enable = hdmi.core_enabled == false;
 
         if (need_enable) {
-                r = hdmi_core_enable(dssdev);
+                r = hdmi4_core_enable(dssdev);
                 if (r)
                         return r;
         }
 
         r = read_edid(edid, len);
-
+        if (r >= 256)
+                hdmi4_cec_set_phys_addr(&hdmi.core,
+                                        cec_get_edid_phys_addr(edid, r, NULL));
+        else
+                hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
         if (need_enable)
-                hdmi_core_disable(dssdev);
+                hdmi4_core_disable(dssdev);
 
         return r;
 }
 
+static void hdmi_lost_hotplug(struct omap_dss_device *dssdev)
+{
+        hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
+}
+
 static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
                 const struct hdmi_avi_infoframe *avi)
 {
@@ -514,6 +543,7 @@ static const struct omapdss_hdmi_ops hdmi_ops = {
         .get_timings            = hdmi_display_get_timings,
 
         .read_edid              = hdmi_read_edid,
+        .lost_hotplug           = hdmi_lost_hotplug,
         .set_infoframe          = hdmi_set_infoframe,
         .set_hdmi_mode          = hdmi_set_hdmi_mode,
 };
@@ -715,6 +745,10 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data)
         if (r)
                 goto err;
 
+        r = hdmi4_cec_init(pdev, &hdmi.core, &hdmi.wp);
+        if (r)
+                goto err;
+
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
                 DSSERR("platform_get_irq failed\n");
@@ -724,7 +758,7 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data)
 
         r = devm_request_threaded_irq(&pdev->dev, irq,
                         NULL, hdmi_irq_handler,
-                        IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
+                        IRQF_ONESHOT, "OMAP HDMI", &hdmi);
         if (r) {
                 DSSERR("HDMI IRQ request failed\n");
                 goto err;
@@ -759,6 +793,8 @@ static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
 
         hdmi_uninit_output(pdev);
 
+        hdmi4_cec_uninit(&hdmi.core);
+
         hdmi_pll_uninit(&hdmi.pll);
 
         pm_runtime_disable(&pdev->dev);
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
new file mode 100644
index 000000000000..d86873f2abe6
--- /dev/null
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
@@ -0,0 +1,381 @@
+/*
+ * HDMI CEC
+ *
+ * Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
+ *
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Authors: Yong Zhi
+ *      Mythri pk <mythripk@ti.com>
+ *
+ * Heavily modified to use the linux CEC framework:
+ *
+ * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "dss.h"
+#include "hdmi.h"
+#include "hdmi4_core.h"
+#include "hdmi4_cec.h"
+
+/* HDMI CEC */
+#define HDMI_CEC_DEV_ID                         0x900
+#define HDMI_CEC_SPEC                           0x904
+
+/* Not really a debug register, more a low-level control register */
+#define HDMI_CEC_DBG_3                          0x91C
+#define HDMI_CEC_TX_INIT                        0x920
+#define HDMI_CEC_TX_DEST                        0x924
+#define HDMI_CEC_SETUP                          0x938
+#define HDMI_CEC_TX_COMMAND                     0x93C
+#define HDMI_CEC_TX_OPERAND                     0x940
+#define HDMI_CEC_TRANSMIT_DATA                  0x97C
+#define HDMI_CEC_CA_7_0                         0x988
+#define HDMI_CEC_CA_15_8                        0x98C
+#define HDMI_CEC_INT_STATUS_0                   0x998
+#define HDMI_CEC_INT_STATUS_1                   0x99C
+#define HDMI_CEC_INT_ENABLE_0                   0x990
+#define HDMI_CEC_INT_ENABLE_1                   0x994
+#define HDMI_CEC_RX_CONTROL                     0x9B0
+#define HDMI_CEC_RX_COUNT                       0x9B4
+#define HDMI_CEC_RX_CMD_HEADER                  0x9B8
+#define HDMI_CEC_RX_COMMAND                     0x9BC
+#define HDMI_CEC_RX_OPERAND                     0x9C0
+
+#define HDMI_CEC_TX_FIFO_INT_MASK               0x64
+#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK        0x2
+
+#define HDMI_CORE_CEC_RETRY    200
+
+static void hdmi_cec_received_msg(struct hdmi_core_data *core)
+{
+        u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
+
+        /* While there are CEC frames in the FIFO */
+        while (cnt & 0x70) {
+                /* and the frame doesn't have an error */
+                if (!(cnt & 0x80)) {
+                        struct cec_msg msg = {};
+                        unsigned int i;
+
+                        /* then read the message */
+                        msg.len = cnt & 0xf;
+                        msg.msg[0] = hdmi_read_reg(core->base,
+                                                   HDMI_CEC_RX_CMD_HEADER);
+                        msg.msg[1] = hdmi_read_reg(core->base,
+                                                   HDMI_CEC_RX_COMMAND);
+                        for (i = 0; i < msg.len; i++) {
+                                unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
+
+                                msg.msg[2 + i] =
+                                        hdmi_read_reg(core->base, reg);
+                        }
+                        msg.len += 2;
+                        cec_received_msg(core->adap, &msg);
+                }
+                /* Clear the current frame from the FIFO */
+                hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
+                /* Wait until the current frame is cleared */
+                while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
+                        udelay(1);
+                /*
+                 * Re-read the count register and loop to see if there are
+                 * more messages in the FIFO.
+                 */
+                cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
+        }
+}
+
+static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
+{
+        if (stat1 & 2) {
+                u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
+
+                cec_transmit_done(core->adap,
+                                  CEC_TX_STATUS_NACK |
+                                  CEC_TX_STATUS_MAX_RETRIES,
+                                  0, (dbg3 >> 4) & 7, 0, 0);
+        } else if (stat1 & 1) {
+                cec_transmit_done(core->adap,
+                                  CEC_TX_STATUS_ARB_LOST |
+                                  CEC_TX_STATUS_MAX_RETRIES,
+                                  0, 0, 0, 0);
+        } else if (stat1 == 0) {
+                cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
+                                  0, 0, 0, 0);
+        }
+}
+
+void hdmi4_cec_irq(struct hdmi_core_data *core)
+{
+        u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
+        u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
+
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
+
+        if (stat0 & 0x40)
+                REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
+        else if (stat0 & 0x24)
+                hdmi_cec_transmit_fifo_empty(core, stat1);
+        if (stat1 & 2) {
+                u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
+
+                cec_transmit_done(core->adap,
+                                  CEC_TX_STATUS_NACK |
+                                  CEC_TX_STATUS_MAX_RETRIES,
+                                  0, (dbg3 >> 4) & 7, 0, 0);
+        } else if (stat1 & 1) {
+                cec_transmit_done(core->adap,
+                                  CEC_TX_STATUS_ARB_LOST |
+                                  CEC_TX_STATUS_MAX_RETRIES,
+                                  0, 0, 0, 0);
+        }
+        if (stat0 & 0x02)
+                hdmi_cec_received_msg(core);
+        if (stat1 & 0x3)
+                REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
+}
+
+static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
+{
+        struct hdmi_core_data *core = cec_get_drvdata(adap);
+        int retry = HDMI_CORE_CEC_RETRY;
+        int temp;
+
+        REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
+        while (retry) {
+                temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
+                if (FLD_GET(temp, 7, 7) == 0)
+                        break;
+                retry--;
+        }
+        return retry != 0;
+}
+
+static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
+{
+        struct hdmi_core_data *core = cec_get_drvdata(adap);
+        int retry = HDMI_CORE_CEC_RETRY;
+        int temp;
+
+        hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
+        retry = HDMI_CORE_CEC_RETRY;
+        while (retry) {
+                temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
+                if (FLD_GET(temp, 1, 0) == 0)
+                        break;
+                retry--;
+        }
+        return retry != 0;
+}
+
+static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
+{
+        struct hdmi_core_data *core = cec_get_drvdata(adap);
+        int temp, err;
+
+        if (!enable) {
+                hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
+                hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
+                REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
+                hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
+                hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
+                hdmi4_core_disable(NULL);
+                return 0;
+        }
+        err = hdmi4_core_enable(NULL);
+        if (err)
+                return err;
+
+        /* Clear TX FIFO */
+        if (!hdmi_cec_clear_tx_fifo(adap)) {
+                pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
+                return -EIO;
+        }
+
+        /* Clear RX FIFO */
+        if (!hdmi_cec_clear_rx_fifo(adap)) {
+                pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
+                return -EIO;
+        }
+
+        /* Clear CEC interrupts */
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
+                hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
+                hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
+
+        /* Enable HDMI core interrupts */
+        hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
+        /* Unmask CEC interrupt */
+        REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
+        /*
+         * Enable CEC interrupts:
+         * Transmit Buffer Full/Empty Change event
+         * Transmitter FIFO Empty event
+         * Receiver FIFO Not Empty event
+         */
+        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
+        /*
+         * Enable CEC interrupts:
+         * RX FIFO Overrun Error event
+         * Short Pulse Detected event
+         * Frame Retransmit Count Exceeded event
+         * Start Bit Irregularity event
+         */
+        hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
+
+        /* cec calibration enable (self clearing) */
+        hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
+        msleep(20);
+        hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
+
+        temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
+        if (FLD_GET(temp, 4, 4) != 0) {
+                temp = FLD_MOD(temp, 0, 4, 4);
+                hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
+
+                /*
+                 * If we enabled CEC in middle of a CEC message on the bus,
+                 * we could have start bit irregularity and/or short
+                 * pulse event. Clear them now.
+                 */
+                temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
+                temp = FLD_MOD(0x0, 0x5, 2, 0);
+                hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
+        }
+        return 0;
+}
+
+static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
+{
+        struct hdmi_core_data *core = cec_get_drvdata(adap);
+        u32 v;
+
+        if (log_addr == CEC_LOG_ADDR_INVALID) {
+                hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
+                hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
+                return 0;
+        }
+        if (log_addr <= 7) {
+                v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
+                v |= 1 << log_addr;
+                hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
+        } else {
+                v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
+                v |= 1 << (log_addr - 8);
+                hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
+        }
+        return 0;
+}
+
+static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+                                   u32 signal_free_time, struct cec_msg *msg)
+{
+        struct hdmi_core_data *core = cec_get_drvdata(adap);
+        int temp;
+        u32 i;
+
+        /* Clear TX FIFO */
+        if (!hdmi_cec_clear_tx_fifo(adap)) {
+                pr_err("cec-%s: could not clear TX FIFO for transmit\n",
+                       adap->name);
+                return -EIO;
+        }
+
+        /* Clear TX interrupts */
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
+                       HDMI_CEC_TX_FIFO_INT_MASK);
+
+        hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
+                       HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
+
+        /* Set the retry count */
+        REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
+
+        /* Set the initiator addresses */
+        hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
+
+        /* Set destination id */
+        temp = cec_msg_destination(msg);
+        if (msg->len == 1)
+                temp |= 0x80;
+        hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
+        if (msg->len == 1)
+                return 0;
+
+        /* Setup command and arguments for the command */
+        hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
+
+        for (i = 0; i < msg->len - 2; i++)
+                hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
+                               msg->msg[2 + i]);
+
+        /* Operand count */
+        hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
+                       (msg->len - 2) | 0x10);
+        return 0;
+}
+
+static const struct cec_adap_ops hdmi_cec_adap_ops = {
+        .adap_enable = hdmi_cec_adap_enable,
+        .adap_log_addr = hdmi_cec_adap_log_addr,
+        .adap_transmit = hdmi_cec_adap_transmit,
+};
+
+void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
+{
+        cec_s_phys_addr(core->adap, pa, false);
+}
+
+int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
+                  struct hdmi_wp_data *wp)
+{
+        const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
+                         CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
+        unsigned int ret;
+
+        core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
+                "omap4", caps, CEC_MAX_LOG_ADDRS);
+        ret = PTR_ERR_OR_ZERO(core->adap);
+        if (ret < 0)
+                return ret;
+        core->wp = wp;
+
+        /*
+         * Initialize CEC clock divider: CEC needs 2MHz clock hence
+         * set the devider to 24 to get 48/24=2MHz clock
+         */
+        REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
+
+        ret = cec_register_adapter(core->adap, &pdev->dev);
+        if (ret < 0) {
+                cec_delete_adapter(core->adap);
+                return ret;
+        }
+        return 0;
+}
+
+void hdmi4_cec_uninit(struct hdmi_core_data *core)
+{
+        cec_unregister_adapter(core->adap);
+}
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h
new file mode 100644
index 000000000000..0292337c97cc
--- /dev/null
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h
@@ -0,0 +1,55 @@
+/*
+ * HDMI header definition for OMAP4 HDMI CEC IP
+ *
+ * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
+ *
+ * This program is free software; you may redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _HDMI4_CEC_H_
+#define _HDMI4_CEC_H_
+
+struct hdmi_core_data;
+struct hdmi_wp_data;
+struct platform_device;
+
+/* HDMI CEC funcs */
+#ifdef CONFIG_OMAP4_DSS_HDMI_CEC
+void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa);
+void hdmi4_cec_irq(struct hdmi_core_data *core);
+int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
+                  struct hdmi_wp_data *wp);
+void hdmi4_cec_uninit(struct hdmi_core_data *core);
+#else
+static inline void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
+{
+}
+
+static inline void hdmi4_cec_irq(struct hdmi_core_data *core)
+{
+}
+
+static inline int hdmi4_cec_init(struct platform_device *pdev,
+                                struct hdmi_core_data *core,
+                                struct hdmi_wp_data *wp)
+{
+        return 0;
+}
+
+static inline void hdmi4_cec_uninit(struct hdmi_core_data *core)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index 365cf07daa01..62e451162d96 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -208,9 +208,9 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 }
 
-static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
+void hdmi4_core_powerdown_disable(struct hdmi_core_data *core)
 {
-        DSSDBG("Enter hdmi_core_powerdown_disable\n");
+        DSSDBG("Enter hdmi4_core_powerdown_disable\n");
         REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
 }
 
@@ -335,9 +335,6 @@ void hdmi4_configure(struct hdmi_core_data *core,
          */
         hdmi_core_swreset_assert(core);
 
-        /* power down off */
-        hdmi_core_powerdown_disable(core);
-
         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
         v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
 
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
index a069f96ec6f6..b6ab579e44d2 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
@@ -266,6 +266,10 @@ void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
 
+int hdmi4_core_enable(struct omap_dss_device *dssdev);
+void hdmi4_core_disable(struct omap_dss_device *dssdev);
+void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);
+
 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 47a331670963..990422b35784 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -395,6 +395,7 @@ struct omapdss_hdmi_ops {
                             struct videomode *vm);
 
         int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
+        void (*lost_hotplug)(struct omap_dss_device *dssdev);
         bool (*detect)(struct omap_dss_device *dssdev);
 
         int (*register_hpd_cb)(struct omap_dss_device *dssdev,
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 718d8ce15b1f..726f3fb3312d 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -82,6 +82,14 @@ config DRM_PANEL_PANASONIC_VVX10F034N00
           WUXGA (1920x1200) Novatek NT1397-based DSI panel as found in some
           Xperia Z2 tablets
 
+config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN
+        tristate "Raspberry Pi 7-inch touchscreen panel"
+        depends on DRM_MIPI_DSI
+        help
+          Say Y here if you want to enable support for the Raspberry
+          Pi 7" Touchscreen.  To compile this driver as a module,
+          choose M here.
+
 config DRM_PANEL_SAMSUNG_S6E3HA2
         tristate "Samsung S6E3HA2 DSI video mode panel"
         depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index c8483fdd5b9b..77ede3467324 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
 obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
 obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o
 obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
+obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
diff --git a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
new file mode 100644
index 000000000000..890fd6ff397c
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright © 2016-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Portions of this file (derived from panel-simple.c) are:
+ *
+ * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * Raspberry Pi 7" touchscreen panel driver.
+ *
+ * The 7" touchscreen consists of a DPI LCD panel, a Toshiba
+ * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
+ * controlling power management, the LCD PWM, and initial register
+ * setup of the Tohsiba.
+ *
+ * This driver controls the TC358762 and ATTINY88, presenting a DSI
+ * device with a drm_panel.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/pm.h>
+
+#include <drm/drm_panel.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
+
+/* I2C registers of the Atmel microcontroller. */
+enum REG_ADDR {
+        REG_ID = 0x80,
+        REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
+        REG_PORTB,
+        REG_PORTC,
+        REG_PORTD,
+        REG_POWERON,
+        REG_PWM,
+        REG_DDRA,
+        REG_DDRB,
+        REG_DDRC,
+        REG_DDRD,
+        REG_TEST,
+        REG_WR_ADDRL,
+        REG_WR_ADDRH,
+        REG_READH,
+        REG_READL,
+        REG_WRITEH,
+        REG_WRITEL,
+        REG_ID2,
+};
+
+/* DSI D-PHY Layer Registers */
+#define D0W_DPHYCONTTX          0x0004
+#define CLW_DPHYCONTRX          0x0020
+#define D0W_DPHYCONTRX          0x0024
+#define D1W_DPHYCONTRX          0x0028
+#define COM_DPHYCONTRX          0x0038
+#define CLW_CNTRL               0x0040
+#define D0W_CNTRL               0x0044
+#define D1W_CNTRL               0x0048
+#define DFTMODE_CNTRL           0x0054
+
+/* DSI PPI Layer Registers */
+#define PPI_STARTPPI            0x0104
+#define PPI_BUSYPPI             0x0108
+#define PPI_LINEINITCNT         0x0110
+#define PPI_LPTXTIMECNT         0x0114
+#define PPI_CLS_ATMR            0x0140
+#define PPI_D0S_ATMR            0x0144
+#define PPI_D1S_ATMR            0x0148
+#define PPI_D0S_CLRSIPOCOUNT    0x0164
+#define PPI_D1S_CLRSIPOCOUNT    0x0168
+#define CLS_PRE                 0x0180
+#define D0S_PRE                 0x0184
+#define D1S_PRE                 0x0188
+#define CLS_PREP                0x01A0
+#define D0S_PREP                0x01A4
+#define D1S_PREP                0x01A8
+#define CLS_ZERO                0x01C0
+#define D0S_ZERO                0x01C4
+#define D1S_ZERO                0x01C8
+#define PPI_CLRFLG              0x01E0
+#define PPI_CLRSIPO             0x01E4
+#define HSTIMEOUT               0x01F0
+#define HSTIMEOUTENABLE         0x01F4
+
+/* DSI Protocol Layer Registers */
+#define DSI_STARTDSI            0x0204
+#define DSI_BUSYDSI             0x0208
+#define DSI_LANEENABLE          0x0210
+# define DSI_LANEENABLE_CLOCK           BIT(0)
+# define DSI_LANEENABLE_D0              BIT(1)
+# define DSI_LANEENABLE_D1              BIT(2)
+
+#define DSI_LANESTATUS0         0x0214
+#define DSI_LANESTATUS1         0x0218
+#define DSI_INTSTATUS           0x0220
+#define DSI_INTMASK             0x0224
+#define DSI_INTCLR              0x0228
+#define DSI_LPTXTO              0x0230
+#define DSI_MODE                0x0260
+#define DSI_PAYLOAD0            0x0268
+#define DSI_PAYLOAD1            0x026C
+#define DSI_SHORTPKTDAT         0x0270
+#define DSI_SHORTPKTREQ         0x0274
+#define DSI_BTASTA              0x0278
+#define DSI_BTACLR              0x027C
+
+/* DSI General Registers */
+#define DSIERRCNT               0x0300
+#define DSISIGMOD               0x0304
+
+/* DSI Application Layer Registers */
+#define APLCTRL                 0x0400
+#define APLSTAT                 0x0404
+#define APLERR                  0x0408
+#define PWRMOD                  0x040C
+#define RDPKTLN                 0x0410
+#define PXLFMT                  0x0414
+#define MEMWRCMD                0x0418
+
+/* LCDC/DPI Host Registers */
+#define LCDCTRL                 0x0420
+#define HSR                     0x0424
+#define HDISPR                  0x0428
+#define VSR                     0x042C
+#define VDISPR                  0x0430
+#define VFUEN                   0x0434
+
+/* DBI-B Host Registers */
+#define DBIBCTRL                0x0440
+
+/* SPI Master Registers */
+#define SPICMR                  0x0450
+#define SPITCR                  0x0454
+
+/* System Controller Registers */
+#define SYSSTAT                 0x0460
+#define SYSCTRL                 0x0464
+#define SYSPLL1                 0x0468
+#define SYSPLL2                 0x046C
+#define SYSPLL3                 0x0470
+#define SYSPMCTRL               0x047C
+
+/* GPIO Registers */
+#define GPIOC                   0x0480
+#define GPIOO                   0x0484
+#define GPIOI                   0x0488
+
+/* I2C Registers */
+#define I2CCLKCTRL              0x0490
+
+/* Chip/Rev Registers */
+#define IDREG                   0x04A0
+
+/* Debug Registers */
+#define WCMDQUEUE               0x0500
+#define RCMDQUEUE               0x0504
+
+struct rpi_touchscreen {
+        struct drm_panel base;
+        struct mipi_dsi_device *dsi;
+        struct i2c_client *i2c;
+};
+
+static const struct drm_display_mode rpi_touchscreen_modes[] = {
+        {
+                /* Modeline comes from the Raspberry Pi firmware, with HFP=1
+                 * plugged in and clock re-computed from that.
+                 */
+                .clock = 25979400 / 1000,
+                .hdisplay = 800,
+                .hsync_start = 800 + 1,
+                .hsync_end = 800 + 1 + 2,
+                .htotal = 800 + 1 + 2 + 46,
+                .vdisplay = 480,
+                .vsync_start = 480 + 7,
+                .vsync_end = 480 + 7 + 2,
+                .vtotal = 480 + 7 + 2 + 21,
+                .vrefresh = 60,
+        },
+};
+
+static struct rpi_touchscreen *panel_to_ts(struct drm_panel *panel)
+{
+        return container_of(panel, struct rpi_touchscreen, base);
+}
+
+static u8 rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)
+{
+        return i2c_smbus_read_byte_data(ts->i2c, reg);
+}
+
+static void rpi_touchscreen_i2c_write(struct rpi_touchscreen *ts,
+                                      u8 reg, u8 val)
+{
+        int ret;
+
+        ret = i2c_smbus_write_byte_data(ts->i2c, reg, val);
+        if (ret)
+                dev_err(&ts->dsi->dev, "I2C write failed: %d\n", ret);
+}
+
+static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val)
+{
+#if 0
+        /* The firmware uses LP DSI transactions like this to bring up
+         * the hardware, which should be faster than using I2C to then
+         * pass to the Toshiba.  However, I was unable to get it to
+         * work.
+         */
+        u8 msg[] = {
+                reg,
+                reg >> 8,
+                val,
+                val >> 8,
+                val >> 16,
+                val >> 24,
+        };
+
+        mipi_dsi_dcs_write_buffer(ts->dsi, msg, sizeof(msg));
+#else
+        rpi_touchscreen_i2c_write(ts, REG_WR_ADDRH, reg >> 8);
+        rpi_touchscreen_i2c_write(ts, REG_WR_ADDRL, reg);
+        rpi_touchscreen_i2c_write(ts, REG_WRITEH, val >> 8);
+        rpi_touchscreen_i2c_write(ts, REG_WRITEL, val);
+#endif
+
+        return 0;
+}
+
+static int rpi_touchscreen_disable(struct drm_panel *panel)
+{
+        struct rpi_touchscreen *ts = panel_to_ts(panel);
+
+        rpi_touchscreen_i2c_write(ts, REG_PWM, 0);
+
+        rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
+        udelay(1);
+
+        return 0;
+}
+
+static int rpi_touchscreen_noop(struct drm_panel *panel)
+{
+        return 0;
+}
+
+static int rpi_touchscreen_enable(struct drm_panel *panel)
+{
+        struct rpi_touchscreen *ts = panel_to_ts(panel);
+        int i;
+
+        rpi_touchscreen_i2c_write(ts, REG_POWERON, 1);
+        /* Wait for nPWRDWN to go low to indicate poweron is done. */
+        for (i = 0; i < 100; i++) {
+                if (rpi_touchscreen_i2c_read(ts, REG_PORTB) & 1)
+                        break;
+        }
+
+        rpi_touchscreen_write(ts, DSI_LANEENABLE,
+                              DSI_LANEENABLE_CLOCK |
+                              DSI_LANEENABLE_D0);
+        rpi_touchscreen_write(ts, PPI_D0S_CLRSIPOCOUNT, 0x05);
+        rpi_touchscreen_write(ts, PPI_D1S_CLRSIPOCOUNT, 0x05);
+        rpi_touchscreen_write(ts, PPI_D0S_ATMR, 0x00);
+        rpi_touchscreen_write(ts, PPI_D1S_ATMR, 0x00);
+        rpi_touchscreen_write(ts, PPI_LPTXTIMECNT, 0x03);
+
+        rpi_touchscreen_write(ts, SPICMR, 0x00);
+        rpi_touchscreen_write(ts, LCDCTRL, 0x00100150);
+        rpi_touchscreen_write(ts, SYSCTRL, 0x040f);
+        msleep(100);
+
+        rpi_touchscreen_write(ts, PPI_STARTPPI, 0x01);
+        rpi_touchscreen_write(ts, DSI_STARTDSI, 0x01);
+        msleep(100);
+
+        /* Turn on the backlight. */
+        rpi_touchscreen_i2c_write(ts, REG_PWM, 255);
+
+        /* Default to the same orientation as the closed source
+         * firmware used for the panel.  Runtime rotation
+         * configuration will be supported using VC4's plane
+         * orientation bits.
+         */
+        rpi_touchscreen_i2c_write(ts, REG_PORTA, BIT(2));
+
+        return 0;
+}
+
+static int rpi_touchscreen_get_modes(struct drm_panel *panel)
+{
+        struct drm_connector *connector = panel->connector;
+        struct drm_device *drm = panel->drm;
+        unsigned int i, num = 0;
+        static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+
+        for (i = 0; i < ARRAY_SIZE(rpi_touchscreen_modes); i++) {
+                const struct drm_display_mode *m = &rpi_touchscreen_modes[i];
+                struct drm_display_mode *mode;
+
+                mode = drm_mode_duplicate(drm, m);
+                if (!mode) {
+                        dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
+                                m->hdisplay, m->vdisplay, m->vrefresh);
+                        continue;
+                }
+
+                mode->type |= DRM_MODE_TYPE_DRIVER;
+
+                if (i == 0)
+                        mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+                drm_mode_set_name(mode);
+
+                drm_mode_probed_add(connector, mode);
+                num++;
+        }
+
+        connector->display_info.bpc = 8;
+        connector->display_info.width_mm = 154;
+        connector->display_info.height_mm = 86;
+        drm_display_info_set_bus_formats(&connector->display_info,
+                                         &bus_format, 1);
+
+        return num;
+}
+
+static const struct drm_panel_funcs rpi_touchscreen_funcs = {
+        .disable = rpi_touchscreen_disable,
+        .unprepare = rpi_touchscreen_noop,
+        .prepare = rpi_touchscreen_noop,
+        .enable = rpi_touchscreen_enable,
+        .get_modes = rpi_touchscreen_get_modes,
+};
+
+static int rpi_touchscreen_probe(struct i2c_client *i2c,
+                                 const struct i2c_device_id *id)
+{
+        struct device *dev = &i2c->dev;
+        struct rpi_touchscreen *ts;
+        struct device_node *endpoint, *dsi_host_node;
+        struct mipi_dsi_host *host;
+        int ret, ver;
+        struct mipi_dsi_device_info info = {
+                .type = RPI_DSI_DRIVER_NAME,
+                .channel = 0,
+                .node = NULL,
+        };
+
+        ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
+        if (!ts)
+                return -ENOMEM;
+
+        i2c_set_clientdata(i2c, ts);
+
+        ts->i2c = i2c;
+
+        ver = rpi_touchscreen_i2c_read(ts, REG_ID);
+        if (ver < 0) {
+                dev_err(dev, "Atmel I2C read failed: %d\n", ver);
+                return -ENODEV;
+        }
+
+        switch (ver) {
+        case 0xde: /* ver 1 */
+        case 0xc3: /* ver 2 */
+                break;
+        default:
+                dev_err(dev, "Unknown Atmel firmware revision: 0x%02x\n", ver);
+                return -ENODEV;
+        }
+
+        /* Turn off at boot, so we can cleanly sequence powering on. */
+        rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
+
+        /* Look up the DSI host.  It needs to probe before we do. */
+        endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+        dsi_host_node = of_graph_get_remote_port_parent(endpoint);
+        host = of_find_mipi_dsi_host_by_node(dsi_host_node);
+        of_node_put(dsi_host_node);
+        if (!host) {
+                of_node_put(endpoint);
+                return -EPROBE_DEFER;
+        }
+
+        info.node = of_graph_get_remote_port(endpoint);
+        of_node_put(endpoint);
+
+        ts->dsi = mipi_dsi_device_register_full(host, &info);
+        if (IS_ERR(ts->dsi)) {
+                dev_err(dev, "DSI device registration failed: %ld\n",
+                        PTR_ERR(ts->dsi));
+                return PTR_ERR(ts->dsi);
+        }
+
+        ts->base.dev = dev;
+        ts->base.funcs = &rpi_touchscreen_funcs;
+
+        /* This appears last, as it's what will unblock the DSI host
+         * driver's component bind function.
+         */
+        ret = drm_panel_add(&ts->base);
+        if (ret)
+                return ret;
+
+        return 0;
+}
+
+static int rpi_touchscreen_remove(struct i2c_client *i2c)
+{
+        struct rpi_touchscreen *ts = i2c_get_clientdata(i2c);
+
+        mipi_dsi_detach(ts->dsi);
+
+        drm_panel_remove(&ts->base);
+
+        mipi_dsi_device_unregister(ts->dsi);
+        kfree(ts->dsi);
+
+        return 0;
+}
+
+static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi)
+{
+        int ret;
+
+        dsi->mode_flags = (MIPI_DSI_MODE_VIDEO |
+                           MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+                           MIPI_DSI_MODE_LPM);
+        dsi->format = MIPI_DSI_FMT_RGB888;
+        dsi->lanes = 1;
+
+        ret = mipi_dsi_attach(dsi);
+
+        if (ret)
+                dev_err(&dsi->dev, "failed to attach dsi to host: %d\n", ret);
+
+        return ret;
+}
+
+static struct mipi_dsi_driver rpi_touchscreen_dsi_driver = {
+        .driver.name = RPI_DSI_DRIVER_NAME,
+        .probe = rpi_touchscreen_dsi_probe,
+};
+
+static const struct of_device_id rpi_touchscreen_of_ids[] = {
+        { .compatible = "raspberrypi,7inch-touchscreen-panel" },
+        { } /* sentinel */
+};
+MODULE_DEVICE_TABLE(of, rpi_touchscreen_of_ids);
+
+static struct i2c_driver rpi_touchscreen_driver = {
+        .driver = {
+                .name = "rpi_touchscreen",
+                .of_match_table = rpi_touchscreen_of_ids,
+        },
+        .probe = rpi_touchscreen_probe,
+        .remove = rpi_touchscreen_remove,
+};
+
+static int __init rpi_touchscreen_init(void)
+{
+        mipi_dsi_driver_register(&rpi_touchscreen_dsi_driver);
+        return i2c_add_driver(&rpi_touchscreen_driver);
+}
+module_init(rpi_touchscreen_init);
+
+static void __exit rpi_touchscreen_exit(void)
+{
+        i2c_del_driver(&rpi_touchscreen_driver);
+        mipi_dsi_driver_unregister(&rpi_touchscreen_dsi_driver);
+}
+module_exit(rpi_touchscreen_exit);
+
+MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
+MODULE_DESCRIPTION("Raspberry Pi 7-inch touchscreen driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c31e660e35db..7d39ed63e5be 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1456,7 +1456,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 5);
         reg = R100_CP_PACKET0_GET_REG(header);
-        crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
+        crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
         if (!crtc) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
                 return -ENOENT;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 97fd58e97043..c96b31950ca7 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -887,7 +887,7 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
         reg = R600_CP_PACKET0_GET_REG(header);
 
-        crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
+        crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
         if (!crtc) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
                 return -ENOENT;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 2f642cbefd8e..59dcefb2df3b 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -263,7 +263,7 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev,
+                encoder = drm_encoder_find(connector->dev, NULL,
                                            connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
@@ -290,7 +290,7 @@ static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector,
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
@@ -404,7 +404,7 @@ static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *conn
         int enc_id = connector->encoder_ids[0];
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
@@ -1368,7 +1368,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
                         if (connector->encoder_ids[i] == 0)
                                 break;
 
-                        encoder = drm_encoder_find(connector->dev,
+                        encoder = drm_encoder_find(connector->dev, NULL,
                                                    connector->encoder_ids[i]);
                         if (!encoder)
                                 continue;
@@ -1454,7 +1454,7 @@ static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
@@ -1473,7 +1473,7 @@ static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
         /* then check use digitial */
         /* pick the first one */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
         return NULL;
 }
 
@@ -1620,7 +1620,7 @@ u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
@@ -1649,7 +1649,7 @@ static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
                 if (connector->encoder_ids[i] == 0)
                         break;
 
-                encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
+                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
                 if (!encoder)
                         continue;
 
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0c31f0a27b9c..3c70c6224bd2 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -60,6 +60,7 @@ config ROCKCHIP_INNO_HDMI
 config ROCKCHIP_LVDS
         bool "Rockchip LVDS support"
         depends on DRM_ROCKCHIP
+        depends on PINCTRL
         help
           Choose this option to enable support for Rockchip LVDS controllers.
           Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index d394a03632c4..735c9081202a 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -791,9 +791,8 @@ static const struct drm_encoder_funcs ltdc_encoder_funcs = {
         .destroy = drm_encoder_cleanup,
 };
 
-static int ltdc_encoder_init(struct drm_device *ddev)
+static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
 {
-        struct ltdc_device *ldev = ddev->dev_private;
         struct drm_encoder *encoder;
         int ret;
 
@@ -807,7 +806,7 @@ static int ltdc_encoder_init(struct drm_device *ddev)
         drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
                          DRM_MODE_ENCODER_DPI, NULL);
 
-        ret = drm_bridge_attach(encoder, ldev->bridge, NULL);
+        ret = drm_bridge_attach(encoder, bridge, NULL);
         if (ret) {
                 drm_encoder_cleanup(encoder);
                 return -EINVAL;
@@ -936,12 +935,9 @@ int ltdc_load(struct drm_device *ddev)
                         ret = PTR_ERR(bridge);
                         goto err;
                 }
-                ldev->is_panel_bridge = true;
         }
 
-        ldev->bridge = bridge;
-
-        ret = ltdc_encoder_init(ddev);
+        ret = ltdc_encoder_init(ddev, bridge);
         if (ret) {
                 DRM_ERROR("Failed to init encoder\n");
                 goto err;
@@ -972,8 +968,7 @@ int ltdc_load(struct drm_device *ddev)
         return 0;
 
 err:
-        if (ldev->is_panel_bridge)
-                drm_panel_bridge_remove(bridge);
+        drm_panel_bridge_remove(bridge);
 
         clk_disable_unprepare(ldev->pixel_clk);
 
@@ -986,8 +981,7 @@ void ltdc_unload(struct drm_device *ddev)
 
         DRM_DEBUG_DRIVER("\n");
 
-        if (ldev->is_panel_bridge)
-                drm_panel_bridge_remove(ldev->bridge);
+        drm_of_panel_bridge_remove(ddev->dev->of_node, 0, 0);
 
         clk_disable_unprepare(ldev->pixel_clk);
 }
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index bc6d6f6419a9..ae437557d715 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -24,8 +24,6 @@ struct ltdc_device {
         struct drm_fbdev_cma *fbdev;
         void __iomem *regs;
         struct clk *pixel_clk;  /* lcd pixel clock */
-        struct drm_bridge *bridge;
-        bool is_panel_bridge;
         struct mutex err_lock;  /* protecting error_status */
         struct ltdc_caps caps;
         u32 error_status;
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index ec5943627aa5..4fefd8add714 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -209,22 +209,11 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 {
         struct drm_plane_state *state = plane->state;
         struct drm_framebuffer *fb = state->fb;
-        struct drm_gem_cma_object *gem;
         u32 lo_paddr, hi_paddr;
         dma_addr_t paddr;
-        int bpp;
-
-        /* Get the physical address of the buffer in memory */
-        gem = drm_fb_cma_get_gem_obj(fb, 0);
-
-        DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
-
-        /* Compute the start of the displayed memory */
-        bpp = fb->format->cpp[0];
-        paddr = gem->paddr + fb->offsets[0];
-        paddr += (state->src_x >> 16) * bpp;
-        paddr += (state->src_y >> 16) * fb->pitches[0];
 
+        /* Get the start of the displayed memory */
+        paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 
         /* Write the 32 lower bits of the address (in bits) */
@@ -369,13 +358,6 @@ static int sun4i_backend_bind(struct device *dev, struct device *master,
         if (IS_ERR(regs))
                 return PTR_ERR(regs);
 
-        backend->engine.regs = devm_regmap_init_mmio(dev, regs,
-                                                     &sun4i_backend_regmap_config);
-        if (IS_ERR(backend->engine.regs)) {
-                dev_err(dev, "Couldn't create the backend regmap\n");
-                return PTR_ERR(backend->engine.regs);
-        }
-
         backend->reset = devm_reset_control_get(dev, NULL);
         if (IS_ERR(backend->reset)) {
                 dev_err(dev, "Couldn't get our reset line\n");
@@ -421,9 +403,23 @@ static int sun4i_backend_bind(struct device *dev, struct device *master,
                 }
         }
 
+        backend->engine.regs = devm_regmap_init_mmio(dev, regs,
+                                                     &sun4i_backend_regmap_config);
+        if (IS_ERR(backend->engine.regs)) {
+                dev_err(dev, "Couldn't create the backend regmap\n");
+                return PTR_ERR(backend->engine.regs);
+        }
+
         list_add_tail(&backend->engine.list, &drv->engine_list);
 
-        /* Reset the registers */
+        /*
+         * Many of the backend's layer configuration registers have
+         * undefined default values. This poses a risk as we use
+         * regmap_update_bits in some places, and don't overwrite
+         * the whole register.
+         *
+         * Clear the registers here to have something predictable.
+         */
         for (i = 0x800; i < 0x1000; i += 4)
                 regmap_write(backend->engine.regs, i, 0);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index a2012638d5f7..b5879d4620d8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -226,6 +226,18 @@ struct endpoint_list {
         struct list_head list;
 };
 
+static bool node_is_in_list(struct list_head *endpoints,
+                            struct device_node *node)
+{
+        struct endpoint_list *endpoint;
+
+        list_for_each_entry(endpoint, endpoints, list)
+                if (endpoint->node == node)
+                        return true;
+
+        return false;
+}
+
 static int sun4i_drv_add_endpoints(struct device *dev,
                                    struct list_head *endpoints,
                                    struct component_match **match,
@@ -292,6 +304,10 @@ static int sun4i_drv_add_endpoints(struct device *dev,
                         }
                 }
 
+                /* skip downstream node if it is already in the queue */
+                if (node_is_in_list(endpoints, remote))
+                        continue;
+
                 /* Add downstream nodes to the queue */
                 endpoint = kzalloc(sizeof(*endpoint), GFP_KERNEL);
                 if (!endpoint) {
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index a1f8cba251a2..b685ee11623d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -14,6 +14,7 @@
 
 #include <drm/drm_connector.h>
 #include <drm/drm_encoder.h>
+#include <linux/regmap.h>
 
 #include <media/cec-pin.h>
 
@@ -58,16 +59,24 @@
 #define SUN4I_HDMI_PAD_CTRL0_TXEN               BIT(23)
 
 #define SUN4I_HDMI_PAD_CTRL1_REG        0x204
+#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN            BIT(24) /* set on A31 */
 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT            BIT(23)
 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT          BIT(22)
 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT            BIT(20)
 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT          BIT(19)
+#define SUN4I_HDMI_PAD_CTRL1_PWSCK              BIT(18)
+#define SUN4I_HDMI_PAD_CTRL1_PWSDT              BIT(17)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN            BIT(15)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK          BIT(14)
 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)         (((n) & 7) << 10)
 #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK          BIT(6)
 #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n)         (((n) & 7) << 3)
 
+/* These bits seem to invert the TMDS data channels */
+#define SUN4I_HDMI_PAD_CTRL1_INVERT_R           BIT(2)
+#define SUN4I_HDMI_PAD_CTRL1_INVERT_G           BIT(1)
+#define SUN4I_HDMI_PAD_CTRL1_INVERT_B           BIT(0)
+
 #define SUN4I_HDMI_PLL_CTRL_REG         0x208
 #define SUN4I_HDMI_PLL_CTRL_PLL_EN              BIT(31)
 #define SUN4I_HDMI_PLL_CTRL_BWS                 BIT(30)
@@ -152,21 +161,106 @@
 
 #define SUN4I_HDMI_DDC_FIFO_SIZE        16
 
+/* A31 specific */
+#define SUN6I_HDMI_DDC_CTRL_REG         0x500
+#define SUN6I_HDMI_DDC_CTRL_RESET               BIT(31)
+#define SUN6I_HDMI_DDC_CTRL_START_CMD           BIT(27)
+#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE          BIT(6)
+#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE          BIT(4)
+#define SUN6I_HDMI_DDC_CTRL_ENABLE              BIT(0)
+
+#define SUN6I_HDMI_DDC_CMD_REG          0x508
+#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)    ((count) << 16)
+/* command types in lower 3 bits are the same as sun4i */
+
+#define SUN6I_HDMI_DDC_ADDR_REG         0x50c
+#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)        (((seg) & 0xff) << 24)
+#define SUN6I_HDMI_DDC_ADDR_EDDC(addr)          (((addr) & 0xff) << 16)
+#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)         (((off) & 0xff) << 8)
+#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)         (((addr) & 0xff) << 1)
+
+#define SUN6I_HDMI_DDC_INT_STATUS_REG   0x514
+#define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT       BIT(8)
+/* lower 8 bits are the same as sun4i */
+
+#define SUN6I_HDMI_DDC_FIFO_CTRL_REG    0x518
+#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR          BIT(15)
+/* lower 9 bits are the same as sun4i */
+
+#define SUN6I_HDMI_DDC_CLK_REG          0x520
+/* DDC CLK bit fields are the same, but the formula is not */
+
+#define SUN6I_HDMI_DDC_FIFO_DATA_REG    0x580
+
 enum sun4i_hdmi_pkt_type {
         SUN4I_HDMI_PKT_AVI = 2,
         SUN4I_HDMI_PKT_END = 15,
 };
 
+struct sun4i_hdmi_variant {
+        bool has_ddc_parent_clk;
+        bool has_reset_control;
+
+        u32 pad_ctrl0_init_val;
+        u32 pad_ctrl1_init_val;
+        u32 pll_ctrl_init_val;
+
+        struct reg_field ddc_clk_reg;
+        u8 ddc_clk_pre_divider;
+        u8 ddc_clk_m_offset;
+
+        u8 tmds_clk_div_offset;
+
+        /* Register fields for I2C adapter */
+        struct reg_field        field_ddc_en;
+        struct reg_field        field_ddc_start;
+        struct reg_field        field_ddc_reset;
+        struct reg_field        field_ddc_addr_reg;
+        struct reg_field        field_ddc_slave_addr;
+        struct reg_field        field_ddc_int_mask;
+        struct reg_field        field_ddc_int_status;
+        struct reg_field        field_ddc_fifo_clear;
+        struct reg_field        field_ddc_fifo_rx_thres;
+        struct reg_field        field_ddc_fifo_tx_thres;
+        struct reg_field        field_ddc_byte_count;
+        struct reg_field        field_ddc_cmd;
+        struct reg_field        field_ddc_sda_en;
+        struct reg_field        field_ddc_sck_en;
+
+        /* DDC FIFO register offset */
+        u32                     ddc_fifo_reg;
+
+        /*
+         * DDC FIFO threshold boundary conditions
+         *
+         * This is used to cope with the threshold boundary condition
+         * being slightly different on sun5i and sun6i.
+         *
+         * On sun5i the threshold is exclusive, i.e. does not include,
+         * the value of the threshold. ( > for RX; < for TX )
+         * On sun6i the threshold is inclusive, i.e. includes, the
+         * value of the threshold. ( >= for RX; <= for TX )
+         */
+        bool                    ddc_fifo_thres_incl;
+
+        bool                    ddc_fifo_has_dir;
+};
+
 struct sun4i_hdmi {
         struct drm_connector    connector;
         struct drm_encoder      encoder;
         struct device           *dev;
 
         void __iomem            *base;
+        struct regmap           *regmap;
+
+        /* Reset control */
+        struct reset_control    *reset;
 
         /* Parent clocks */
         struct clk              *bus_clk;
         struct clk              *mod_clk;
+        struct clk              *ddc_parent_clk;
         struct clk              *pll0_clk;
         struct clk              *pll1_clk;
 
@@ -176,10 +270,28 @@ struct sun4i_hdmi {
 
         struct i2c_adapter      *i2c;
 
+        /* Regmap fields for I2C adapter */
+        struct regmap_field     *field_ddc_en;
+        struct regmap_field     *field_ddc_start;
+        struct regmap_field     *field_ddc_reset;
+        struct regmap_field     *field_ddc_addr_reg;
+        struct regmap_field     *field_ddc_slave_addr;
+        struct regmap_field     *field_ddc_int_mask;
+        struct regmap_field     *field_ddc_int_status;
+        struct regmap_field     *field_ddc_fifo_clear;
+        struct regmap_field     *field_ddc_fifo_rx_thres;
+        struct regmap_field     *field_ddc_fifo_tx_thres;
+        struct regmap_field     *field_ddc_byte_count;
+        struct regmap_field     *field_ddc_cmd;
+        struct regmap_field     *field_ddc_sda_en;
+        struct regmap_field     *field_ddc_sck_en;
+
         struct sun4i_drv        *drv;
 
         bool                    hdmi_monitor;
         struct cec_adapter      *cec_adap;
+
+        const struct sun4i_hdmi_variant *variant;
 };
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 4692e8c345ed..04f85b1cf922 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/regmap.h>
 
 #include "sun4i_tcon.h"
 #include "sun4i_hdmi.h"
@@ -18,6 +19,9 @@
 struct sun4i_ddc {
         struct clk_hw           hw;
         struct sun4i_hdmi       *hdmi;
+        struct regmap_field     *reg;
+        u8                      pre_div;
+        u8                      m_offset;
 };
 
 static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
@@ -27,6 +31,8 @@ static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
 
 static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
                                             unsigned long parent_rate,
+                                            const u8 pre_div,
+                                            const u8 m_offset,
                                             u8 *m, u8 *n)
 {
         unsigned long best_rate = 0;
@@ -36,7 +42,8 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
                 for (_n = 0; _n < 8; _n++) {
                         unsigned long tmp_rate;
 
-                        tmp_rate = (((parent_rate / 2) / 10) >> _n) / (_m + 1);
+                        tmp_rate = (((parent_rate / pre_div) / 10) >> _n) /
+                                (_m + m_offset);
 
                         if (tmp_rate > rate)
                                 continue;
@@ -60,21 +67,25 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
 static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
                                  unsigned long *prate)
 {
-        return sun4i_ddc_calc_divider(rate, *prate, NULL, NULL);
+        struct sun4i_ddc *ddc = hw_to_ddc(hw);
+
+        return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div,
+                                      ddc->m_offset, NULL, NULL);
 }
 
 static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
                                             unsigned long parent_rate)
 {
         struct sun4i_ddc *ddc = hw_to_ddc(hw);
-        u32 reg;
+        unsigned int reg;
         u8 m, n;
 
-        reg = readl(ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
-        m = (reg >> 3) & 0x7;
+        regmap_field_read(ddc->reg, &reg);
+        m = (reg >> 3) & 0xf;
         n = reg & 0x7;
 
-        return (((parent_rate / 2) / 10) >> n) / (m + 1);
+        return (((parent_rate / ddc->pre_div) / 10) >> n) /
+               (m + ddc->m_offset);
 }
 
 static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -83,10 +94,12 @@ static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
         struct sun4i_ddc *ddc = hw_to_ddc(hw);
         u8 div_m, div_n;
 
-        sun4i_ddc_calc_divider(rate, parent_rate, &div_m, &div_n);
+        sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div,
+                               ddc->m_offset, &div_m, &div_n);
 
-        writel(SUN4I_HDMI_DDC_CLK_M(div_m) | SUN4I_HDMI_DDC_CLK_N(div_n),
-               ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
+        regmap_field_write(ddc->reg,
+                           SUN4I_HDMI_DDC_CLK_M(div_m) |
+                           SUN4I_HDMI_DDC_CLK_N(div_n));
 
         return 0;
 }
@@ -111,6 +124,11 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
         if (!ddc)
                 return -ENOMEM;
 
+        ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                           hdmi->variant->ddc_clk_reg);
+        if (IS_ERR(ddc->reg))
+                return PTR_ERR(ddc->reg);
+
         init.name = "hdmi-ddc";
         init.ops = &sun4i_ddc_ops;
         init.parent_names = &parent_name;
@@ -118,6 +136,8 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
 
         ddc->hdmi = hdmi;
         ddc->hw.init = &init;
+        ddc->pre_div = hdmi->variant->ddc_clk_pre_divider;
+        ddc->m_offset = hdmi->variant->ddc_clk_m_offset;
 
         hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
         if (IS_ERR(hdmi->ddc_clk))
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 9ea6cd5a1370..6ca6e6a74c4a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -20,8 +20,11 @@
 #include <linux/clk.h>
 #include <linux/component.h>
 #include <linux/iopoll.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
 
 #include "sun4i_backend.h"
 #include "sun4i_crtc.h"
@@ -141,6 +144,22 @@ static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
         writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
                hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
 
+        /*
+         * Setup output pad (?) controls
+         *
+         * This is done here instead of at probe/bind time because
+         * the controller seems to toggle some of the bits on its own.
+         *
+         * We can't just initialize the register there, we need to
+         * protect the clock bits that have already been read out and
+         * cached by the clock framework.
+         */
+        val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
+        val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
+        val |= hdmi->variant->pad_ctrl1_init_val;
+        writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
+        val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
+
         /* Setup timing registers */
         writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
                SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
@@ -267,6 +286,124 @@ static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
 };
 #endif
 
+#define SUN4I_HDMI_PAD_CTRL1_MASK       (GENMASK(24, 7) | GENMASK(5, 0))
+#define SUN4I_HDMI_PLL_CTRL_MASK        (GENMASK(31, 8) | GENMASK(3, 0))
+
+static const struct sun4i_hdmi_variant sun5i_variant = {
+        .pad_ctrl0_init_val     = SUN4I_HDMI_PAD_CTRL0_TXEN |
+                                  SUN4I_HDMI_PAD_CTRL0_CKEN |
+                                  SUN4I_HDMI_PAD_CTRL0_PWENG |
+                                  SUN4I_HDMI_PAD_CTRL0_PWEND |
+                                  SUN4I_HDMI_PAD_CTRL0_PWENC |
+                                  SUN4I_HDMI_PAD_CTRL0_LDODEN |
+                                  SUN4I_HDMI_PAD_CTRL0_LDOCEN |
+                                  SUN4I_HDMI_PAD_CTRL0_BIASEN,
+        .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_DEN |
+                                  SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
+        .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
+                                  SUN4I_HDMI_PLL_CTRL_CS(7) |
+                                  SUN4I_HDMI_PLL_CTRL_CP_S(15) |
+                                  SUN4I_HDMI_PLL_CTRL_S(7) |
+                                  SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
+                                  SUN4I_HDMI_PLL_CTRL_SDIV2 |
+                                  SUN4I_HDMI_PLL_CTRL_LDO2_EN |
+                                  SUN4I_HDMI_PLL_CTRL_LDO1_EN |
+                                  SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
+                                  SUN4I_HDMI_PLL_CTRL_BWS |
+                                  SUN4I_HDMI_PLL_CTRL_PLL_EN,
+
+        .ddc_clk_reg            = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
+        .ddc_clk_pre_divider    = 2,
+        .ddc_clk_m_offset       = 1,
+
+        .field_ddc_en           = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
+        .field_ddc_start        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
+        .field_ddc_reset        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
+        .field_ddc_addr_reg     = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
+        .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
+        .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
+        .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
+        .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
+        .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
+        .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
+        .field_ddc_cmd          = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
+        .field_ddc_sda_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
+        .field_ddc_sck_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
+
+        .ddc_fifo_reg           = SUN4I_HDMI_DDC_FIFO_DATA_REG,
+        .ddc_fifo_has_dir       = true,
+};
+
+static const struct sun4i_hdmi_variant sun6i_variant = {
+        .has_ddc_parent_clk     = true,
+        .has_reset_control      = true,
+        .pad_ctrl0_init_val     = 0xff |
+                                  SUN4I_HDMI_PAD_CTRL0_TXEN |
+                                  SUN4I_HDMI_PAD_CTRL0_CKEN |
+                                  SUN4I_HDMI_PAD_CTRL0_PWENG |
+                                  SUN4I_HDMI_PAD_CTRL0_PWEND |
+                                  SUN4I_HDMI_PAD_CTRL0_PWENC |
+                                  SUN4I_HDMI_PAD_CTRL0_LDODEN |
+                                  SUN4I_HDMI_PAD_CTRL0_LDOCEN,
+        .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
+                                  SUN4I_HDMI_PAD_CTRL1_REG_DEN |
+                                  SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_PWSDT |
+                                  SUN4I_HDMI_PAD_CTRL1_PWSCK |
+                                  SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
+                                  SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
+        .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
+                                  SUN4I_HDMI_PLL_CTRL_CS(3) |
+                                  SUN4I_HDMI_PLL_CTRL_CP_S(10) |
+                                  SUN4I_HDMI_PLL_CTRL_S(4) |
+                                  SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
+                                  SUN4I_HDMI_PLL_CTRL_SDIV2 |
+                                  SUN4I_HDMI_PLL_CTRL_LDO2_EN |
+                                  SUN4I_HDMI_PLL_CTRL_LDO1_EN |
+                                  SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
+                                  SUN4I_HDMI_PLL_CTRL_PLL_EN,
+
+        .ddc_clk_reg            = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
+        .ddc_clk_pre_divider    = 1,
+        .ddc_clk_m_offset       = 2,
+
+        .tmds_clk_div_offset    = 1,
+
+        .field_ddc_en           = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
+        .field_ddc_start        = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
+        .field_ddc_reset        = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
+        .field_ddc_addr_reg     = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
+        .field_ddc_slave_addr   = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
+        .field_ddc_int_status   = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
+        .field_ddc_fifo_clear   = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
+        .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
+        .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
+        .field_ddc_byte_count   = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
+        .field_ddc_cmd          = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
+        .field_ddc_sda_en       = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
+        .field_ddc_sck_en       = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
+
+        .ddc_fifo_reg           = SUN6I_HDMI_DDC_FIFO_DATA_REG,
+        .ddc_fifo_thres_incl    = true,
+};
+
+static const struct regmap_config sun4i_hdmi_regmap_config = {
+        .reg_bits       = 32,
+        .val_bits       = 32,
+        .reg_stride     = 4,
+        .max_register   = 0x580,
+};
+
 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
                            void *data)
 {
@@ -285,6 +422,10 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
         hdmi->dev = dev;
         hdmi->drv = drv;
 
+        hdmi->variant = of_device_get_match_data(dev);
+        if (!hdmi->variant)
+                return -EINVAL;
+
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         hdmi->base = devm_ioremap_resource(dev, res);
         if (IS_ERR(hdmi->base)) {
@@ -292,77 +433,87 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master,
                 return PTR_ERR(hdmi->base);
         }
 
+        if (hdmi->variant->has_reset_control) {
+                hdmi->reset = devm_reset_control_get(dev, NULL);
+                if (IS_ERR(hdmi->reset)) {
+                        dev_err(dev, "Couldn't get the HDMI reset control\n");
+                        return PTR_ERR(hdmi->reset);
+                }
+
+                ret = reset_control_deassert(hdmi->reset);
+                if (ret) {
+                        dev_err(dev, "Couldn't deassert HDMI reset\n");
+                        return ret;
+                }
+        }
+
         hdmi->bus_clk = devm_clk_get(dev, "ahb");
         if (IS_ERR(hdmi->bus_clk)) {
                 dev_err(dev, "Couldn't get the HDMI bus clock\n");
-                return PTR_ERR(hdmi->bus_clk);
+                ret = PTR_ERR(hdmi->bus_clk);
+                goto err_assert_reset;
         }
         clk_prepare_enable(hdmi->bus_clk);
 
         hdmi->mod_clk = devm_clk_get(dev, "mod");
         if (IS_ERR(hdmi->mod_clk)) {
                 dev_err(dev, "Couldn't get the HDMI mod clock\n");
-                return PTR_ERR(hdmi->mod_clk);
+                ret = PTR_ERR(hdmi->mod_clk);
+                goto err_disable_bus_clk;
         }
         clk_prepare_enable(hdmi->mod_clk);
 
         hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
         if (IS_ERR(hdmi->pll0_clk)) {
                 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
-                return PTR_ERR(hdmi->pll0_clk);
+                ret = PTR_ERR(hdmi->pll0_clk);
+                goto err_disable_mod_clk;
         }
 
         hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
         if (IS_ERR(hdmi->pll1_clk)) {
                 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
-                return PTR_ERR(hdmi->pll1_clk);
+                ret = PTR_ERR(hdmi->pll1_clk);
+                goto err_disable_mod_clk;
+        }
+
+        hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
+                                             &sun4i_hdmi_regmap_config);
+        if (IS_ERR(hdmi->regmap)) {
+                dev_err(dev, "Couldn't create HDMI encoder regmap\n");
+                return PTR_ERR(hdmi->regmap);
         }
 
         ret = sun4i_tmds_create(hdmi);
         if (ret) {
                 dev_err(dev, "Couldn't create the TMDS clock\n");
-                return ret;
+                goto err_disable_mod_clk;
+        }
+
+        if (hdmi->variant->has_ddc_parent_clk) {
+                hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
+                if (IS_ERR(hdmi->ddc_parent_clk)) {
+                        dev_err(dev, "Couldn't get the HDMI DDC clock\n");
+                        return PTR_ERR(hdmi->ddc_parent_clk);
+                }
+        } else {
+                hdmi->ddc_parent_clk = hdmi->tmds_clk;
         }
 
         writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
 
-        writel(SUN4I_HDMI_PAD_CTRL0_TXEN | SUN4I_HDMI_PAD_CTRL0_CKEN |
-               SUN4I_HDMI_PAD_CTRL0_PWENG | SUN4I_HDMI_PAD_CTRL0_PWEND |
-               SUN4I_HDMI_PAD_CTRL0_PWENC | SUN4I_HDMI_PAD_CTRL0_LDODEN |
-               SUN4I_HDMI_PAD_CTRL0_LDOCEN | SUN4I_HDMI_PAD_CTRL0_BIASEN,
+        writel(hdmi->variant->pad_ctrl0_init_val,
                hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
 
-        /*
-         * We can't just initialize the register there, we need to
-         * protect the clock bits that have already been read out and
-         * cached by the clock framework.
-         */
-        reg = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
-        reg &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
-        reg |= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
-                SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
-                SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
-                SUN4I_HDMI_PAD_CTRL1_REG_DEN |
-                SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
-                SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
-                SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
-                SUN4I_HDMI_PAD_CTRL1_AMP_OPT;
-        writel(reg, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
-
         reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
         reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
-        reg |= SUN4I_HDMI_PLL_CTRL_VCO_S(8) | SUN4I_HDMI_PLL_CTRL_CS(7) |
-                SUN4I_HDMI_PLL_CTRL_CP_S(15) | SUN4I_HDMI_PLL_CTRL_S(7) |
-                SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | SUN4I_HDMI_PLL_CTRL_SDIV2 |
-                SUN4I_HDMI_PLL_CTRL_LDO2_EN | SUN4I_HDMI_PLL_CTRL_LDO1_EN |
-                SUN4I_HDMI_PLL_CTRL_HV_IS_33 | SUN4I_HDMI_PLL_CTRL_BWS |
-                SUN4I_HDMI_PLL_CTRL_PLL_EN;
+        reg |= hdmi->variant->pll_ctrl_init_val;
         writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 
         ret = sun4i_hdmi_i2c_create(dev, hdmi);
         if (ret) {
                 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
-                return ret;
+                goto err_disable_mod_clk;
         }
 
         drm_encoder_helper_add(&hdmi->encoder,
@@ -422,6 +573,12 @@ err_cleanup_connector:
         drm_encoder_cleanup(&hdmi->encoder);
 err_del_i2c_adapter:
         i2c_del_adapter(hdmi->i2c);
+err_disable_mod_clk:
+        clk_disable_unprepare(hdmi->mod_clk);
+err_disable_bus_clk:
+        clk_disable_unprepare(hdmi->bus_clk);
+err_assert_reset:
+        reset_control_assert(hdmi->reset);
         return ret;
 }
 
@@ -434,6 +591,8 @@ static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
         drm_connector_cleanup(&hdmi->connector);
         drm_encoder_cleanup(&hdmi->encoder);
         i2c_del_adapter(hdmi->i2c);
+        clk_disable_unprepare(hdmi->mod_clk);
+        clk_disable_unprepare(hdmi->bus_clk);
 }
 
 static const struct component_ops sun4i_hdmi_ops = {
@@ -454,7 +613,8 @@ static int sun4i_hdmi_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id sun4i_hdmi_of_table[] = {
-        { .compatible = "allwinner,sun5i-a10s-hdmi" },
+        { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
+        { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
         { }
 };
 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
index 2e42d09ab42e..58e9d37e8c17 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
@@ -25,8 +25,6 @@
 
 /* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */
 #define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX
-/* FIFO request bit is set when FIFO level is below TX_THRESHOLD during write */
-#define TX_THRESHOLD 1
 
 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
 {
@@ -39,27 +37,36 @@ static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
                          SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
                          SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE;
         u32 reg;
+        /*
+         * If threshold is inclusive, then the FIFO may only have
+         * RX_THRESHOLD number of bytes, instead of RX_THRESHOLD + 1.
+         */
+        int read_len = RX_THRESHOLD +
+                (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
 
-        /* Limit transfer length by FIFO threshold */
-        len = min_t(int, len, read ? (RX_THRESHOLD + 1) :
-                              (SUN4I_HDMI_DDC_FIFO_SIZE - TX_THRESHOLD + 1));
+        /*
+         * Limit transfer length by FIFO threshold or FIFO size.
+         * For TX the threshold is for an empty FIFO.
+         */
+        len = min_t(int, len, read ? read_len : SUN4I_HDMI_DDC_FIFO_SIZE);
 
         /* Wait until error, FIFO request bit set or transfer complete */
-        if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG, reg,
-                               reg & mask, len * byte_time_ns, 100000))
+        if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
+                                           reg & mask, len * byte_time_ns,
+                                           100000))
                 return -ETIMEDOUT;
 
         if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK)
                 return -EIO;
 
         if (read)
-                readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
+                readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
         else
-                writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
+                writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
 
-        /* Clear FIFO request bit */
-        writel(SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST,
-               hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
+        /* Clear FIFO request bit by forcing a write to that bit */
+        regmap_field_force_write(hdmi->field_ddc_int_status,
+                                 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST);
 
         return len;
 }
@@ -70,50 +77,52 @@ static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg)
         u32 reg;
 
         /* Set FIFO direction */
-        reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-        reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
-        reg |= (msg->flags & I2C_M_RD) ?
-               SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
-               SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
-        writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
+        if (hdmi->variant->ddc_fifo_has_dir) {
+                reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
+                reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
+                reg |= (msg->flags & I2C_M_RD) ?
+                       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
+                       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
+                writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
+        }
+
+        /* Clear address register (not cleared by soft reset) */
+        regmap_field_write(hdmi->field_ddc_addr_reg, 0);
 
         /* Set I2C address */
-        writel(SUN4I_HDMI_DDC_ADDR_SLAVE(msg->addr),
-               hdmi->base + SUN4I_HDMI_DDC_ADDR_REG);
-
-        /* Set FIFO RX/TX thresholds and clear FIFO */
-        reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
-        reg |= SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR;
-        reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK;
-        reg |= SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(RX_THRESHOLD);
-        reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK;
-        reg |= SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(TX_THRESHOLD);
-        writel(reg, hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
-        if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG,
-                               reg,
-                               !(reg & SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR),
-                               100, 2000))
+        regmap_field_write(hdmi->field_ddc_slave_addr, msg->addr);
+
+        /*
+         * Set FIFO RX/TX thresholds and clear FIFO
+         *
+         * If threshold is inclusive, we can set the TX threshold to
+         * 0 instead of 1.
+         */
+        regmap_field_write(hdmi->field_ddc_fifo_tx_thres,
+                           hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
+        regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD);
+        regmap_field_write(hdmi->field_ddc_fifo_clear, 1);
+        if (regmap_field_read_poll_timeout(hdmi->field_ddc_fifo_clear,
+                                           reg, !reg, 100, 2000))
                 return -EIO;
 
         /* Set transfer length */
-        writel(msg->len, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG);
+        regmap_field_write(hdmi->field_ddc_byte_count, msg->len);
 
         /* Set command */
-        writel(msg->flags & I2C_M_RD ?
-               SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
-               SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE,
-               hdmi->base + SUN4I_HDMI_DDC_CMD_REG);
+        regmap_field_write(hdmi->field_ddc_cmd,
+                           msg->flags & I2C_M_RD ?
+                           SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
+                           SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE);
 
-        /* Clear interrupt status bits */
-        writel(SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
-               SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
-               SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE,
-               hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
+        /* Clear interrupt status bits by forcing a write */
+        regmap_field_force_write(hdmi->field_ddc_int_status,
+                                 SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
+                                 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
+                                 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE);
 
         /* Start command */
-        reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-        writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD,
-               hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
+        regmap_field_write(hdmi->field_ddc_start, 1);
 
         /* Transfer bytes */
         for (i = 0; i < msg->len; i += len) {
@@ -124,14 +133,12 @@ static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg)
         }
 
         /* Wait for command to finish */
-        if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG,
-                               reg,
-                               !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD),
-                               100, 100000))
+        if (regmap_field_read_poll_timeout(hdmi->field_ddc_start,
+                                           reg, !reg, 100, 100000))
                 return -EIO;
 
         /* Check for errors */
-        reg = readl(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
+        regmap_field_read(hdmi->field_ddc_int_status, &reg);
         if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) ||
             !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) {
                 return -EIO;
@@ -154,20 +161,21 @@ static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap,
                         return -EINVAL;
         }
 
+        /* DDC clock needs to be enabled for the module to work */
+        clk_prepare_enable(hdmi->ddc_clk);
+        clk_set_rate(hdmi->ddc_clk, 100000);
+
         /* Reset I2C controller */
-        writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET,
-               hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-        if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg,
-                               !(reg & SUN4I_HDMI_DDC_CTRL_RESET),
-                               100, 2000))
+        regmap_field_write(hdmi->field_ddc_en, 1);
+        regmap_field_write(hdmi->field_ddc_reset, 1);
+        if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset,
+                                           reg, !reg, 100, 2000)) {
+                clk_disable_unprepare(hdmi->ddc_clk);
                 return -EIO;
+        }
 
-        writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE |
-               SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE,
-               hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG);
-
-        clk_prepare_enable(hdmi->ddc_clk);
-        clk_set_rate(hdmi->ddc_clk, 100000);
+        regmap_field_write(hdmi->field_ddc_sck_en, 1);
+        regmap_field_write(hdmi->field_ddc_sda_en, 1);
 
         for (i = 0; i < num; i++) {
                 err = xfer_msg(hdmi, &msgs[i]);
@@ -191,12 +199,105 @@ static const struct i2c_algorithm sun4i_hdmi_i2c_algorithm = {
         .functionality  = sun4i_hdmi_i2c_func,
 };
 
+static int sun4i_hdmi_init_regmap_fields(struct sun4i_hdmi *hdmi)
+{
+        hdmi->field_ddc_en =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_en);
+        if (IS_ERR(hdmi->field_ddc_en))
+                return PTR_ERR(hdmi->field_ddc_en);
+
+        hdmi->field_ddc_start =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_start);
+        if (IS_ERR(hdmi->field_ddc_start))
+                return PTR_ERR(hdmi->field_ddc_start);
+
+        hdmi->field_ddc_reset =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_reset);
+        if (IS_ERR(hdmi->field_ddc_reset))
+                return PTR_ERR(hdmi->field_ddc_reset);
+
+        hdmi->field_ddc_addr_reg =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_addr_reg);
+        if (IS_ERR(hdmi->field_ddc_addr_reg))
+                return PTR_ERR(hdmi->field_ddc_addr_reg);
+
+        hdmi->field_ddc_slave_addr =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_slave_addr);
+        if (IS_ERR(hdmi->field_ddc_slave_addr))
+                return PTR_ERR(hdmi->field_ddc_slave_addr);
+
+        hdmi->field_ddc_int_mask =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_int_mask);
+        if (IS_ERR(hdmi->field_ddc_int_mask))
+                return PTR_ERR(hdmi->field_ddc_int_mask);
+
+        hdmi->field_ddc_int_status =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_int_status);
+        if (IS_ERR(hdmi->field_ddc_int_status))
+                return PTR_ERR(hdmi->field_ddc_int_status);
+
+        hdmi->field_ddc_fifo_clear =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_fifo_clear);
+        if (IS_ERR(hdmi->field_ddc_fifo_clear))
+                return PTR_ERR(hdmi->field_ddc_fifo_clear);
+
+        hdmi->field_ddc_fifo_rx_thres =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_fifo_rx_thres);
+        if (IS_ERR(hdmi->field_ddc_fifo_rx_thres))
+                return PTR_ERR(hdmi->field_ddc_fifo_rx_thres);
+
+        hdmi->field_ddc_fifo_tx_thres =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_fifo_tx_thres);
+        if (IS_ERR(hdmi->field_ddc_fifo_tx_thres))
+                return PTR_ERR(hdmi->field_ddc_fifo_tx_thres);
+
+        hdmi->field_ddc_byte_count =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_byte_count);
+        if (IS_ERR(hdmi->field_ddc_byte_count))
+                return PTR_ERR(hdmi->field_ddc_byte_count);
+
+        hdmi->field_ddc_cmd =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_cmd);
+        if (IS_ERR(hdmi->field_ddc_cmd))
+                return PTR_ERR(hdmi->field_ddc_cmd);
+
+        hdmi->field_ddc_sda_en =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_sda_en);
+        if (IS_ERR(hdmi->field_ddc_sda_en))
+                return PTR_ERR(hdmi->field_ddc_sda_en);
+
+        hdmi->field_ddc_sck_en =
+                devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
+                                        hdmi->variant->field_ddc_sck_en);
+        if (IS_ERR(hdmi->field_ddc_sck_en))
+                return PTR_ERR(hdmi->field_ddc_sck_en);
+
+        return 0;
+}
+
 int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi)
 {
         struct i2c_adapter *adap;
         int ret = 0;
 
-        ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
+        ret = sun4i_ddc_create(hdmi, hdmi->ddc_parent_clk);
+        if (ret)
+                return ret;
+
+        ret = sun4i_hdmi_init_regmap_fields(hdmi);
         if (ret)
                 return ret;
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5cf2527bffc8..1b6b37aefc38 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -18,6 +18,8 @@
 struct sun4i_tmds {
         struct clk_hw           hw;
         struct sun4i_hdmi       *hdmi;
+
+        u8                      div_offset;
 };
 
 static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
@@ -28,6 +30,7 @@ static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
 
 static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
                                              unsigned long parent_rate,
+                                             u8 div_offset,
                                              u8 *div,
                                              bool *half)
 {
@@ -35,7 +38,7 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
         u8 best_m = 0, m;
         bool is_double;
 
-        for (m = 1; m < 16; m++) {
+        for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
                 u8 d;
 
                 for (d = 1; d < 3; d++) {
@@ -67,11 +70,12 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
 static int sun4i_tmds_determine_rate(struct clk_hw *hw,
                                      struct clk_rate_request *req)
 {
-        struct clk_hw *parent;
+        struct sun4i_tmds *tmds = hw_to_tmds(hw);
+        struct clk_hw *parent = NULL;
         unsigned long best_parent = 0;
         unsigned long rate = req->rate;
         int best_div = 1, best_half = 1;
-        int i, j;
+        int i, j, p;
 
         /*
          * We only consider PLL3, since the TCON is very likely to be
@@ -79,32 +83,38 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
          * clock, so we should not need to do anything.
          */
 
-        parent = clk_hw_get_parent_by_index(hw, 0);
-        if (!parent)
-                return -EINVAL;
-
-        for (i = 1; i < 3; i++) {
-                for (j = 1; j < 16; j++) {
-                        unsigned long ideal = rate * i * j;
-                        unsigned long rounded;
-
-                        rounded = clk_hw_round_rate(parent, ideal);
-
-                        if (rounded == ideal) {
-                                best_parent = rounded;
-                                best_half = i;
-                                best_div = j;
-                                goto out;
-                        }
-
-                        if (abs(rate - rounded / i) <
-                            abs(rate - best_parent / best_div)) {
-                                best_parent = rounded;
-                                best_div = i;
+        for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
+                parent = clk_hw_get_parent_by_index(hw, p);
+                if (!parent)
+                        continue;
+
+                for (i = 1; i < 3; i++) {
+                        for (j = tmds->div_offset ?: 1;
+                             j < (16 + tmds->div_offset); j++) {
+                                unsigned long ideal = rate * i * j;
+                                unsigned long rounded;
+
+                                rounded = clk_hw_round_rate(parent, ideal);
+
+                                if (rounded == ideal) {
+                                        best_parent = rounded;
+                                        best_half = i;
+                                        best_div = j;
+                                        goto out;
+                                }
+
+                                if (abs(rate - rounded / i) <
+                                    abs(rate - best_parent / best_div)) {
+                                        best_parent = rounded;
+                                        best_div = i;
+                                }
                         }
                 }
         }
 
+        if (!parent)
+                return -EINVAL;
+
 out:
         req->rate = best_parent / best_half / best_div;
         req->best_parent_rate = best_parent;
@@ -124,7 +134,7 @@ static unsigned long sun4i_tmds_recalc_rate(struct clk_hw *hw,
                 parent_rate /= 2;
 
         reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
-        reg = (reg >> 4) & 0xf;
+        reg = ((reg >> 4) & 0xf) + tmds->div_offset;
         if (!reg)
                 reg = 1;
 
@@ -139,7 +149,8 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned long rate,
         u32 reg;
         u8 div;
 
-        sun4i_tmds_calc_divider(rate, parent_rate, &div, &half);
+        sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
+                                &div, &half);
 
         reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
         reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
@@ -149,7 +160,7 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned long rate,
 
         reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
         reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
-        writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div),
+        writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
                tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 
         return 0;
@@ -216,6 +227,7 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 
         tmds->hdmi = hdmi;
         tmds->hw.init = &init;
+        tmds->div_offset = hdmi->variant->tmds_clk_div_offset;
 
         hdmi->tmds_clk = devm_clk_register(hdmi->dev, &tmds->hw);
         if (IS_ERR(hdmi->tmds_clk))
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index e853dfe51389..68751b999877 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -14,9 +14,12 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder.h>
 #include <drm/drm_modes.h>
 #include <drm/drm_of.h>
 
+#include <uapi/drm/drm_mode.h>
+
 #include <linux/component.h>
 #include <linux/ioport.h>
 #include <linux/of_address.h>
@@ -109,26 +112,37 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 }
 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 
-void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
-                        struct drm_encoder *encoder)
+/*
+ * This function is a helper for TCON output muxing. The TCON output
+ * muxing control register in earlier SoCs (without the TCON TOP block)
+ * are located in TCON0. This helper returns a pointer to TCON0's
+ * sun4i_tcon structure, or NULL if not found.
+ */
+static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
 {
-        u32 val;
+        struct sun4i_drv *drv = drm->dev_private;
+        struct sun4i_tcon *tcon;
 
-        if (!tcon->quirks->has_unknown_mux)
-                return;
+        list_for_each_entry(tcon, &drv->tcon_list, list)
+                if (tcon->id == 0)
+                        return tcon;
 
-        if (channel != 1)
-                return;
+        dev_warn(drm->dev,
+                 "TCON0 not found, display output muxing may not work\n");
 
-        if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
-                val = 1;
-        else
-                val = 0;
+        return NULL;
+}
 
-        /*
-         * FIXME: Undocumented bits
-         */
-        regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
+void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
+                        struct drm_encoder *encoder)
+{
+        int ret = -ENOTSUPP;
+
+        if (tcon->quirks->set_mux)
+                ret = tcon->quirks->set_mux(tcon, encoder);
+
+        DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
+                         encoder->name, encoder->crtc->name, ret);
 }
 EXPORT_SYMBOL(sun4i_tcon_set_mux);
 
@@ -767,14 +781,57 @@ static int sun4i_tcon_remove(struct platform_device *pdev)
         return 0;
 }
 
+/* platform specific TCON muxing callbacks */
+static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
+                                  struct drm_encoder *encoder)
+{
+        u32 val;
+
+        if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
+                val = 1;
+        else
+                val = 0;
+
+        /*
+         * FIXME: Undocumented bits
+         */
+        return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
+}
+
+static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
+                              struct drm_encoder *encoder)
+{
+        struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
+        u32 shift;
+
+        if (!tcon0)
+                return -EINVAL;
+
+        switch (encoder->encoder_type) {
+        case DRM_MODE_ENCODER_TMDS:
+                /* HDMI */
+                shift = 8;
+                break;
+        default:
+                /* TODO A31 has MIPI DSI but A31s does not */
+                return -EINVAL;
+        }
+
+        regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
+                           0x3 << shift, tcon->id << shift);
+
+        return 0;
+}
+
 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
-        .has_unknown_mux = true,
-        .has_channel_1  = true,
+        .has_channel_1          = true,
+        .set_mux                = sun5i_a13_tcon_set_mux,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
         .has_channel_1          = true,
         .needs_de_be_mux        = true,
+        .set_mux                = sun6i_tcon_set_mux,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 5a219d1ccc26..d9e1357cc8ae 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -145,10 +145,14 @@
 
 #define SUN4I_TCON_MAX_CHANNELS         2
 
+struct sun4i_tcon;
+
 struct sun4i_tcon_quirks {
-        bool    has_unknown_mux; /* sun5i has undocumented mux */
         bool    has_channel_1;  /* a33 does not have channel 1 */
         bool    needs_de_be_mux; /* sun6i needs mux to select backend */
+
+        /* callback to handle tcon muxing options */
+        int     (*set_mux)(struct sun4i_tcon *, struct drm_encoder *);
 };
 
 struct sun4i_tcon {
diff --git a/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c b/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
index fc447c9a1a27..f41fc506ff87 100644
--- a/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
+++ b/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
@@ -51,7 +51,6 @@ static int tinydrm_connector_get_modes(struct drm_connector *connector)
 
 static const struct drm_connector_helper_funcs tinydrm_connector_hfuncs = {
         .get_modes = tinydrm_connector_get_modes,
-        .best_encoder = drm_atomic_helper_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/tinydrm/mi0283qt.c b/drivers/gpu/drm/tinydrm/mi0283qt.c
index 7fd26912f2ba..6a83b3093254 100644
--- a/drivers/gpu/drm/tinydrm/mi0283qt.c
+++ b/drivers/gpu/drm/tinydrm/mi0283qt.c
@@ -31,7 +31,7 @@ static int mi0283qt_init(struct mipi_dbi *mipi)
 
         ret = regulator_enable(mipi->regulator);
         if (ret) {
-                dev_err(dev, "Failed to enable regulator %d\n", ret);
+                DRM_DEV_ERROR(dev, "Failed to enable regulator %d\n", ret);
                 return ret;
         }
 
@@ -42,7 +42,7 @@ static int mi0283qt_init(struct mipi_dbi *mipi)
         mipi_dbi_hw_reset(mipi);
         ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
         if (ret) {
-                dev_err(dev, "Error sending command %d\n", ret);
+                DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
                 regulator_disable(mipi->regulator);
                 return ret;
         }
@@ -174,13 +174,13 @@ static int mi0283qt_probe(struct spi_device *spi)
 
         mipi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
         if (IS_ERR(mipi->reset)) {
-                dev_err(dev, "Failed to get gpio 'reset'\n");
+                DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
                 return PTR_ERR(mipi->reset);
         }
 
         dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
         if (IS_ERR(dc)) {
-                dev_err(dev, "Failed to get gpio 'dc'\n");
+                DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
                 return PTR_ERR(dc);
         }
 
diff --git a/drivers/gpu/drm/tinydrm/repaper.c b/drivers/gpu/drm/tinydrm/repaper.c
index 340198f5afea..75740630c410 100644
--- a/drivers/gpu/drm/tinydrm/repaper.c
+++ b/drivers/gpu/drm/tinydrm/repaper.c
@@ -474,8 +474,7 @@ static void repaper_get_temperature(struct repaper_epd *epd)
 
         ret = thermal_zone_get_temp(epd->thermal, &temperature);
         if (ret) {
-                dev_err(&epd->spi->dev, "Failed to get temperature (%d)\n",
-                        ret);
+                DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
                 return;
         }
 
@@ -630,7 +629,7 @@ out_unlock:
         mutex_unlock(&tdev->dirty_lock);
 
         if (ret)
-                dev_err(fb->dev->dev, "Failed to update display (%d)\n", ret);
+                DRM_DEV_ERROR(fb->dev->dev, "Failed to update display (%d)\n", ret);
         kfree(buf);
 
         return ret;
@@ -704,7 +703,7 @@ static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
         }
 
         if (!i) {
-                dev_err(dev, "timeout waiting for panel to become ready.\n");
+                DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
                 power_off(epd);
                 return;
         }
@@ -726,9 +725,9 @@ static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
         ret = repaper_read_val(spi, 0x0f);
         if (ret < 0 || !(ret & 0x80)) {
                 if (ret < 0)
-                        dev_err(dev, "failed to read chip (%d)\n", ret);
+                        DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
                 else
-                        dev_err(dev, "panel is reported broken\n");
+                        DRM_DEV_ERROR(dev, "panel is reported broken\n");
                 power_off(epd);
                 return;
         }
@@ -768,7 +767,7 @@ static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
                 /* check DC/DC */
                 ret = repaper_read_val(spi, 0x0f);
                 if (ret < 0) {
-                        dev_err(dev, "failed to read chip (%d)\n", ret);
+                        DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
                         power_off(epd);
                         return;
                 }
@@ -780,7 +779,7 @@ static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
         }
 
         if (!dc_ok) {
-                dev_err(dev, "dc/dc failed\n");
+                DRM_DEV_ERROR(dev, "dc/dc failed\n");
                 power_off(epd);
                 return;
         }
@@ -960,7 +959,7 @@ static int repaper_probe(struct spi_device *spi)
         if (IS_ERR(epd->panel_on)) {
                 ret = PTR_ERR(epd->panel_on);
                 if (ret != -EPROBE_DEFER)
-                        dev_err(dev, "Failed to get gpio 'panel-on'\n");
+                        DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
                 return ret;
         }
 
@@ -968,7 +967,7 @@ static int repaper_probe(struct spi_device *spi)
         if (IS_ERR(epd->discharge)) {
                 ret = PTR_ERR(epd->discharge);
                 if (ret != -EPROBE_DEFER)
-                        dev_err(dev, "Failed to get gpio 'discharge'\n");
+                        DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
                 return ret;
         }
 
@@ -976,7 +975,7 @@ static int repaper_probe(struct spi_device *spi)
         if (IS_ERR(epd->reset)) {
                 ret = PTR_ERR(epd->reset);
                 if (ret != -EPROBE_DEFER)
-                        dev_err(dev, "Failed to get gpio 'reset'\n");
+                        DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
                 return ret;
         }
 
@@ -984,7 +983,7 @@ static int repaper_probe(struct spi_device *spi)
         if (IS_ERR(epd->busy)) {
                 ret = PTR_ERR(epd->busy);
                 if (ret != -EPROBE_DEFER)
-                        dev_err(dev, "Failed to get gpio 'busy'\n");
+                        DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
                 return ret;
         }
 
@@ -992,8 +991,7 @@ static int repaper_probe(struct spi_device *spi)
                                          &thermal_zone)) {
                 epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
                 if (IS_ERR(epd->thermal)) {
-                        dev_err(dev, "Failed to get thermal zone: %s\n",
-                                thermal_zone);
+                        DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
                         return PTR_ERR(epd->thermal);
                 }
         }
@@ -1034,7 +1032,7 @@ static int repaper_probe(struct spi_device *spi)
                 if (IS_ERR(epd->border)) {
                         ret = PTR_ERR(epd->border);
                         if (ret != -EPROBE_DEFER)
-                                dev_err(dev, "Failed to get gpio 'border'\n");
+                                DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
                         return ret;
                 }
 
diff --git a/drivers/gpu/drm/tinydrm/st7586.c b/drivers/gpu/drm/tinydrm/st7586.c
index da9c0d83045f..0a2c60da5c0e 100644
--- a/drivers/gpu/drm/tinydrm/st7586.c
+++ b/drivers/gpu/drm/tinydrm/st7586.c
@@ -188,7 +188,7 @@ static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
         mipi_dbi_hw_reset(mipi);
         ret = mipi_dbi_command(mipi, ST7586_AUTO_READ_CTRL, 0x9f);
         if (ret) {
-                dev_err(dev, "Error sending command %d\n", ret);
+                DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
                 return;
         }
 
@@ -355,13 +355,13 @@ static int st7586_probe(struct spi_device *spi)
 
         mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
         if (IS_ERR(mipi->reset)) {
-                dev_err(dev, "Failed to get gpio 'reset'\n");
+                DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
                 return PTR_ERR(mipi->reset);
         }
 
         a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW);
         if (IS_ERR(a0)) {
-                dev_err(dev, "Failed to get gpio 'a0'\n");
+                DRM_DEV_ERROR(dev, "Failed to get gpio 'a0'\n");
                 return PTR_ERR(a0);
         }
 
diff --git a/drivers/gpu/drm/udl/udl_connector.c b/drivers/gpu/drm/udl/udl_connector.c
index 9f9a49748d17..091ca81658eb 100644
--- a/drivers/gpu/drm/udl/udl_connector.c
+++ b/drivers/gpu/drm/udl/udl_connector.c
@@ -105,7 +105,7 @@ static struct drm_encoder*
 udl_best_single_encoder(struct drm_connector *connector)
 {
         int enc_id = connector->encoder_ids[0];
-        return drm_encoder_find(connector->dev, enc_id);
+        return drm_encoder_find(connector->dev, NULL, enc_id);
 }
 
 static int udl_connector_set_property(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index 519cefef800d..72c9dbd81d7f 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -97,8 +97,6 @@ struct vc4_dpi {
 
         struct drm_encoder *encoder;
         struct drm_connector *connector;
-        struct drm_bridge *bridge;
-        bool is_panel_bridge;
 
         void __iomem *regs;
 
@@ -251,10 +249,11 @@ static int vc4_dpi_init_bridge(struct vc4_dpi *dpi)
 {
         struct device *dev = &dpi->pdev->dev;
         struct drm_panel *panel;
+        struct drm_bridge *bridge;
         int ret;
 
         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
-                                          &panel, &dpi->bridge);
+                                          &panel, &bridge);
         if (ret) {
                 /* If nothing was connected in the DT, that's not an
                  * error.
@@ -265,13 +264,10 @@ static int vc4_dpi_init_bridge(struct vc4_dpi *dpi)
                         return ret;
         }
 
-        if (panel) {
-                dpi->bridge = drm_panel_bridge_add(panel,
-                                                   DRM_MODE_CONNECTOR_DPI);
-                dpi->is_panel_bridge = true;
-        }
+        if (panel)
+                bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
 
-        return drm_bridge_attach(dpi->encoder, dpi->bridge, NULL);
+        return drm_bridge_attach(dpi->encoder, bridge, NULL);
 }
 
 static int vc4_dpi_bind(struct device *dev, struct device *master, void *data)
@@ -352,8 +348,7 @@ static void vc4_dpi_unbind(struct device *dev, struct device *master,
         struct vc4_dev *vc4 = to_vc4_dev(drm);
         struct vc4_dpi *dpi = dev_get_drvdata(dev);
 
-        if (dpi->is_panel_bridge)
-                drm_panel_bridge_remove(dpi->bridge);
+        drm_of_panel_bridge_remove(dev->of_node, 0, 0);
 
         drm_encoder_cleanup(dpi->encoder);
 
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 925c726ac694..554605af344e 100644
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
         pll_clock = parent_rate / divider;
         pixel_clock_hz = pll_clock / dsi->divider;
 
-        /* Round up the clk_set_rate() request slightly, since
-         * PLLD_DSI1 is an integer divider and its rate selection will
-         * never round up.
-         */
-        adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
+        adjusted_mode->clock = pixel_clock_hz / 1000;
 
         /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
         adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
@@ -901,7 +897,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
                 vc4_dsi_dump_regs(dsi);
         }
 
-        phy_clock = pixel_clock_hz * dsi->divider;
+        /* Round up the clk_set_rate() request slightly, since
+         * PLLD_DSI1 is an integer divider and its rate selection will
+         * never round up.
+         */
+        phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
         ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
         if (ret) {
                 dev_err(&dsi->pdev->dev,
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 2968b3ebb895..3a767a038f72 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -547,14 +547,24 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
                 tiling = SCALER_CTL0_TILING_LINEAR;
                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
                 break;
-        case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
+
+        case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
+                /* For T-tiled, the FB pitch is "how many bytes from
+                 * one row to the next, such that pitch * tile_h ==
+                 * tile_size * tiles_per_row."
+                 */
+                u32 tile_size_shift = 12; /* T tiles are 4kb */
+                u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
+                u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
+
                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 
-                pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
-                          VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
-                          VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
-                                        SCALER_PITCH0_TILE_WIDTH_R));
+                pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
+                          VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
+                          VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
                 break;
+        }
+
         default:
                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
                               (long long)fb->modifier);
diff --git a/drivers/gpu/drm/via/via_verifier.c b/drivers/gpu/drm/via/via_verifier.c
index 0677bbf4ec7e..fb2609434df7 100644
--- a/drivers/gpu/drm/via/via_verifier.c
+++ b/drivers/gpu/drm/via/via_verifier.c
@@ -34,6 +34,7 @@
 #include <drm/drm_legacy.h>
 #include "via_verifier.h"
 #include "via_drv.h"
+#include <linux/kernel.h>
 
 typedef enum {
         state_command,
@@ -1102,10 +1103,7 @@ setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
 
 void via_init_command_verifier(void)
 {
-        setup_hazard_table(init_table1, table1,
-                           sizeof(init_table1) / sizeof(hz_init_t));
-        setup_hazard_table(init_table2, table2,
-                           sizeof(init_table2) / sizeof(hz_init_t));
-        setup_hazard_table(init_table3, table3,
-                           sizeof(init_table3) / sizeof(hz_init_t));
+        setup_hazard_table(init_table1, table1, ARRAY_SIZE(init_table1));
+        setup_hazard_table(init_table2, table2, ARRAY_SIZE(init_table2));
+        setup_hazard_table(init_table3, table3, ARRAY_SIZE(init_table3));
 }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 5ec24fd801cd..01be355525e4 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -286,7 +286,7 @@ int vmw_present_ioctl(struct drm_device *dev, void *data,
 
         drm_modeset_lock_all(dev);
 
-        fb = drm_framebuffer_lookup(dev, arg->fb_id);
+        fb = drm_framebuffer_lookup(dev, file_priv, arg->fb_id);
         if (!fb) {
                 DRM_ERROR("Invalid framebuffer id.\n");
                 ret = -ENOENT;
@@ -369,7 +369,7 @@ int vmw_present_readback_ioctl(struct drm_device *dev, void *data,
 
         drm_modeset_lock_all(dev);
 
-        fb = drm_framebuffer_lookup(dev, arg->fb_id);
+        fb = drm_framebuffer_lookup(dev, file_priv, arg->fb_id);
         if (!fb) {
                 DRM_ERROR("Invalid framebuffer id.\n");
                 ret = -ENOENT;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index b850562fbdd6..0545740b3724 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1726,7 +1726,7 @@ int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
                 return 0;
         }
 
-        crtc = drm_crtc_find(dev, arg->crtc_id);
+        crtc = drm_crtc_find(dev, file_priv, arg->crtc_id);
         if (!crtc) {
                 ret = -ENOENT;
                 goto out;
diff --git a/drivers/media/v4l2-core/videobuf2-dma-contig.c b/drivers/media/v4l2-core/videobuf2-dma-contig.c
index 9f389f36566d..a9806ba6116d 100644
--- a/drivers/media/v4l2-core/videobuf2-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf2-dma-contig.c
@@ -479,7 +479,7 @@ static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr,
 {
         struct vb2_dc_buf *buf;
         struct frame_vector *vec;
-        unsigned long offset;
+        unsigned int offset;
         int n_pages, i;
         int ret = 0;
         struct sg_table *sgt;
@@ -507,7 +507,7 @@ static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr,
         buf->dev = dev;
         buf->dma_dir = dma_dir;
 
-        offset = vaddr & ~PAGE_MASK;
+        offset = lower_32_bits(offset_in_page(vaddr));
         vec = vb2_create_framevec(vaddr, size, dma_dir == DMA_FROM_DEVICE ||
                                                dma_dir == DMA_BIDIRECTIONAL);
         if (IS_ERR(vec)) {
diff --git a/drivers/rapidio/devices/rio_mport_cdev.c b/drivers/rapidio/devices/rio_mport_cdev.c
index 5beb0c361076..5c1b6388122a 100644
--- a/drivers/rapidio/devices/rio_mport_cdev.c
+++ b/drivers/rapidio/devices/rio_mport_cdev.c
@@ -876,10 +876,10 @@ rio_dma_transfer(struct file *filp, u32 transfer_mode,
          * offset within the internal buffer specified by handle parameter.
          */
         if (xfer->loc_addr) {
-                unsigned long offset;
+                unsigned int offset;
                 long pinned;
 
-                offset = (unsigned long)(uintptr_t)xfer->loc_addr & ~PAGE_MASK;
+                offset = lower_32_bits(offset_in_page(xfer->loc_addr));
                 nr_pages = PAGE_ALIGN(xfer->length + offset) >> PAGE_SHIFT;
 
                 page_list = kmalloc_array(nr_pages,
diff --git a/drivers/staging/vboxvideo/vbox_mode.c b/drivers/staging/vboxvideo/vbox_mode.c
index 257a77830410..c745a0402c68 100644
--- a/drivers/staging/vboxvideo/vbox_mode.c
+++ b/drivers/staging/vboxvideo/vbox_mode.c
@@ -377,7 +377,7 @@ static struct drm_encoder *vbox_best_single_encoder(struct drm_connector
 
         /* pick the encoder ids */
         if (enc_id)
-                return drm_encoder_find(connector->dev, enc_id);
+                return drm_encoder_find(connector->dev, NULL, enc_id);
 
         return NULL;
 }
diff --git a/include/drm/bridge/mhl.h b/include/drm/bridge/mhl.h
index fbdfc8d7f3c7..96a5e0f6ff12 100644
--- a/include/drm/bridge/mhl.h
+++ b/include/drm/bridge/mhl.h
@@ -262,6 +262,10 @@ enum {
 #define MHL_RAPK_UNSUPPORTED    0x02    /* Rcvd RAP action code not supported */
 #define MHL_RAPK_BUSY           0x03    /* Responder too busy to respond */
 
+/* Bit masks for RCP messages */
+#define MHL_RCP_KEY_RELEASED_MASK       0x80
+#define MHL_RCP_KEY_ID_MASK             0x7F
+
 /*
  * Error status codes for RCPE messages
  */
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 5834580d75bc..5afd6e364fb6 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -585,12 +585,12 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_oldnew_connector_in_state(__state, connector, old_connector_state, new_connector_state, __i) \
         for ((__i) = 0;                                                         \
-             (__i) < (__state)->num_connector &&                                \
-             ((connector) = (__state)->connectors[__i].ptr,                     \
-             (old_connector_state) = (__state)->connectors[__i].old_state,      \
-             (new_connector_state) = (__state)->connectors[__i].new_state, 1);  \
-             (__i)++)                                                   \
-                for_each_if (connector)
+             (__i) < (__state)->num_connector;                                  \
+             (__i)++)                                                           \
+                for_each_if ((__state)->connectors[__i].ptr &&                  \
+                             ((connector) = (__state)->connectors[__i].ptr,     \
+                             (old_connector_state) = (__state)->connectors[__i].old_state,      \
+                             (new_connector_state) = (__state)->connectors[__i].new_state, 1))
 
 /**
  * for_each_old_connector_in_state - iterate over all connectors in an atomic update
@@ -606,11 +606,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_old_connector_in_state(__state, connector, old_connector_state, __i) \
         for ((__i) = 0;                                                         \
-             (__i) < (__state)->num_connector &&                                \
-             ((connector) = (__state)->connectors[__i].ptr,                     \
-             (old_connector_state) = (__state)->connectors[__i].old_state, 1);  \
-             (__i)++)                                                   \
-                for_each_if (connector)
+             (__i) < (__state)->num_connector;                                  \
+             (__i)++)                                                           \
+                for_each_if ((__state)->connectors[__i].ptr &&                  \
+                             ((connector) = (__state)->connectors[__i].ptr,     \
+                             (old_connector_state) = (__state)->connectors[__i].old_state, 1))
 
 /**
  * for_each_new_connector_in_state - iterate over all connectors in an atomic update
@@ -626,11 +626,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_new_connector_in_state(__state, connector, new_connector_state, __i) \
         for ((__i) = 0;                                                         \
-             (__i) < (__state)->num_connector &&                                \
-             ((connector) = (__state)->connectors[__i].ptr,                     \
-             (new_connector_state) = (__state)->connectors[__i].new_state, 1);  \
-             (__i)++)                                                   \
-                for_each_if (connector)
+             (__i) < (__state)->num_connector;                                  \
+             (__i)++)                                                           \
+                for_each_if ((__state)->connectors[__i].ptr &&                  \
+                             ((connector) = (__state)->connectors[__i].ptr,     \
+                             (new_connector_state) = (__state)->connectors[__i].new_state, 1))
 
 /**
  * for_each_oldnew_crtc_in_state - iterate over all CRTCs in an atomic update
@@ -646,12 +646,12 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_oldnew_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_crtc &&            \
-             ((crtc) = (__state)->crtcs[__i].ptr,                       \
-             (old_crtc_state) = (__state)->crtcs[__i].old_state,        \
-             (new_crtc_state) = (__state)->crtcs[__i].new_state, 1);    \
+             (__i) < (__state)->dev->mode_config.num_crtc;              \
              (__i)++)                                                   \
-                for_each_if (crtc)
+                for_each_if ((__state)->crtcs[__i].ptr &&               \
+                             ((crtc) = (__state)->crtcs[__i].ptr,       \
+                             (old_crtc_state) = (__state)->crtcs[__i].old_state, \
+                             (new_crtc_state) = (__state)->crtcs[__i].new_state, 1))
 
 /**
  * for_each_old_crtc_in_state - iterate over all CRTCs in an atomic update
@@ -666,11 +666,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_old_crtc_in_state(__state, crtc, old_crtc_state, __i)  \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_crtc &&            \
-             ((crtc) = (__state)->crtcs[__i].ptr,                       \
-             (old_crtc_state) = (__state)->crtcs[__i].old_state, 1);    \
+             (__i) < (__state)->dev->mode_config.num_crtc;              \
              (__i)++)                                                   \
-                for_each_if (crtc)
+                for_each_if ((__state)->crtcs[__i].ptr &&               \
+                             ((crtc) = (__state)->crtcs[__i].ptr,       \
+                             (old_crtc_state) = (__state)->crtcs[__i].old_state, 1))
 
 /**
  * for_each_new_crtc_in_state - iterate over all CRTCs in an atomic update
@@ -685,11 +685,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_new_crtc_in_state(__state, crtc, new_crtc_state, __i)  \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_crtc &&            \
-             ((crtc) = (__state)->crtcs[__i].ptr,                       \
-             (new_crtc_state) = (__state)->crtcs[__i].new_state, 1);    \
+             (__i) < (__state)->dev->mode_config.num_crtc;              \
              (__i)++)                                                   \
-                for_each_if (crtc)
+                for_each_if ((__state)->crtcs[__i].ptr &&               \
+                             ((crtc) = (__state)->crtcs[__i].ptr,       \
+                             (new_crtc_state) = (__state)->crtcs[__i].new_state, 1))
 
 /**
  * for_each_oldnew_plane_in_state - iterate over all planes in an atomic update
@@ -705,12 +705,12 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_oldnew_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_total_plane &&     \
-             ((plane) = (__state)->planes[__i].ptr,                     \
-             (old_plane_state) = (__state)->planes[__i].old_state,      \
-             (new_plane_state) = (__state)->planes[__i].new_state, 1);  \
+             (__i) < (__state)->dev->mode_config.num_total_plane;       \
              (__i)++)                                                   \
-                for_each_if (plane)
+                for_each_if ((__state)->planes[__i].ptr &&              \
+                             ((plane) = (__state)->planes[__i].ptr,     \
+                              (old_plane_state) = (__state)->planes[__i].old_state,\
+                              (new_plane_state) = (__state)->planes[__i].new_state, 1))
 
 /**
  * for_each_old_plane_in_state - iterate over all planes in an atomic update
@@ -725,12 +725,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_old_plane_in_state(__state, plane, old_plane_state, __i) \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_total_plane &&     \
-             ((plane) = (__state)->planes[__i].ptr,                     \
-             (old_plane_state) = (__state)->planes[__i].old_state, 1);  \
+             (__i) < (__state)->dev->mode_config.num_total_plane;       \
              (__i)++)                                                   \
-                for_each_if (plane)
-
+                for_each_if ((__state)->planes[__i].ptr &&              \
+                             ((plane) = (__state)->planes[__i].ptr,     \
+                              (old_plane_state) = (__state)->planes[__i].old_state, 1))
 /**
  * for_each_new_plane_in_state - iterate over all planes in an atomic update
  * @__state: &struct drm_atomic_state pointer
@@ -744,11 +743,11 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
  */
 #define for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \
         for ((__i) = 0;                                                 \
-             (__i) < (__state)->dev->mode_config.num_total_plane &&     \
-             ((plane) = (__state)->planes[__i].ptr,                     \
-             (new_plane_state) = (__state)->planes[__i].new_state, 1);  \
+             (__i) < (__state)->dev->mode_config.num_total_plane;       \
              (__i)++)                                                   \
-                for_each_if (plane)
+                for_each_if ((__state)->planes[__i].ptr &&              \
+                             ((plane) = (__state)->planes[__i].ptr,     \
+                              (new_plane_state) = (__state)->planes[__i].new_state, 1))
 
 /**
  * for_each_oldnew_private_obj_in_state - iterate over all private objects in an atomic update
@@ -768,8 +767,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
                      ((obj) = (__state)->private_objs[__i].ptr, \
                       (old_obj_state) = (__state)->private_objs[__i].old_state, \
                       (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \
-             (__i)++) \
-                for_each_if (obj)
+             (__i)++)
 
 /**
  * for_each_old_private_obj_in_state - iterate over all private objects in an atomic update
@@ -787,8 +785,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
              (__i) < (__state)->num_private_objs && \
                      ((obj) = (__state)->private_objs[__i].ptr, \
                       (old_obj_state) = (__state)->private_objs[__i].old_state, 1); \
-             (__i)++) \
-                for_each_if (obj)
+             (__i)++)
 
 /**
  * for_each_new_private_obj_in_state - iterate over all private objects in an atomic update
@@ -806,8 +803,7 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
              (__i) < (__state)->num_private_objs && \
                      ((obj) = (__state)->private_objs[__i].ptr, \
                       (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \
-             (__i)++) \
-                for_each_if (obj)
+             (__i)++)
 
 /**
  * drm_atomic_crtc_needs_modeset - compute combined modeset need
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index b34904dc8b9b..b4285c40e1e4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -939,10 +939,11 @@ static inline unsigned drm_connector_index(struct drm_connector *connector)
  * add takes a reference to it.
  */
 static inline struct drm_connector *drm_connector_lookup(struct drm_device *dev,
+                struct drm_file *file_priv,
                 uint32_t id)
 {
         struct drm_mode_object *mo;
-        mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CONNECTOR);
+        mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CONNECTOR);
         return mo ? obj_to_connector(mo) : NULL;
 }
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 80c97210eda5..f7fcceef46d9 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -959,10 +959,11 @@ struct drm_crtc *drm_crtc_from_index(struct drm_device *dev, int idx);
  * userspace interface should be done using &drm_property.
  */
 static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
-        uint32_t id)
+                struct drm_file *file_priv,
+                uint32_t id)
 {
         struct drm_mode_object *mo;
-        mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CRTC);
+        mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CRTC);
         return mo ? obj_to_crtc(mo) : NULL;
 }
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3123988e819b..2623a1255481 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -752,6 +752,12 @@
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+#define DP_SYNCHRONIZATION_LATENCY_IN_SINK              0x2009 /* edp 1.4 */
+# define DP_MAX_RESYNC_FRAME_COUNT_MASK                 (0xf << 0)
+# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT                0
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK    (0xf << 4)
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT   4
+
 #define DP_RECEIVER_ALPM_STATUS             0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR         (1 << 0)
 
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index ee06ecd6c01f..412e83a4d3db 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -324,7 +324,7 @@ struct drm_driver {
          */
         bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe,
                                      int *max_error,
-                                     struct timeval *vblank_time,
+                                     ktime_t *vblank_time,
                                      bool in_vblank_irq);
 
         /**
diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h
index 8d8245ec0181..86db0da8bdcb 100644
--- a/include/drm/drm_encoder.h
+++ b/include/drm/drm_encoder.h
@@ -214,11 +214,12 @@ static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
  * drm_mode_object_find().
  */
 static inline struct drm_encoder *drm_encoder_find(struct drm_device *dev,
+                                                   struct drm_file *file_priv,
                                                    uint32_t id)
 {
         struct drm_mode_object *mo;
 
-        mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_ENCODER);
+        mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_ENCODER);
 
         return mo ? obj_to_encoder(mo) : NULL;
 }
diff --git a/include/drm/drm_framebuffer.h b/include/drm/drm_framebuffer.h
index b6996ddb19d6..4c5ee4ae54df 100644
--- a/include/drm/drm_framebuffer.h
+++ b/include/drm/drm_framebuffer.h
@@ -205,6 +205,7 @@ int drm_framebuffer_init(struct drm_device *dev,
                          struct drm_framebuffer *fb,
                          const struct drm_framebuffer_funcs *funcs);
 struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev,
+                                               struct drm_file *file_priv,
                                                uint32_t id);
 void drm_framebuffer_remove(struct drm_framebuffer *fb);
 void drm_framebuffer_cleanup(struct drm_framebuffer *fb);
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index a767b4a30a6d..b2f920b518e3 100644
--- a/include/drm/drm_mode_object.h
+++ b/include/drm/drm_mode_object.h
@@ -27,6 +27,7 @@
 struct drm_object_properties;
 struct drm_property;
 struct drm_device;
+struct drm_file;
 
 /**
  * struct drm_mode_object - base structure for modeset objects
@@ -113,6 +114,7 @@ struct drm_object_properties {
         }
 
 struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
+                                             struct drm_file *file_priv,
                                              uint32_t id, uint32_t type);
 void drm_mode_object_get(struct drm_mode_object *obj);
 void drm_mode_object_put(struct drm_mode_object *obj);
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
index 104dd517fdbe..d20ec4e0431d 100644
--- a/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@ -2,6 +2,9 @@
 #define __DRM_OF_H__
 
 #include <linux/of_graph.h>
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
+#include <drm/drm_bridge.h>
+#endif
 
 struct component_master_ops;
 struct component_match;
@@ -67,6 +70,34 @@ static inline int drm_of_find_panel_or_bridge(const struct device_node *np,
 }
 #endif
 
+/*
+ * drm_of_panel_bridge_remove - remove panel bridge
+ * @np: device tree node containing panel bridge output ports
+ *
+ * Remove the panel bridge of a given DT node's port and endpoint number
+ *
+ * Returns zero if successful, or one of the standard error codes if it fails.
+ */
+static inline int drm_of_panel_bridge_remove(const struct device_node *np,
+                                             int port, int endpoint)
+{
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
+        struct drm_bridge *bridge;
+        struct device_node *remote;
+
+        remote = of_graph_get_remote_node(np, port, endpoint);
+        if (!remote)
+                return -ENODEV;
+
+        bridge = of_drm_find_bridge(remote);
+        drm_panel_bridge_remove(bridge);
+
+        return 0;
+#else
+        return -EINVAL;
+#endif
+}
+
 static inline int drm_of_encoder_active_endpoint_id(struct device_node *node,
                                                     struct drm_encoder *encoder)
 {
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 82a217bd77f0..069c4c8ce360 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -597,10 +597,11 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane,
  * drm_mode_object_find().
  */
 static inline struct drm_plane *drm_plane_find(struct drm_device *dev,
+                struct drm_file *file_priv,
                 uint32_t id)
 {
         struct drm_mode_object *mo;
-        mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PLANE);
+        mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PLANE);
         return mo ? obj_to_plane(mo) : NULL;
 }
 
diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
index 37355c623e6c..429d8218f740 100644
--- a/include/drm/drm_property.h
+++ b/include/drm/drm_property.h
@@ -312,10 +312,11 @@ drm_property_unreference_blob(struct drm_property_blob *blob)
  * This function looks up the property object specified by id and returns it.
  */
 static inline struct drm_property *drm_property_find(struct drm_device *dev,
+                                                     struct drm_file *file_priv,
                                                      uint32_t id)
 {
         struct drm_mode_object *mo;
-        mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PROPERTY);
+        mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PROPERTY);
         return mo ? obj_to_property(mo) : NULL;
 }
 
diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h
index 7fba9efe4951..6a58e2e91a0f 100644
--- a/include/drm/drm_vblank.h
+++ b/include/drm/drm_vblank.h
@@ -92,7 +92,7 @@ struct drm_vblank_crtc {
         /**
          * @time: Vblank timestamp corresponding to @count.
          */
-        struct timeval time;
+        ktime_t time;
 
         /**
          * @refcount: Number of users/waiters of the vblank interrupt. Only when
@@ -154,7 +154,7 @@ struct drm_vblank_crtc {
 int drm_vblank_init(struct drm_device *dev, unsigned int num_crtcs);
 u32 drm_crtc_vblank_count(struct drm_crtc *crtc);
 u32 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
-                                   struct timeval *vblanktime);
+                                   ktime_t *vblanktime);
 void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
                                struct drm_pending_vblank_event *e);
 void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
@@ -172,7 +172,7 @@ u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);
 
 bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
                                            unsigned int pipe, int *max_error,
-                                           struct timeval *vblank_time,
+                                           ktime_t *vblank_time,
                                            bool in_vblank_irq);
 void drm_calc_timestamping_constants(struct drm_crtc *crtc,
                                      const struct drm_display_mode *mode);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1257e15c1a03..972a25633525 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -339,7 +339,6 @@
 #define INTEL_KBL_GT1_IDS(info) \
         INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
         INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
-        INTEL_VGA_DEVICE(0x5917, info), /* DT  GT1.5 */ \
         INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
         INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
         INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
@@ -349,6 +348,7 @@
 
 #define INTEL_KBL_GT2_IDS(info) \
         INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+        INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
         INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
         INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
         INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
index 171895072435..ca974224d92e 100644
--- a/include/linux/dma-fence.h
+++ b/include/linux/dma-fence.h
@@ -248,9 +248,12 @@ dma_fence_get_rcu_safe(struct dma_fence * __rcu *fencep)
                 struct dma_fence *fence;
 
                 fence = rcu_dereference(*fencep);
-                if (!fence || !dma_fence_get_rcu(fence))
+                if (!fence)
                         return NULL;
 
+                if (!dma_fence_get_rcu(fence))
+                        continue;
+
                 /* The atomic_inc_not_zero() inside dma_fence_get_rcu()
                  * provides a full memory barrier upon success (such as now).
                  * This is paired with the write barrier from assigning
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 978abfbac617..93a4663d7acb 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -139,6 +139,45 @@ struct reg_sequence {
         pollret ?: ((cond) ? 0 : -ETIMEDOUT); \
 })
 
+/**
+ * regmap_field_read_poll_timeout - Poll until a condition is met or timeout
+ *
+ * @field: Regmap field to read from
+ * @val: Unsigned integer variable to read the value into
+ * @cond: Break condition (usually involving @val)
+ * @sleep_us: Maximum time to sleep between reads in us (0
+ *            tight-loops).  Should be less than ~20ms since usleep_range
+ *            is used (see Documentation/timers/timers-howto.txt).
+ * @timeout_us: Timeout in us, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_field_read
+ * error return value in case of a error read. In the two former cases,
+ * the last read value at @addr is stored in @val. Must not be called
+ * from atomic context if sleep_us or timeout_us are used.
+ *
+ * This is modelled after the readx_poll_timeout macros in linux/iopoll.h.
+ */
+#define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_us) \
+({ \
+        ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
+        int pollret; \
+        might_sleep_if(sleep_us); \
+        for (;;) { \
+                pollret = regmap_field_read((field), &(val)); \
+                if (pollret) \
+                        break; \
+                if (cond) \
+                        break; \
+                if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
+                        pollret = regmap_field_read((field), &(val)); \
+                        break; \
+                } \
+                if (sleep_us) \
+                        usleep_range((sleep_us >> 2) + 1, sleep_us); \
+        } \
+        pollret ?: ((cond) ? 0 : -ETIMEDOUT); \
+})
+
 #ifdef CONFIG_REGMAP
 
 enum regmap_endian {
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 4b3286ac60c8..874b50c232de 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -21,6 +21,12 @@ struct scatterlist {
 };
 
 /*
+ * Since the above length field is an unsigned int, below we define the maximum
+ * length in bytes that can be stored in one scatterlist entry.
+ */
+#define SCATTERLIST_MAX_SEGMENT (UINT_MAX & PAGE_MASK)
+
+/*
  * These macros should be used after a dma_map_sg call has been done
  * to get bus addresses of each of the SG entries and their lengths.
  * You should only work with the number of sg entries dma_map_sg
@@ -261,10 +267,13 @@ void sg_free_table(struct sg_table *);
 int __sg_alloc_table(struct sg_table *, unsigned int, unsigned int,
                      struct scatterlist *, gfp_t, sg_alloc_fn *);
 int sg_alloc_table(struct sg_table *, unsigned int, gfp_t);
-int sg_alloc_table_from_pages(struct sg_table *sgt,
-        struct page **pages, unsigned int n_pages,
-        unsigned long offset, unsigned long size,
-        gfp_t gfp_mask);
+int __sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                                unsigned int n_pages, unsigned int offset,
+                                unsigned long size, unsigned int max_segment,
+                                gfp_t gfp_mask);
+int sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                              unsigned int n_pages, unsigned int offset,
+                              unsigned long size, gfp_t gfp_mask);
 
 size_t sg_copy_buffer(struct scatterlist *sgl, unsigned int nents, void *buf,
                       size_t buflen, off_t skip, bool to_buffer);
diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h
index 76f6f78a352b..110cc73bf549 100644
--- a/include/uapi/drm/etnaviv_drm.h
+++ b/include/uapi/drm/etnaviv_drm.h
@@ -150,6 +150,19 @@ struct drm_etnaviv_gem_submit_bo {
         __u64 presumed;       /* in/out, presumed buffer address */
 };
 
+/* performance monitor request (pmr) */
+#define ETNA_PM_PROCESS_PRE             0x0001
+#define ETNA_PM_PROCESS_POST            0x0002
+struct drm_etnaviv_gem_submit_pmr {
+        __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
+        __u8  domain;         /* in, pm domain */
+        __u8  pad;
+        __u16 signal;         /* in, pm signal */
+        __u32 sequence;       /* in, sequence number */
+        __u32 read_offset;    /* in, offset from read_bo */
+        __u32 read_idx;       /* in, index of read_bo buffer */
+};
+
 /* Each cmdstream submit consists of a table of buffers involved, and
  * one or more cmdstream buffers.  This allows for conditional execution
  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
@@ -175,6 +188,9 @@ struct drm_etnaviv_gem_submit {
         __u64 stream;         /* in, ptr to cmdstream */
         __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
         __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
+        __u64 pmrs;           /* in, ptr to array of submit_pmr's */
+        __u32 nr_pmrs;        /* in, number of submit_pmr's */
+        __u32 pad;
 };
 
 /* The normal way to synchronize with the GPU is just to CPU_PREP on
@@ -210,6 +226,27 @@ struct drm_etnaviv_gem_wait {
         struct drm_etnaviv_timespec timeout;    /* in */
 };
 
+/*
+ * Performance Monitor (PM):
+ */
+
+struct drm_etnaviv_pm_domain {
+        __u32 pipe;       /* in */
+        __u8  iter;       /* in/out, select pm domain at index iter */
+        __u8  id;         /* out, id of domain */
+        __u16 nr_signals; /* out, how many signals does this domain provide */
+        char  name[64];   /* out, name of domain */
+};
+
+struct drm_etnaviv_pm_signal {
+        __u32 pipe;       /* in */
+        __u8  domain;     /* in, pm domain index */
+        __u8  pad;
+        __u16 iter;       /* in/out, select pm source at index iter */
+        __u16 id;         /* out, id of signal */
+        char  name[64];   /* out, name of domain */
+};
+
 #define DRM_ETNAVIV_GET_PARAM          0x00
 /* placeholder:
 #define DRM_ETNAVIV_SET_PARAM          0x01
@@ -222,7 +259,9 @@ struct drm_etnaviv_gem_wait {
 #define DRM_ETNAVIV_WAIT_FENCE         0x07
 #define DRM_ETNAVIV_GEM_USERPTR        0x08
 #define DRM_ETNAVIV_GEM_WAIT           0x09
-#define DRM_ETNAVIV_NUM_IOCTLS         0x0a
+#define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
+#define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
+#define DRM_ETNAVIV_NUM_IOCTLS         0x0c
 
 #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
 #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
@@ -233,6 +272,8 @@ struct drm_etnaviv_gem_wait {
 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
 #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
+#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
+#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
 
 #if defined(__cplusplus)
 }
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d8d10d932759..fe25a01c81f2 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1308,14 +1308,16 @@ struct drm_i915_reg_read {
          * be specified
          */
         __u64 offset;
+#define I915_REG_READ_8B_WA BIT(0)
+
         __u64 val; /* Return value */
 };
 /* Known registers:
  *
  * Render engine timestamp - 0x2358 + 64bit - gen7+
  * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that use
- *   offset (0x2538 | 1) instead.
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
  *
  */
 
@@ -1509,6 +1511,11 @@ struct drm_i915_perf_oa_config {
         __u32 n_boolean_regs;
         __u32 n_flex_regs;
 
+        /*
+         * These fields are pointers to tuples of u32 values (register
+         * address, value). For example the expected length of the buffer
+         * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+         */
         __u64 mux_regs_ptr;
         __u64 boolean_regs_ptr;
         __u64 flex_regs_ptr;
diff --git a/lib/scatterlist.c b/lib/scatterlist.c
index be7b4dd6b68d..7c1c55f7daaa 100644
--- a/lib/scatterlist.c
+++ b/lib/scatterlist.c
@@ -370,41 +370,49 @@ int sg_alloc_table(struct sg_table *table, unsigned int nents, gfp_t gfp_mask)
 EXPORT_SYMBOL(sg_alloc_table);
 
 /**
- * sg_alloc_table_from_pages - Allocate and initialize an sg table from
- *                             an array of pages
- * @sgt:        The sg table header to use
- * @pages:      Pointer to an array of page pointers
- * @n_pages:    Number of pages in the pages array
- * @offset:     Offset from start of the first page to the start of a buffer
- * @size:       Number of valid bytes in the buffer (after offset)
- * @gfp_mask:   GFP allocation mask
+ * __sg_alloc_table_from_pages - Allocate and initialize an sg table from
+ *                               an array of pages
+ * @sgt:         The sg table header to use
+ * @pages:       Pointer to an array of page pointers
+ * @n_pages:     Number of pages in the pages array
+ * @offset:      Offset from start of the first page to the start of a buffer
+ * @size:        Number of valid bytes in the buffer (after offset)
+ * @max_segment: Maximum size of a scatterlist node in bytes (page aligned)
+ * @gfp_mask:    GFP allocation mask
  *
  *  Description:
  *    Allocate and initialize an sg table from a list of pages. Contiguous
- *    ranges of the pages are squashed into a single scatterlist node. A user
- *    may provide an offset at a start and a size of valid data in a buffer
- *    specified by the page array. The returned sg table is released by
- *    sg_free_table.
+ *    ranges of the pages are squashed into a single scatterlist node up to the
+ *    maximum size specified in @max_segment. An user may provide an offset at a
+ *    start and a size of valid data in a buffer specified by the page array.
+ *    The returned sg table is released by sg_free_table.
  *
  * Returns:
  *   0 on success, negative error on failure
  */
-int sg_alloc_table_from_pages(struct sg_table *sgt,
-        struct page **pages, unsigned int n_pages,
-        unsigned long offset, unsigned long size,
-        gfp_t gfp_mask)
+int __sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                                unsigned int n_pages, unsigned int offset,
+                                unsigned long size, unsigned int max_segment,
+                                gfp_t gfp_mask)
 {
-        unsigned int chunks;
-        unsigned int i;
-        unsigned int cur_page;
+        unsigned int chunks, cur_page, seg_len, i;
         int ret;
         struct scatterlist *s;
 
+        if (WARN_ON(!max_segment || offset_in_page(max_segment)))
+                return -EINVAL;
+
         /* compute number of contiguous chunks */
         chunks = 1;
-        for (i = 1; i < n_pages; ++i)
-                if (page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) + 1)
-                        ++chunks;
+        seg_len = 0;
+        for (i = 1; i < n_pages; i++) {
+                seg_len += PAGE_SIZE;
+                if (seg_len >= max_segment ||
+                    page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) + 1) {
+                        chunks++;
+                        seg_len = 0;
+                }
+        }
 
         ret = sg_alloc_table(sgt, chunks, gfp_mask);
         if (unlikely(ret))
@@ -413,17 +421,21 @@ int sg_alloc_table_from_pages(struct sg_table *sgt,
         /* merging chunks and putting them into the scatterlist */
         cur_page = 0;
         for_each_sg(sgt->sgl, s, sgt->orig_nents, i) {
-                unsigned long chunk_size;
-                unsigned int j;
+                unsigned int j, chunk_size;
 
                 /* look for the end of the current chunk */
-                for (j = cur_page + 1; j < n_pages; ++j)
-                        if (page_to_pfn(pages[j]) !=
+                seg_len = 0;
+                for (j = cur_page + 1; j < n_pages; j++) {
+                        seg_len += PAGE_SIZE;
+                        if (seg_len >= max_segment ||
+                            page_to_pfn(pages[j]) !=
                             page_to_pfn(pages[j - 1]) + 1)
                                 break;
+                }
 
                 chunk_size = ((j - cur_page) << PAGE_SHIFT) - offset;
-                sg_set_page(s, pages[cur_page], min(size, chunk_size), offset);
+                sg_set_page(s, pages[cur_page],
+                            min_t(unsigned long, size, chunk_size), offset);
                 size -= chunk_size;
                 offset = 0;
                 cur_page = j;
@@ -431,6 +443,35 @@ int sg_alloc_table_from_pages(struct sg_table *sgt,
 
         return 0;
 }
+EXPORT_SYMBOL(__sg_alloc_table_from_pages);
+
+/**
+ * sg_alloc_table_from_pages - Allocate and initialize an sg table from
+ *                             an array of pages
+ * @sgt:         The sg table header to use
+ * @pages:       Pointer to an array of page pointers
+ * @n_pages:     Number of pages in the pages array
+ * @offset:      Offset from start of the first page to the start of a buffer
+ * @size:        Number of valid bytes in the buffer (after offset)
+ * @gfp_mask:    GFP allocation mask
+ *
+ *  Description:
+ *    Allocate and initialize an sg table from a list of pages. Contiguous
+ *    ranges of the pages are squashed into a single scatterlist node. A user
+ *    may provide an offset at a start and a size of valid data in a buffer
+ *    specified by the page array. The returned sg table is released by
+ *    sg_free_table.
+ *
+ * Returns:
+ *   0 on success, negative error on failure
+ */
+int sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
+                              unsigned int n_pages, unsigned int offset,
+                              unsigned long size, gfp_t gfp_mask)
+{
+        return __sg_alloc_table_from_pages(sgt, pages, n_pages, offset, size,
+                                           SCATTERLIST_MAX_SEGMENT, gfp_mask);
+}
 EXPORT_SYMBOL(sg_alloc_table_from_pages);
 
 void __sg_page_iter_start(struct sg_page_iter *piter,
diff --git a/tools/testing/scatterlist/Makefile b/tools/testing/scatterlist/Makefile
new file mode 100644
index 000000000000..933c3a6e4d77
--- /dev/null
+++ b/tools/testing/scatterlist/Makefile
@@ -0,0 +1,30 @@
+CFLAGS += -I. -I../../include -g -O2 -Wall -fsanitize=address
+LDFLAGS += -fsanitize=address -fsanitize=undefined
+TARGETS = main
+OFILES = main.o scatterlist.o
+
+ifeq ($(BUILD), 32)
+        CFLAGS += -m32
+        LDFLAGS += -m32
+endif
+
+targets: include $(TARGETS)
+
+main: $(OFILES)
+
+clean:
+        $(RM) $(TARGETS) $(OFILES) scatterlist.c linux/scatterlist.h linux/highmem.h linux/kmemleak.h asm/io.h
+        @rmdir asm
+
+scatterlist.c: ../../../lib/scatterlist.c
+        @sed -e 's/^static //' -e 's/__always_inline //' -e 's/inline //' < $< > $@
+
+.PHONY: include
+
+include: ../../../include/linux/scatterlist.h
+        @mkdir -p linux
+        @mkdir -p asm
+        @touch asm/io.h
+        @touch linux/highmem.h
+        @touch linux/kmemleak.h
+        @cp $< linux/scatterlist.h
diff --git a/tools/testing/scatterlist/linux/mm.h b/tools/testing/scatterlist/linux/mm.h
new file mode 100644
index 000000000000..6f9ac14aa800
--- /dev/null
+++ b/tools/testing/scatterlist/linux/mm.h
@@ -0,0 +1,125 @@
+#ifndef _LINUX_MM_H
+#define _LINUX_MM_H
+
+#include <assert.h>
+#include <string.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <limits.h>
+#include <stdio.h>
+
+typedef unsigned long dma_addr_t;
+
+#define unlikely
+
+#define BUG_ON(x) assert(!(x))
+
+#define WARN_ON(condition) ({                                           \
+        int __ret_warn_on = !!(condition);                              \
+        unlikely(__ret_warn_on);                                        \
+})
+
+#define WARN_ON_ONCE(condition) ({                              \
+        int __ret_warn_on = !!(condition);                      \
+        if (unlikely(__ret_warn_on))                            \
+                assert(0);                                      \
+        unlikely(__ret_warn_on);                                \
+})
+
+#define PAGE_SIZE       (4096)
+#define PAGE_SHIFT      (12)
+#define PAGE_MASK       (~(PAGE_SIZE-1))
+
+#define __ALIGN_KERNEL(x, a)            __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
+#define __ALIGN_KERNEL_MASK(x, mask)    (((x) + (mask)) & ~(mask))
+#define ALIGN(x, a)                     __ALIGN_KERNEL((x), (a))
+
+#define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE)
+
+#define offset_in_page(p)       ((unsigned long)(p) & ~PAGE_MASK)
+
+#define virt_to_page(x) ((void *)x)
+#define page_address(x) ((void *)x)
+
+static inline unsigned long page_to_phys(struct page *page)
+{
+        assert(0);
+
+        return 0;
+}
+
+#define page_to_pfn(page) ((unsigned long)(page) / PAGE_SIZE)
+#define pfn_to_page(pfn) (void *)((pfn) * PAGE_SIZE)
+#define nth_page(page,n) pfn_to_page(page_to_pfn((page)) + (n))
+
+#define __min(t1, t2, min1, min2, x, y) ({              \
+        t1 min1 = (x);                                  \
+        t2 min2 = (y);                                  \
+        (void) (&min1 == &min2);                        \
+        min1 < min2 ? min1 : min2; })
+
+#define ___PASTE(a,b) a##b
+#define __PASTE(a,b) ___PASTE(a,b)
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#define min(x, y)                                       \
+        __min(typeof(x), typeof(y),                     \
+              __UNIQUE_ID(min1_), __UNIQUE_ID(min2_),   \
+              x, y)
+
+#define min_t(type, x, y)                               \
+        __min(type, type,                               \
+              __UNIQUE_ID(min1_), __UNIQUE_ID(min2_),   \
+              x, y)
+
+#define preemptible() (1)
+
+static inline void *kmap(struct page *page)
+{
+        assert(0);
+
+        return NULL;
+}
+
+static inline void *kmap_atomic(struct page *page)
+{
+        assert(0);
+
+        return NULL;
+}
+
+static inline void kunmap(void *addr)
+{
+        assert(0);
+}
+
+static inline void kunmap_atomic(void *addr)
+{
+        assert(0);
+}
+
+static inline unsigned long __get_free_page(unsigned int flags)
+{
+        return (unsigned long)malloc(PAGE_SIZE);
+}
+
+static inline void free_page(unsigned long page)
+{
+        free((void *)page);
+}
+
+static inline void *kmalloc(unsigned int size, unsigned int flags)
+{
+        return malloc(size);
+}
+
+#define kfree(x) free(x)
+
+#define kmemleak_alloc(a, b, c, d)
+#define kmemleak_free(a)
+
+#define PageSlab(p) (0)
+#define flush_kernel_dcache_page(p)
+
+#endif
diff --git a/tools/testing/scatterlist/main.c b/tools/testing/scatterlist/main.c
new file mode 100644
index 000000000000..0a1464181226
--- /dev/null
+++ b/tools/testing/scatterlist/main.c
@@ -0,0 +1,79 @@
+#include <stdio.h>
+#include <assert.h>
+
+#include <linux/scatterlist.h>
+
+#define MAX_PAGES (64)
+
+static void set_pages(struct page **pages, const unsigned *array, unsigned num)
+{
+        unsigned int i;
+
+        assert(num < MAX_PAGES);
+        for (i = 0; i < num; i++)
+                pages[i] = (struct page *)(unsigned long)
+                           ((1 + array[i]) * PAGE_SIZE);
+}
+
+#define pfn(...) (unsigned []){ __VA_ARGS__ }
+
+int main(void)
+{
+        const unsigned int sgmax = SCATTERLIST_MAX_SEGMENT;
+        struct test {
+                int alloc_ret;
+                unsigned num_pages;
+                unsigned *pfn;
+                unsigned size;
+                unsigned int max_seg;
+                unsigned int expected_segments;
+        } *test, tests[] = {
+                { -EINVAL, 1, pfn(0), PAGE_SIZE, PAGE_SIZE + 1, 1 },
+                { -EINVAL, 1, pfn(0), PAGE_SIZE, 0, 1 },
+                { -EINVAL, 1, pfn(0), PAGE_SIZE, sgmax + 1, 1 },
+                { 0, 1, pfn(0), PAGE_SIZE, sgmax, 1 },
+                { 0, 1, pfn(0), 1, sgmax, 1 },
+                { 0, 2, pfn(0, 1), 2 * PAGE_SIZE, sgmax, 1 },
+                { 0, 2, pfn(1, 0), 2 * PAGE_SIZE, sgmax, 2 },
+                { 0, 3, pfn(0, 1, 2), 3 * PAGE_SIZE, sgmax, 1 },
+                { 0, 3, pfn(0, 2, 1), 3 * PAGE_SIZE, sgmax, 3 },
+                { 0, 3, pfn(0, 1, 3), 3 * PAGE_SIZE, sgmax, 2 },
+                { 0, 3, pfn(1, 2, 4), 3 * PAGE_SIZE, sgmax, 2 },
+                { 0, 3, pfn(1, 3, 4), 3 * PAGE_SIZE, sgmax, 2 },
+                { 0, 4, pfn(0, 1, 3, 4), 4 * PAGE_SIZE, sgmax, 2 },
+                { 0, 5, pfn(0, 1, 3, 4, 5), 5 * PAGE_SIZE, sgmax, 2 },
+                { 0, 5, pfn(0, 1, 3, 4, 6), 5 * PAGE_SIZE, sgmax, 3 },
+                { 0, 5, pfn(0, 1, 2, 3, 4), 5 * PAGE_SIZE, sgmax, 1 },
+                { 0, 5, pfn(0, 1, 2, 3, 4), 5 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
+                { 0, 6, pfn(0, 1, 2, 3, 4, 5), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
+                { 0, 6, pfn(0, 2, 3, 4, 5, 6), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 4 },
+                { 0, 6, pfn(0, 1, 3, 4, 5, 6), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
+                { 0, 0, NULL, 0, 0, 0 },
+        };
+        unsigned int i;
+
+        for (i = 0, test = tests; test->expected_segments; test++, i++) {
+                struct page *pages[MAX_PAGES];
+                struct sg_table st;
+                int ret;
+
+                set_pages(pages, test->pfn, test->num_pages);
+
+                ret = __sg_alloc_table_from_pages(&st, pages, test->num_pages,
+                                                  0, test->size, test->max_seg,
+                                                  GFP_KERNEL);
+                assert(ret == test->alloc_ret);
+
+                if (test->alloc_ret)
+                        continue;
+
+                assert(st.nents == test->expected_segments);
+                assert(st.orig_nents == test->expected_segments);
+
+                sg_free_table(&st);
+        }
+
+        assert(i == (sizeof(tests) / sizeof(tests[0])) - 1);
+
+        return 0;
+}