diff options
author | Tony Lindgren <tony@atomide.com> | 2018-01-12 18:15:50 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2018-01-12 18:15:50 -0500 |
commit | bcc8d312dedf6f867be2f32da3410277949c344e (patch) | |
tree | 43fd9eb29868067aa8a4c4d45d9f1b76243ee850 | |
parent | 80a06c0d8357d1e75a8fbc10813fcdada4d897fb (diff) | |
parent | 20a2742e5784295b9197250b50c40f6d38a55880 (diff) |
Merge commit '20a2742e5784295b9197250b50c40f6d38a55880' into omap-for-v4.16/dt-clk
-rw-r--r-- | Documentation/devicetree/bindings/bus/ti-sysc.txt | 36 | ||||
-rw-r--r-- | include/dt-bindings/bus/ti-sysc.h | 22 |
2 files changed, 58 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index fb1790e39398..48bbb0c96835 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt | |||
@@ -26,6 +26,8 @@ Required standard properties: | |||
26 | or one of the following derivative types for hardware | 26 | or one of the following derivative types for hardware |
27 | needing special workarounds: | 27 | needing special workarounds: |
28 | 28 | ||
29 | "ti,sysc-omap2-timer" | ||
30 | "ti,sysc-omap4-timer" | ||
29 | "ti,sysc-omap3430-sr" | 31 | "ti,sysc-omap3430-sr" |
30 | "ti,sysc-omap3630-sr" | 32 | "ti,sysc-omap3630-sr" |
31 | "ti,sysc-omap4-sr" | 33 | "ti,sysc-omap4-sr" |
@@ -49,6 +51,26 @@ Required standard properties: | |||
49 | 51 | ||
50 | Optional properties: | 52 | Optional properties: |
51 | 53 | ||
54 | - ti,sysc-mask shall contain mask of supported register bits for the | ||
55 | SYSCONFIG register as documented in the Technical Reference | ||
56 | Manual (TRM) for the interconnect target module | ||
57 | |||
58 | - ti,sysc-midle list of master idle modes supported by the interconnect | ||
59 | target module as documented in the TRM for SYSCONFIG | ||
60 | register MIDLEMODE bits | ||
61 | |||
62 | - ti,sysc-sidle list of slave idle modes supported by the interconnect | ||
63 | target module as documented in the TRM for SYSCONFIG | ||
64 | register SIDLEMODE bits | ||
65 | |||
66 | - ti,sysc-delay-us delay needed after OCP softreset before accssing | ||
67 | SYSCONFIG register again | ||
68 | |||
69 | - ti,syss-mask optional mask of reset done status bits as described in the | ||
70 | TRM for SYSSTATUS registers, typically 1 with some devices | ||
71 | having separate reset done bits for children like OHCI and | ||
72 | EHCI | ||
73 | |||
52 | - clocks clock specifier for each name in the clock-names as | 74 | - clocks clock specifier for each name in the clock-names as |
53 | specified in the binding documentation for ti-clkctrl, | 75 | specified in the binding documentation for ti-clkctrl, |
54 | typically available for all interconnect targets on TI SoCs | 76 | typically available for all interconnect targets on TI SoCs |
@@ -61,6 +83,9 @@ Optional properties: | |||
61 | - ti,hwmods optional TI interconnect module name to use legacy | 83 | - ti,hwmods optional TI interconnect module name to use legacy |
62 | hwmod platform data | 84 | hwmod platform data |
63 | 85 | ||
86 | - ti,no-reset-on-init interconnect target module should not be reset at init | ||
87 | |||
88 | - ti,no-idle-on-init interconnect target module should not be idled at init | ||
64 | 89 | ||
65 | Example: Single instance of MUSB controller on omap4 using interconnect ranges | 90 | Example: Single instance of MUSB controller on omap4 using interconnect ranges |
66 | using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): | 91 | using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): |
@@ -74,6 +99,17 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): | |||
74 | reg-names = "rev", "sysc", "syss"; | 99 | reg-names = "rev", "sysc", "syss"; |
75 | clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; | 100 | clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; |
76 | clock-names = "fck"; | 101 | clock-names = "fck"; |
102 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | ||
103 | SYSC_OMAP2_SOFTRESET | | ||
104 | SYSC_OMAP2_AUTOIDLE)>; | ||
105 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | ||
106 | <SYSC_IDLE_NO>, | ||
107 | <SYSC_IDLE_SMART>; | ||
108 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | ||
109 | <SYSC_IDLE_NO>, | ||
110 | <SYSC_IDLE_SMART>, | ||
111 | <SYSC_IDLE_SMART_WKUP>; | ||
112 | ti,syss-mask = <1>; | ||
77 | #address-cells = <1>; | 113 | #address-cells = <1>; |
78 | #size-cells = <1>; | 114 | #size-cells = <1>; |
79 | ranges = <0 0x2b000 0x1000>; | 115 | ranges = <0 0x2b000 0x1000>; |
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h new file mode 100644 index 000000000000..2c005376ac0e --- /dev/null +++ b/include/dt-bindings/bus/ti-sysc.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* TI sysc interconnect target module defines */ | ||
2 | |||
3 | /* Generic sysc found on omap2 and later, also known as type1 */ | ||
4 | #define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) | ||
5 | #define SYSC_OMAP2_EMUFREE (1 << 5) | ||
6 | #define SYSC_OMAP2_ENAWAKEUP (1 << 2) | ||
7 | #define SYSC_OMAP2_SOFTRESET (1 << 1) | ||
8 | #define SYSC_OMAP2_AUTOIDLE (1 << 0) | ||
9 | |||
10 | /* Generic sysc found on omap4 and later, also known as type2 */ | ||
11 | #define SYSC_OMAP4_DMADISABLE (1 << 16) | ||
12 | #define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ | ||
13 | #define SYSC_OMAP4_SOFTRESET (1 << 0) | ||
14 | |||
15 | /* SmartReflex sysc found on 36xx and later */ | ||
16 | #define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) | ||
17 | |||
18 | /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ | ||
19 | #define SYSC_IDLE_FORCE 0 | ||
20 | #define SYSC_IDLE_NO 1 | ||
21 | #define SYSC_IDLE_SMART 2 | ||
22 | #define SYSC_IDLE_SMART_WKUP 3 | ||