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authorVineet Gupta <vgupta@synopsys.com>2015-06-04 05:09:15 -0400
committerVineet Gupta <vgupta@synopsys.com>2015-06-22 04:36:56 -0400
commitbcc4d65abec2adb74157b34519e80331eb4427eb (patch)
treebb35ec4fc31cc6f9e8d3063c82cf682e2e723434
parentd1f317d8254413447bcd6b6adbde24a985d256c2 (diff)
ARCv2: MMUv4: support aliasing icache config
This is also default for AXS103 release Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r--arch/arc/include/asm/cache.h4
-rw-r--r--arch/arc/mm/cache.c14
2 files changed, 14 insertions, 4 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index e54977a7d006..d21c76d6b054 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void);
60#define ARC_REG_IC_IVIC 0x10 60#define ARC_REG_IC_IVIC 0x10
61#define ARC_REG_IC_CTRL 0x11 61#define ARC_REG_IC_CTRL 0x11
62#define ARC_REG_IC_IVIL 0x19 62#define ARC_REG_IC_IVIL 0x19
63#if defined(CONFIG_ARC_MMU_V3) 63#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
64#define ARC_REG_IC_PTAG 0x1E 64#define ARC_REG_IC_PTAG 0x1E
65#endif 65#endif
66 66
@@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void);
74#define ARC_REG_DC_IVDL 0x4A 74#define ARC_REG_DC_IVDL 0x4A
75#define ARC_REG_DC_FLSH 0x4B 75#define ARC_REG_DC_FLSH 0x4B
76#define ARC_REG_DC_FLDL 0x4C 76#define ARC_REG_DC_FLDL 0x4C
77#if defined(CONFIG_ARC_MMU_V3)
78#define ARC_REG_DC_PTAG 0x5C 77#define ARC_REG_DC_PTAG 0x5C
79#endif
80 78
81/* Bit val in DC_CTRL */ 79/* Bit val in DC_CTRL */
82#define DC_CTRL_INV_MODE_FLUSH 0x40 80#define DC_CTRL_INV_MODE_FLUSH 0x40
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7a898f57d84b..0eaaee60fd0b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -21,6 +21,9 @@
21#include <asm/cachectl.h> 21#include <asm/cachectl.h>
22#include <asm/setup.h> 22#include <asm/setup.h>
23 23
24void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,
25 unsigned long sz, const int cacheop);
26
24char *arc_cache_mumbojumbo(int c, char *buf, int len) 27char *arc_cache_mumbojumbo(int c, char *buf, int len)
25{ 28{
26 int n = 0; 29 int n = 0;
@@ -414,7 +417,7 @@ __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr,
414 unsigned long flags; 417 unsigned long flags;
415 418
416 local_irq_save(flags); 419 local_irq_save(flags);
417 __cache_line_loop(paddr, vaddr, sz, OP_INV_IC); 420 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
418 local_irq_restore(flags); 421 local_irq_restore(flags);
419} 422}
420 423
@@ -746,6 +749,15 @@ void arc_cache_init(void)
746 if (ic->ver != CONFIG_ARC_MMU_VER) 749 if (ic->ver != CONFIG_ARC_MMU_VER)
747 panic("Cache ver [%d] doesn't match MMU ver [%d]\n", 750 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
748 ic->ver, CONFIG_ARC_MMU_VER); 751 ic->ver, CONFIG_ARC_MMU_VER);
752
753 /*
754 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG
755 * pair to provide vaddr/paddr respectively, just as in MMU v3
756 */
757 if (is_isa_arcv2() && ic->alias)
758 _cache_line_loop_ic_fn = __cache_line_loop_v3;
759 else
760 _cache_line_loop_ic_fn = __cache_line_loop;
749 } 761 }
750 762
751 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { 763 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {