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authorMarek Szyprowski <m.szyprowski@samsung.com>2017-01-11 02:44:28 -0500
committerKrzysztof Kozlowski <krzk@kernel.org>2017-01-11 11:28:43 -0500
commitbca9085e0ae93253bc93ce218c85ac7d7e7f1831 (patch)
tree65d385e3a401ada9c5b5b4cae9fad3c0e2dbceab
parent80b7a2e2498bcffb1a79980dfbeb7a1275577b28 (diff)
ARM: dts: exynos: remove Exynos4212 support (dead code)
There are no Exynos4212 based boards in mainline, so there is no need to keep additional files for SoCs, which are never used. This patch removes support for Exynos4212 SoCs and moves previously shared Exynos4412 definitions to a single file to simplify future maintenance. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi133
-rw-r--r--arch/arm/boot/dts/exynos4412-pinctrl.dtsi (renamed from arch/arm/boot/dts/exynos4x12-pinctrl.dtsi)4
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi575
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi594
4 files changed, 572 insertions, 734 deletions
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
deleted file mode 100644
index 538901123d37..000000000000
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Samsung's Exynos4212 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4212", "samsung,exynos4";
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu0: cpu@A00 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <0xA00>;
33 clocks = <&clock CLK_ARM_CLK>;
34 clock-names = "cpu";
35 operating-points-v2 = <&cpu0_opp_table>;
36 cooling-min-level = <13>;
37 cooling-max-level = <7>;
38 #cooling-cells = <2>; /* min followed by max */
39 };
40
41 cpu@A01 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 reg = <0xA01>;
45 operating-points-v2 = <&cpu0_opp_table>;
46 };
47 };
48
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp00 {
54 opp-hz = /bits/ 64 <200000000>;
55 opp-microvolt = <900000>;
56 clock-latency-ns = <200000>;
57 };
58 opp01 {
59 opp-hz = /bits/ 64 <300000000>;
60 opp-microvolt = <900000>;
61 clock-latency-ns = <200000>;
62 };
63 opp02 {
64 opp-hz = /bits/ 64 <400000000>;
65 opp-microvolt = <925000>;
66 clock-latency-ns = <200000>;
67 };
68 opp03 {
69 opp-hz = /bits/ 64 <500000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <200000>;
72 };
73 opp04 {
74 opp-hz = /bits/ 64 <600000000>;
75 opp-microvolt = <975000>;
76 clock-latency-ns = <200000>;
77 };
78 opp05 {
79 opp-hz = /bits/ 64 <700000000>;
80 opp-microvolt = <987500>;
81 clock-latency-ns = <200000>;
82 };
83 opp06 {
84 opp-hz = /bits/ 64 <800000000>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <200000>;
87 };
88 opp07 {
89 opp-hz = /bits/ 64 <900000000>;
90 opp-microvolt = <1037500>;
91 clock-latency-ns = <200000>;
92 };
93 opp08 {
94 opp-hz = /bits/ 64 <1000000000>;
95 opp-microvolt = <1087500>;
96 clock-latency-ns = <200000>;
97 };
98 opp09 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-microvolt = <1137500>;
101 clock-latency-ns = <200000>;
102 };
103 opp10 {
104 opp-hz = /bits/ 64 <1200000000>;
105 opp-microvolt = <1187500>;
106 clock-latency-ns = <200000>;
107 };
108 opp11 {
109 opp-hz = /bits/ 64 <1300000000>;
110 opp-microvolt = <1250000>;
111 clock-latency-ns = <200000>;
112 };
113 opp12 {
114 opp-hz = /bits/ 64 <1400000000>;
115 opp-microvolt = <1287500>;
116 clock-latency-ns = <200000>;
117 };
118 opp13 {
119 opp-hz = /bits/ 64 <1500000000>;
120 opp-microvolt = <1350000>;
121 clock-latency-ns = <200000>;
122 turbo-mode;
123 };
124 };
125};
126
127&combiner {
128 samsung,combiner-nr = <18>;
129};
130
131&gic {
132 cpu-offset = <0x8000>;
133};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index 2f866f6e5838..1d27c28564e4 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -1,10 +1,10 @@
1/* 1/*
2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source 2 * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source
3 * 3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
6 * 6 *
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device 7 * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device
8 * tree nodes are listed in this file. 8 * tree nodes are listed in this file.
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 3ebdf01d814c..4f7b5a1a848c 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,11 +17,23 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20#include "exynos4x12.dtsi" 20#include "exynos4.dtsi"
21#include "exynos4412-pinctrl.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
21 23
22/ { 24/ {
23 compatible = "samsung,exynos4412", "samsung,exynos4"; 25 compatible = "samsung,exynos4412", "samsung,exynos4";
24 26
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 fimc-lite0 = &fimc_lite_0;
33 fimc-lite1 = &fimc_lite_1;
34 mshc0 = &mshc_0;
35 };
36
25 cpus { 37 cpus {
26 #address-cells = <1>; 38 #address-cells = <1>;
27 #size-cells = <0>; 39 #size-cells = <0>;
@@ -138,19 +150,572 @@
138 }; 150 };
139 }; 151 };
140 152
153 sysram@02020000 {
154 compatible = "mmio-sram";
155 reg = <0x02020000 0x40000>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0x02020000 0x40000>;
159
160 smp-sysram@0 {
161 compatible = "samsung,exynos4210-sysram";
162 reg = <0x0 0x1000>;
163 };
164
165 smp-sysram@2f000 {
166 compatible = "samsung,exynos4210-sysram-ns";
167 reg = <0x2f000 0x1000>;
168 };
169 };
170
171 pd_isp: isp-power-domain@10023CA0 {
172 compatible = "samsung,exynos4210-pd";
173 reg = <0x10023CA0 0x20>;
174 #power-domain-cells = <0>;
175 };
176
177 l2c: l2-cache-controller@10502000 {
178 compatible = "arm,pl310-cache";
179 reg = <0x10502000 0x1000>;
180 cache-unified;
181 cache-level = <2>;
182 arm,tag-latency = <2 2 1>;
183 arm,data-latency = <3 2 1>;
184 arm,double-linefill = <1>;
185 arm,double-linefill-incr = <0>;
186 arm,double-linefill-wrap = <1>;
187 arm,prefetch-drop = <1>;
188 arm,prefetch-offset = <7>;
189 };
190
191 clock: clock-controller@10030000 {
192 compatible = "samsung,exynos4412-clock";
193 reg = <0x10030000 0x20000>;
194 #clock-cells = <1>;
195 };
196
197 mct@10050000 {
198 compatible = "samsung,exynos4412-mct";
199 reg = <0x10050000 0x800>;
200 interrupt-parent = <&mct_map>;
201 interrupts = <0>, <1>, <2>, <3>, <4>;
202 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
203 clock-names = "fin_pll", "mct";
204
205 mct_map: mct-map {
206 #interrupt-cells = <1>;
207 #address-cells = <0>;
208 #size-cells = <0>;
209 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
210 <1 &combiner 12 5>,
211 <2 &combiner 12 6>,
212 <3 &combiner 12 7>,
213 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
214 };
215 };
216
217 adc: adc@126C0000 {
218 compatible = "samsung,exynos-adc-v1";
219 reg = <0x126C0000 0x100>;
220 interrupt-parent = <&combiner>;
221 interrupts = <10 3>;
222 clocks = <&clock CLK_TSADC>;
223 clock-names = "adc";
224 #io-channel-cells = <1>;
225 io-channel-ranges;
226 samsung,syscon-phandle = <&pmu_system_controller>;
227 status = "disabled";
228 };
229
230 g2d: g2d@10800000 {
231 compatible = "samsung,exynos4212-g2d";
232 reg = <0x10800000 0x1000>;
233 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
235 clock-names = "sclk_fimg2d", "fimg2d";
236 iommus = <&sysmmu_g2d>;
237 };
238
239 camera {
240 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
241 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
242 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
243
244 /* fimc_[0-3] are configured outside, under phandles */
245 fimc_lite_0: fimc-lite@12390000 {
246 compatible = "samsung,exynos4212-fimc-lite";
247 reg = <0x12390000 0x1000>;
248 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
249 power-domains = <&pd_isp>;
250 clocks = <&clock CLK_FIMC_LITE0>;
251 clock-names = "flite";
252 iommus = <&sysmmu_fimc_lite0>;
253 status = "disabled";
254 };
255
256 fimc_lite_1: fimc-lite@123A0000 {
257 compatible = "samsung,exynos4212-fimc-lite";
258 reg = <0x123A0000 0x1000>;
259 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
260 power-domains = <&pd_isp>;
261 clocks = <&clock CLK_FIMC_LITE1>;
262 clock-names = "flite";
263 iommus = <&sysmmu_fimc_lite1>;
264 status = "disabled";
265 };
266
267 fimc_is: fimc-is@12000000 {
268 compatible = "samsung,exynos4212-fimc-is";
269 reg = <0x12000000 0x260000>;
270 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
272 power-domains = <&pd_isp>;
273 clocks = <&clock CLK_FIMC_LITE0>,
274 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
275 <&clock CLK_PPMUISPMX>,
276 <&clock CLK_MOUT_MPLL_USER_T>,
277 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
278 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
279 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
280 <&clock CLK_PWM_ISP>,
281 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
282 <&clock CLK_DIV_MCUISP0>,
283 <&clock CLK_DIV_MCUISP1>,
284 <&clock CLK_UART_ISP_SCLK>,
285 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
286 <&clock CLK_ACLK400_MCUISP>,
287 <&clock CLK_DIV_ACLK400_MCUISP>;
288 clock-names = "lite0", "lite1", "ppmuispx",
289 "ppmuispmx", "mpll", "isp",
290 "drc", "fd", "mcuisp",
291 "gicisp", "mcuctl_isp", "pwm_isp",
292 "ispdiv0", "ispdiv1", "mcuispdiv0",
293 "mcuispdiv1", "uart", "aclk200",
294 "div_aclk200", "aclk400mcuisp",
295 "div_aclk400mcuisp";
296 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
297 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
298 iommu-names = "isp", "drc", "fd", "mcuctl";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges;
302 status = "disabled";
303
304 pmu@10020000 {
305 reg = <0x10020000 0x3000>;
306 };
307
308 i2c1_isp: i2c-isp@12140000 {
309 compatible = "samsung,exynos4212-i2c-isp";
310 reg = <0x12140000 0x100>;
311 clocks = <&clock CLK_I2C1_ISP>;
312 clock-names = "i2c_isp";
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317 };
318
319 mshc_0: mmc@12550000 {
320 compatible = "samsung,exynos4412-dw-mshc";
321 reg = <0x12550000 0x1000>;
322 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 fifo-depth = <0x80>;
326 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
327 clock-names = "biu", "ciu";
328 status = "disabled";
329 };
330
331 sysmmu_g2d: sysmmu@10A40000{
332 compatible = "samsung,exynos-sysmmu";
333 reg = <0x10A40000 0x1000>;
334 interrupt-parent = <&combiner>;
335 interrupts = <4 7>;
336 clock-names = "sysmmu", "master";
337 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
338 #iommu-cells = <0>;
339 };
340
341 sysmmu_fimc_isp: sysmmu@12260000 {
342 compatible = "samsung,exynos-sysmmu";
343 reg = <0x12260000 0x1000>;
344 interrupt-parent = <&combiner>;
345 interrupts = <16 2>;
346 power-domains = <&pd_isp>;
347 clock-names = "sysmmu";
348 clocks = <&clock CLK_SMMU_ISP>;
349 #iommu-cells = <0>;
350 };
351
352 sysmmu_fimc_drc: sysmmu@12270000 {
353 compatible = "samsung,exynos-sysmmu";
354 reg = <0x12270000 0x1000>;
355 interrupt-parent = <&combiner>;
356 interrupts = <16 3>;
357 power-domains = <&pd_isp>;
358 clock-names = "sysmmu";
359 clocks = <&clock CLK_SMMU_DRC>;
360 #iommu-cells = <0>;
361 };
362
363 sysmmu_fimc_fd: sysmmu@122A0000 {
364 compatible = "samsung,exynos-sysmmu";
365 reg = <0x122A0000 0x1000>;
366 interrupt-parent = <&combiner>;
367 interrupts = <16 4>;
368 power-domains = <&pd_isp>;
369 clock-names = "sysmmu";
370 clocks = <&clock CLK_SMMU_FD>;
371 #iommu-cells = <0>;
372 };
373
374 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
375 compatible = "samsung,exynos-sysmmu";
376 reg = <0x122B0000 0x1000>;
377 interrupt-parent = <&combiner>;
378 interrupts = <16 5>;
379 power-domains = <&pd_isp>;
380 clock-names = "sysmmu";
381 clocks = <&clock CLK_SMMU_ISPCX>;
382 #iommu-cells = <0>;
383 };
384
385 sysmmu_fimc_lite0: sysmmu@123B0000 {
386 compatible = "samsung,exynos-sysmmu";
387 reg = <0x123B0000 0x1000>;
388 interrupt-parent = <&combiner>;
389 interrupts = <16 0>;
390 power-domains = <&pd_isp>;
391 clock-names = "sysmmu", "master";
392 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
393 #iommu-cells = <0>;
394 };
395
396 sysmmu_fimc_lite1: sysmmu@123C0000 {
397 compatible = "samsung,exynos-sysmmu";
398 reg = <0x123C0000 0x1000>;
399 interrupt-parent = <&combiner>;
400 interrupts = <16 1>;
401 power-domains = <&pd_isp>;
402 clock-names = "sysmmu", "master";
403 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
404 #iommu-cells = <0>;
405 };
406
407 bus_dmc: bus_dmc {
408 compatible = "samsung,exynos-bus";
409 clocks = <&clock CLK_DIV_DMC>;
410 clock-names = "bus";
411 operating-points-v2 = <&bus_dmc_opp_table>;
412 status = "disabled";
413 };
414
415 bus_acp: bus_acp {
416 compatible = "samsung,exynos-bus";
417 clocks = <&clock CLK_DIV_ACP>;
418 clock-names = "bus";
419 operating-points-v2 = <&bus_acp_opp_table>;
420 status = "disabled";
421 };
422
423 bus_c2c: bus_c2c {
424 compatible = "samsung,exynos-bus";
425 clocks = <&clock CLK_DIV_C2C>;
426 clock-names = "bus";
427 operating-points-v2 = <&bus_dmc_opp_table>;
428 status = "disabled";
429 };
430
431 bus_dmc_opp_table: opp_table1 {
432 compatible = "operating-points-v2";
433 opp-shared;
434
435 opp@100000000 {
436 opp-hz = /bits/ 64 <100000000>;
437 opp-microvolt = <900000>;
438 };
439 opp@134000000 {
440 opp-hz = /bits/ 64 <134000000>;
441 opp-microvolt = <900000>;
442 };
443 opp@160000000 {
444 opp-hz = /bits/ 64 <160000000>;
445 opp-microvolt = <900000>;
446 };
447 opp@267000000 {
448 opp-hz = /bits/ 64 <267000000>;
449 opp-microvolt = <950000>;
450 };
451 opp@400000000 {
452 opp-hz = /bits/ 64 <400000000>;
453 opp-microvolt = <1050000>;
454 };
455 };
456
457 bus_acp_opp_table: opp_table2 {
458 compatible = "operating-points-v2";
459 opp-shared;
460
461 opp@100000000 {
462 opp-hz = /bits/ 64 <100000000>;
463 };
464 opp@134000000 {
465 opp-hz = /bits/ 64 <134000000>;
466 };
467 opp@160000000 {
468 opp-hz = /bits/ 64 <160000000>;
469 };
470 opp@267000000 {
471 opp-hz = /bits/ 64 <267000000>;
472 };
473 };
474
475 bus_leftbus: bus_leftbus {
476 compatible = "samsung,exynos-bus";
477 clocks = <&clock CLK_DIV_GDL>;
478 clock-names = "bus";
479 operating-points-v2 = <&bus_leftbus_opp_table>;
480 status = "disabled";
481 };
482
483 bus_rightbus: bus_rightbus {
484 compatible = "samsung,exynos-bus";
485 clocks = <&clock CLK_DIV_GDR>;
486 clock-names = "bus";
487 operating-points-v2 = <&bus_leftbus_opp_table>;
488 status = "disabled";
489 };
490
491 bus_display: bus_display {
492 compatible = "samsung,exynos-bus";
493 clocks = <&clock CLK_ACLK160>;
494 clock-names = "bus";
495 operating-points-v2 = <&bus_display_opp_table>;
496 status = "disabled";
497 };
498
499 bus_fsys: bus_fsys {
500 compatible = "samsung,exynos-bus";
501 clocks = <&clock CLK_ACLK133>;
502 clock-names = "bus";
503 operating-points-v2 = <&bus_fsys_opp_table>;
504 status = "disabled";
505 };
506
507 bus_peri: bus_peri {
508 compatible = "samsung,exynos-bus";
509 clocks = <&clock CLK_ACLK100>;
510 clock-names = "bus";
511 operating-points-v2 = <&bus_peri_opp_table>;
512 status = "disabled";
513 };
514
515 bus_mfc: bus_mfc {
516 compatible = "samsung,exynos-bus";
517 clocks = <&clock CLK_SCLK_MFC>;
518 clock-names = "bus";
519 operating-points-v2 = <&bus_leftbus_opp_table>;
520 status = "disabled";
521 };
522
523 bus_leftbus_opp_table: opp_table3 {
524 compatible = "operating-points-v2";
525 opp-shared;
526
527 opp@100000000 {
528 opp-hz = /bits/ 64 <100000000>;
529 opp-microvolt = <900000>;
530 };
531 opp@134000000 {
532 opp-hz = /bits/ 64 <134000000>;
533 opp-microvolt = <925000>;
534 };
535 opp@160000000 {
536 opp-hz = /bits/ 64 <160000000>;
537 opp-microvolt = <950000>;
538 };
539 opp@200000000 {
540 opp-hz = /bits/ 64 <200000000>;
541 opp-microvolt = <1000000>;
542 };
543 };
544
545 bus_display_opp_table: opp_table4 {
546 compatible = "operating-points-v2";
547 opp-shared;
548
549 opp@160000000 {
550 opp-hz = /bits/ 64 <160000000>;
551 };
552 opp@200000000 {
553 opp-hz = /bits/ 64 <200000000>;
554 };
555 };
556
557 bus_fsys_opp_table: opp_table5 {
558 compatible = "operating-points-v2";
559 opp-shared;
560
561 opp@100000000 {
562 opp-hz = /bits/ 64 <100000000>;
563 };
564 opp@134000000 {
565 opp-hz = /bits/ 64 <134000000>;
566 };
567 };
568
569 bus_peri_opp_table: opp_table6 {
570 compatible = "operating-points-v2";
571 opp-shared;
572
573 opp@50000000 {
574 opp-hz = /bits/ 64 <50000000>;
575 };
576 opp@100000000 {
577 opp-hz = /bits/ 64 <100000000>;
578 };
579 };
580
141 pmu { 581 pmu {
142 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 582 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
143 }; 583 };
144}; 584};
145 585
146&pmu_system_controller {
147 compatible = "samsung,exynos4412-pmu", "syscon";
148};
149
150&combiner { 586&combiner {
151 samsung,combiner-nr = <20>; 587 samsung,combiner-nr = <20>;
588 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
608};
609
610&exynos_usbphy {
611 compatible = "samsung,exynos4x12-usb2-phy";
612 samsung,sysreg-phandle = <&sys_reg>;
613};
614
615&fimc_0 {
616 compatible = "samsung,exynos4212-fimc";
617 samsung,pix-limits = <4224 8192 1920 4224>;
618 samsung,mainscaler-ext;
619 samsung,isp-wb;
620 samsung,cam-if;
621};
622
623&fimc_1 {
624 compatible = "samsung,exynos4212-fimc";
625 samsung,pix-limits = <4224 8192 1920 4224>;
626 samsung,mainscaler-ext;
627 samsung,isp-wb;
628 samsung,cam-if;
629};
630
631&fimc_2 {
632 compatible = "samsung,exynos4212-fimc";
633 samsung,pix-limits = <4224 8192 1920 4224>;
634 samsung,mainscaler-ext;
635 samsung,isp-wb;
636 samsung,lcd-wb;
637 samsung,cam-if;
638};
639
640&fimc_3 {
641 compatible = "samsung,exynos4212-fimc";
642 samsung,pix-limits = <1920 8192 1366 1920>;
643 samsung,rotators = <0>;
644 samsung,mainscaler-ext;
645 samsung,isp-wb;
646 samsung,lcd-wb;
152}; 647};
153 648
154&gic { 649&gic {
155 cpu-offset = <0x4000>; 650 cpu-offset = <0x4000>;
156}; 651};
652
653&hdmi {
654 compatible = "samsung,exynos4212-hdmi";
655};
656
657&jpeg_codec {
658 compatible = "samsung,exynos4212-jpeg";
659};
660
661&rotator {
662 compatible = "samsung,exynos4212-rotator";
663};
664
665&mixer {
666 compatible = "samsung,exynos4212-mixer";
667 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
668 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
669 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
670};
671
672&pinctrl_0 {
673 compatible = "samsung,exynos4x12-pinctrl";
674 reg = <0x11400000 0x1000>;
675 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
676};
677
678&pinctrl_1 {
679 compatible = "samsung,exynos4x12-pinctrl";
680 reg = <0x11000000 0x1000>;
681 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
682
683 wakup_eint: wakeup-interrupt-controller {
684 compatible = "samsung,exynos4210-wakeup-eint";
685 interrupt-parent = <&gic>;
686 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
687 };
688};
689
690&pinctrl_2 {
691 compatible = "samsung,exynos4x12-pinctrl";
692 reg = <0x03860000 0x1000>;
693 interrupt-parent = <&combiner>;
694 interrupts = <10 0>;
695};
696
697&pinctrl_3 {
698 compatible = "samsung,exynos4x12-pinctrl";
699 reg = <0x106E0000 0x1000>;
700 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
701};
702
703&pmu_system_controller {
704 compatible = "samsung,exynos4412-pmu", "syscon";
705 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
706 "clkout4", "clkout8", "clkout9";
707 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
708 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
709 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
710 #clock-cells = <1>;
711};
712
713&tmu {
714 compatible = "samsung,exynos4412-tmu";
715 interrupt-parent = <&combiner>;
716 interrupts = <2 4>;
717 reg = <0x100C0000 0x100>;
718 clocks = <&clock 383>;
719 clock-names = "tmu_apbif";
720 status = "disabled";
721};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
deleted file mode 100644
index 85a7122658f1..000000000000
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ /dev/null
@@ -1,594 +0,0 @@
1/*
2 * Samsung's Exynos4x12 SoCs device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include "exynos4.dtsi"
21#include "exynos4x12-pinctrl.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
23
24/ {
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 pinctrl3 = &pinctrl_3;
30 fimc-lite0 = &fimc_lite_0;
31 fimc-lite1 = &fimc_lite_1;
32 mshc0 = &mshc_0;
33 };
34
35 sysram@02020000 {
36 compatible = "mmio-sram";
37 reg = <0x02020000 0x40000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges = <0 0x02020000 0x40000>;
41
42 smp-sysram@0 {
43 compatible = "samsung,exynos4210-sysram";
44 reg = <0x0 0x1000>;
45 };
46
47 smp-sysram@2f000 {
48 compatible = "samsung,exynos4210-sysram-ns";
49 reg = <0x2f000 0x1000>;
50 };
51 };
52
53 pd_isp: isp-power-domain@10023CA0 {
54 compatible = "samsung,exynos4210-pd";
55 reg = <0x10023CA0 0x20>;
56 #power-domain-cells = <0>;
57 };
58
59 l2c: l2-cache-controller@10502000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10502000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 arm,tag-latency = <2 2 1>;
65 arm,data-latency = <3 2 1>;
66 arm,double-linefill = <1>;
67 arm,double-linefill-incr = <0>;
68 arm,double-linefill-wrap = <1>;
69 arm,prefetch-drop = <1>;
70 arm,prefetch-offset = <7>;
71 };
72
73 clock: clock-controller@10030000 {
74 compatible = "samsung,exynos4412-clock";
75 reg = <0x10030000 0x20000>;
76 #clock-cells = <1>;
77 };
78
79 mct@10050000 {
80 compatible = "samsung,exynos4412-mct";
81 reg = <0x10050000 0x800>;
82 interrupt-parent = <&mct_map>;
83 interrupts = <0>, <1>, <2>, <3>, <4>;
84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85 clock-names = "fin_pll", "mct";
86
87 mct_map: mct-map {
88 #interrupt-cells = <1>;
89 #address-cells = <0>;
90 #size-cells = <0>;
91 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
92 <1 &combiner 12 5>,
93 <2 &combiner 12 6>,
94 <3 &combiner 12 7>,
95 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
96 };
97 };
98
99 adc: adc@126C0000 {
100 compatible = "samsung,exynos-adc-v1";
101 reg = <0x126C0000 0x100>;
102 interrupt-parent = <&combiner>;
103 interrupts = <10 3>;
104 clocks = <&clock CLK_TSADC>;
105 clock-names = "adc";
106 #io-channel-cells = <1>;
107 io-channel-ranges;
108 samsung,syscon-phandle = <&pmu_system_controller>;
109 status = "disabled";
110 };
111
112 g2d: g2d@10800000 {
113 compatible = "samsung,exynos4212-g2d";
114 reg = <0x10800000 0x1000>;
115 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
117 clock-names = "sclk_fimg2d", "fimg2d";
118 iommus = <&sysmmu_g2d>;
119 };
120
121 camera {
122 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
123 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
124 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
125
126 /* fimc_[0-3] are configured outside, under phandles */
127 fimc_lite_0: fimc-lite@12390000 {
128 compatible = "samsung,exynos4212-fimc-lite";
129 reg = <0x12390000 0x1000>;
130 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
131 power-domains = <&pd_isp>;
132 clocks = <&clock CLK_FIMC_LITE0>;
133 clock-names = "flite";
134 iommus = <&sysmmu_fimc_lite0>;
135 status = "disabled";
136 };
137
138 fimc_lite_1: fimc-lite@123A0000 {
139 compatible = "samsung,exynos4212-fimc-lite";
140 reg = <0x123A0000 0x1000>;
141 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
142 power-domains = <&pd_isp>;
143 clocks = <&clock CLK_FIMC_LITE1>;
144 clock-names = "flite";
145 iommus = <&sysmmu_fimc_lite1>;
146 status = "disabled";
147 };
148
149 fimc_is: fimc-is@12000000 {
150 compatible = "samsung,exynos4212-fimc-is";
151 reg = <0x12000000 0x260000>;
152 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
154 power-domains = <&pd_isp>;
155 clocks = <&clock CLK_FIMC_LITE0>,
156 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
157 <&clock CLK_PPMUISPMX>,
158 <&clock CLK_MOUT_MPLL_USER_T>,
159 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
160 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
161 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
162 <&clock CLK_PWM_ISP>,
163 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
164 <&clock CLK_DIV_MCUISP0>,
165 <&clock CLK_DIV_MCUISP1>,
166 <&clock CLK_UART_ISP_SCLK>,
167 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
168 <&clock CLK_ACLK400_MCUISP>,
169 <&clock CLK_DIV_ACLK400_MCUISP>;
170 clock-names = "lite0", "lite1", "ppmuispx",
171 "ppmuispmx", "mpll", "isp",
172 "drc", "fd", "mcuisp",
173 "gicisp", "mcuctl_isp", "pwm_isp",
174 "ispdiv0", "ispdiv1", "mcuispdiv0",
175 "mcuispdiv1", "uart", "aclk200",
176 "div_aclk200", "aclk400mcuisp",
177 "div_aclk400mcuisp";
178 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
179 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
180 iommu-names = "isp", "drc", "fd", "mcuctl";
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
184 status = "disabled";
185
186 pmu@10020000 {
187 reg = <0x10020000 0x3000>;
188 };
189
190 i2c1_isp: i2c-isp@12140000 {
191 compatible = "samsung,exynos4212-i2c-isp";
192 reg = <0x12140000 0x100>;
193 clocks = <&clock CLK_I2C1_ISP>;
194 clock-names = "i2c_isp";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198 };
199 };
200
201 mshc_0: mmc@12550000 {
202 compatible = "samsung,exynos4412-dw-mshc";
203 reg = <0x12550000 0x1000>;
204 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 fifo-depth = <0x80>;
208 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
209 clock-names = "biu", "ciu";
210 status = "disabled";
211 };
212
213 sysmmu_g2d: sysmmu@10A40000{
214 compatible = "samsung,exynos-sysmmu";
215 reg = <0x10A40000 0x1000>;
216 interrupt-parent = <&combiner>;
217 interrupts = <4 7>;
218 clock-names = "sysmmu", "master";
219 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
220 #iommu-cells = <0>;
221 };
222
223 sysmmu_fimc_isp: sysmmu@12260000 {
224 compatible = "samsung,exynos-sysmmu";
225 reg = <0x12260000 0x1000>;
226 interrupt-parent = <&combiner>;
227 interrupts = <16 2>;
228 power-domains = <&pd_isp>;
229 clock-names = "sysmmu";
230 clocks = <&clock CLK_SMMU_ISP>;
231 #iommu-cells = <0>;
232 };
233
234 sysmmu_fimc_drc: sysmmu@12270000 {
235 compatible = "samsung,exynos-sysmmu";
236 reg = <0x12270000 0x1000>;
237 interrupt-parent = <&combiner>;
238 interrupts = <16 3>;
239 power-domains = <&pd_isp>;
240 clock-names = "sysmmu";
241 clocks = <&clock CLK_SMMU_DRC>;
242 #iommu-cells = <0>;
243 };
244
245 sysmmu_fimc_fd: sysmmu@122A0000 {
246 compatible = "samsung,exynos-sysmmu";
247 reg = <0x122A0000 0x1000>;
248 interrupt-parent = <&combiner>;
249 interrupts = <16 4>;
250 power-domains = <&pd_isp>;
251 clock-names = "sysmmu";
252 clocks = <&clock CLK_SMMU_FD>;
253 #iommu-cells = <0>;
254 };
255
256 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
257 compatible = "samsung,exynos-sysmmu";
258 reg = <0x122B0000 0x1000>;
259 interrupt-parent = <&combiner>;
260 interrupts = <16 5>;
261 power-domains = <&pd_isp>;
262 clock-names = "sysmmu";
263 clocks = <&clock CLK_SMMU_ISPCX>;
264 #iommu-cells = <0>;
265 };
266
267 sysmmu_fimc_lite0: sysmmu@123B0000 {
268 compatible = "samsung,exynos-sysmmu";
269 reg = <0x123B0000 0x1000>;
270 interrupt-parent = <&combiner>;
271 interrupts = <16 0>;
272 power-domains = <&pd_isp>;
273 clock-names = "sysmmu", "master";
274 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
275 #iommu-cells = <0>;
276 };
277
278 sysmmu_fimc_lite1: sysmmu@123C0000 {
279 compatible = "samsung,exynos-sysmmu";
280 reg = <0x123C0000 0x1000>;
281 interrupt-parent = <&combiner>;
282 interrupts = <16 1>;
283 power-domains = <&pd_isp>;
284 clock-names = "sysmmu", "master";
285 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
286 #iommu-cells = <0>;
287 };
288
289 bus_dmc: bus_dmc {
290 compatible = "samsung,exynos-bus";
291 clocks = <&clock CLK_DIV_DMC>;
292 clock-names = "bus";
293 operating-points-v2 = <&bus_dmc_opp_table>;
294 status = "disabled";
295 };
296
297 bus_acp: bus_acp {
298 compatible = "samsung,exynos-bus";
299 clocks = <&clock CLK_DIV_ACP>;
300 clock-names = "bus";
301 operating-points-v2 = <&bus_acp_opp_table>;
302 status = "disabled";
303 };
304
305 bus_c2c: bus_c2c {
306 compatible = "samsung,exynos-bus";
307 clocks = <&clock CLK_DIV_C2C>;
308 clock-names = "bus";
309 operating-points-v2 = <&bus_dmc_opp_table>;
310 status = "disabled";
311 };
312
313 bus_dmc_opp_table: opp_table1 {
314 compatible = "operating-points-v2";
315 opp-shared;
316
317 opp@100000000 {
318 opp-hz = /bits/ 64 <100000000>;
319 opp-microvolt = <900000>;
320 };
321 opp@134000000 {
322 opp-hz = /bits/ 64 <134000000>;
323 opp-microvolt = <900000>;
324 };
325 opp@160000000 {
326 opp-hz = /bits/ 64 <160000000>;
327 opp-microvolt = <900000>;
328 };
329 opp@267000000 {
330 opp-hz = /bits/ 64 <267000000>;
331 opp-microvolt = <950000>;
332 };
333 opp@400000000 {
334 opp-hz = /bits/ 64 <400000000>;
335 opp-microvolt = <1050000>;
336 };
337 };
338
339 bus_acp_opp_table: opp_table2 {
340 compatible = "operating-points-v2";
341 opp-shared;
342
343 opp@100000000 {
344 opp-hz = /bits/ 64 <100000000>;
345 };
346 opp@134000000 {
347 opp-hz = /bits/ 64 <134000000>;
348 };
349 opp@160000000 {
350 opp-hz = /bits/ 64 <160000000>;
351 };
352 opp@267000000 {
353 opp-hz = /bits/ 64 <267000000>;
354 };
355 };
356
357 bus_leftbus: bus_leftbus {
358 compatible = "samsung,exynos-bus";
359 clocks = <&clock CLK_DIV_GDL>;
360 clock-names = "bus";
361 operating-points-v2 = <&bus_leftbus_opp_table>;
362 status = "disabled";
363 };
364
365 bus_rightbus: bus_rightbus {
366 compatible = "samsung,exynos-bus";
367 clocks = <&clock CLK_DIV_GDR>;
368 clock-names = "bus";
369 operating-points-v2 = <&bus_leftbus_opp_table>;
370 status = "disabled";
371 };
372
373 bus_display: bus_display {
374 compatible = "samsung,exynos-bus";
375 clocks = <&clock CLK_ACLK160>;
376 clock-names = "bus";
377 operating-points-v2 = <&bus_display_opp_table>;
378 status = "disabled";
379 };
380
381 bus_fsys: bus_fsys {
382 compatible = "samsung,exynos-bus";
383 clocks = <&clock CLK_ACLK133>;
384 clock-names = "bus";
385 operating-points-v2 = <&bus_fsys_opp_table>;
386 status = "disabled";
387 };
388
389 bus_peri: bus_peri {
390 compatible = "samsung,exynos-bus";
391 clocks = <&clock CLK_ACLK100>;
392 clock-names = "bus";
393 operating-points-v2 = <&bus_peri_opp_table>;
394 status = "disabled";
395 };
396
397 bus_mfc: bus_mfc {
398 compatible = "samsung,exynos-bus";
399 clocks = <&clock CLK_SCLK_MFC>;
400 clock-names = "bus";
401 operating-points-v2 = <&bus_leftbus_opp_table>;
402 status = "disabled";
403 };
404
405 bus_leftbus_opp_table: opp_table3 {
406 compatible = "operating-points-v2";
407 opp-shared;
408
409 opp@100000000 {
410 opp-hz = /bits/ 64 <100000000>;
411 opp-microvolt = <900000>;
412 };
413 opp@134000000 {
414 opp-hz = /bits/ 64 <134000000>;
415 opp-microvolt = <925000>;
416 };
417 opp@160000000 {
418 opp-hz = /bits/ 64 <160000000>;
419 opp-microvolt = <950000>;
420 };
421 opp@200000000 {
422 opp-hz = /bits/ 64 <200000000>;
423 opp-microvolt = <1000000>;
424 };
425 };
426
427 bus_display_opp_table: opp_table4 {
428 compatible = "operating-points-v2";
429 opp-shared;
430
431 opp@160000000 {
432 opp-hz = /bits/ 64 <160000000>;
433 };
434 opp@200000000 {
435 opp-hz = /bits/ 64 <200000000>;
436 };
437 };
438
439 bus_fsys_opp_table: opp_table5 {
440 compatible = "operating-points-v2";
441 opp-shared;
442
443 opp@100000000 {
444 opp-hz = /bits/ 64 <100000000>;
445 };
446 opp@134000000 {
447 opp-hz = /bits/ 64 <134000000>;
448 };
449 };
450
451 bus_peri_opp_table: opp_table6 {
452 compatible = "operating-points-v2";
453 opp-shared;
454
455 opp@50000000 {
456 opp-hz = /bits/ 64 <50000000>;
457 };
458 opp@100000000 {
459 opp-hz = /bits/ 64 <100000000>;
460 };
461 };
462};
463
464&combiner {
465 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
485};
486
487&exynos_usbphy {
488 compatible = "samsung,exynos4x12-usb2-phy";
489 samsung,sysreg-phandle = <&sys_reg>;
490};
491
492&fimc_0 {
493 compatible = "samsung,exynos4212-fimc";
494 samsung,pix-limits = <4224 8192 1920 4224>;
495 samsung,mainscaler-ext;
496 samsung,isp-wb;
497 samsung,cam-if;
498};
499
500&fimc_1 {
501 compatible = "samsung,exynos4212-fimc";
502 samsung,pix-limits = <4224 8192 1920 4224>;
503 samsung,mainscaler-ext;
504 samsung,isp-wb;
505 samsung,cam-if;
506};
507
508&fimc_2 {
509 compatible = "samsung,exynos4212-fimc";
510 samsung,pix-limits = <4224 8192 1920 4224>;
511 samsung,mainscaler-ext;
512 samsung,isp-wb;
513 samsung,lcd-wb;
514 samsung,cam-if;
515};
516
517&fimc_3 {
518 compatible = "samsung,exynos4212-fimc";
519 samsung,pix-limits = <1920 8192 1366 1920>;
520 samsung,rotators = <0>;
521 samsung,mainscaler-ext;
522 samsung,isp-wb;
523 samsung,lcd-wb;
524};
525
526&hdmi {
527 compatible = "samsung,exynos4212-hdmi";
528};
529
530&jpeg_codec {
531 compatible = "samsung,exynos4212-jpeg";
532};
533
534&rotator {
535 compatible = "samsung,exynos4212-rotator";
536};
537
538&mixer {
539 compatible = "samsung,exynos4212-mixer";
540 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
541 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
542 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
543};
544
545&pinctrl_0 {
546 compatible = "samsung,exynos4x12-pinctrl";
547 reg = <0x11400000 0x1000>;
548 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
549};
550
551&pinctrl_1 {
552 compatible = "samsung,exynos4x12-pinctrl";
553 reg = <0x11000000 0x1000>;
554 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
555
556 wakup_eint: wakeup-interrupt-controller {
557 compatible = "samsung,exynos4210-wakeup-eint";
558 interrupt-parent = <&gic>;
559 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
560 };
561};
562
563&pinctrl_2 {
564 compatible = "samsung,exynos4x12-pinctrl";
565 reg = <0x03860000 0x1000>;
566 interrupt-parent = <&combiner>;
567 interrupts = <10 0>;
568};
569
570&pinctrl_3 {
571 compatible = "samsung,exynos4x12-pinctrl";
572 reg = <0x106E0000 0x1000>;
573 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
574};
575
576&pmu_system_controller {
577 compatible = "samsung,exynos4212-pmu", "syscon";
578 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
579 "clkout4", "clkout8", "clkout9";
580 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
581 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
582 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
583 #clock-cells = <1>;
584};
585
586&tmu {
587 compatible = "samsung,exynos4412-tmu";
588 interrupt-parent = <&combiner>;
589 interrupts = <2 4>;
590 reg = <0x100C0000 0x100>;
591 clocks = <&clock 383>;
592 clock-names = "tmu_apbif";
593 status = "disabled";
594};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 05:15:39 -0400