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authorJon Hunter <jonathanh@nvidia.com>2016-02-15 07:38:11 -0500
committerThierry Reding <treding@nvidia.com>2016-04-05 09:22:51 -0400
commitbc9af23d314f5c846e66e9425b31df2815ef1763 (patch)
tree8b686783acdba347424215fc6e39857d0a1bfa6c
parentc3ea297260b77a99a2383c1029a381d125f788fe (diff)
soc/tegra: pmc: Ensure GPU partition can be toggled on/off by PMC
For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the partition is simply powered up and down via an external regulator. For these devices, there is a separate register for controlling the signal clamping of the partition and this is described in the PMC SoC data by the "has_gpu_clamp" variable. Use this variable to determine if the GPU partition can be controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that no one can incorrectly try to toggle the GPU partition via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. Furthermore, we cannot use the APBDEV_PMC_PWRGATE_STATUS_0 register to determine if the GPU partition is powered for Tegra124 and Tegra210. However, if the GPU partition is powered, then the signal clamp for the GPU partition should be removed and so use bit 0 of the APBDEV_PMC_GPU_RG_CNTRL_0 register to determine if the clamp has been removed (bit[0] = 0) and the GPU partition is powered. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/soc/tegra/pmc.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 8e358dbffaed..e4fd40fa27e8 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -176,7 +176,10 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
176 176
177static inline bool tegra_powergate_state(int id) 177static inline bool tegra_powergate_state(int id)
178{ 178{
179 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 179 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
180 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
181 else
182 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
180} 183}
181 184
182static inline bool tegra_powergate_is_valid(int id) 185static inline bool tegra_powergate_is_valid(int id)
@@ -191,6 +194,9 @@ static inline bool tegra_powergate_is_valid(int id)
191 */ 194 */
192static int tegra_powergate_set(unsigned int id, bool new_state) 195static int tegra_powergate_set(unsigned int id, bool new_state)
193{ 196{
197 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
198 return -EINVAL;
199
194 mutex_lock(&pmc->powergates_lock); 200 mutex_lock(&pmc->powergates_lock);
195 201
196 if (tegra_powergate_state(id) == new_state) { 202 if (tegra_powergate_state(id) == new_state) {