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authorPhilipp Zabel <p.zabel@pengutronix.de>2017-06-12 14:23:54 -0400
committerShawn Guo <shawnguo@kernel.org>2017-06-14 11:06:02 -0400
commitbc97e88ecd360a730b0f9c96f285b680be496e06 (patch)
tree78c0add3d9a362af8107a277c54dc589cc761b59
parentcc20028f68e760d6958e892aba1f9bafbce63e22 (diff)
ARM: dts: imx6qdl: add multiplexer controls
The IOMUXC General Purpose Register space contains various bitfields that control video bus multiplexers. Describe them using a mmio-mux node. The placement of the IPU CSI video mux controls differs between i.MX6D/Q and i.MX6S/DL. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi10
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi10
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi7
3 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 7aa120fbdc71..10bc9d135956 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -181,6 +181,16 @@
181 "di0", "di1"; 181 "di0", "di1";
182}; 182};
183 183
184&mux {
185 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
186 <0x34 0x00000038>, /* IPU_CSI1_MUX */
187 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
188 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
189 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
190 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
191 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
192};
193
184&vpu { 194&vpu {
185 compatible = "fsl,imx6dl-vpu", "cnm,coda960"; 195 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
186}; 196};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index dd33849335b2..1a14ae2ce6d8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -332,6 +332,16 @@
332 }; 332 };
333}; 333};
334 334
335&mux {
336 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
337 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
338 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
339 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
340 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
341 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
342 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
343};
344
335&vpu { 345&vpu {
336 compatible = "fsl,imx6q-vpu", "cnm,coda960"; 346 compatible = "fsl,imx6q-vpu", "cnm,coda960";
337}; 347};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index f325411f66aa..4ea7d86e625e 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -826,8 +826,13 @@
826 }; 826 };
827 827
828 gpr: iomuxc-gpr@020e0000 { 828 gpr: iomuxc-gpr@020e0000 {
829 compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; 829 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
830 reg = <0x020e0000 0x38>; 830 reg = <0x020e0000 0x38>;
831
832 mux: mux-controller {
833 compatible = "mmio-mux";
834 #mux-control-cells = <1>;
835 };
831 }; 836 };
832 837
833 iomuxc: iomuxc@020e0000 { 838 iomuxc: iomuxc@020e0000 {