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authorMatthew McClintock <mmcclint@codeaurora.org>2016-03-23 18:04:59 -0400
committerStephen Boyd <sboyd@codeaurora.org>2016-03-29 19:31:11 -0400
commitbc95d4f0a920150e77083c2946fe7b7d2f6e217c (patch)
treebbbb6b7479079421a35b665628ae931bbf570093
parentadd479eeb1a208a31ab913ae7c97506a81383079 (diff)
clk: qcom: ipq4019: switch remaining defines to enums
When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r--drivers/clk/qcom/gcc-ipq4019.c60
1 files changed, 25 insertions, 35 deletions
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 5428efb9fbf5..3599ade11b0c 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -129,20 +129,10 @@ static const char * const gcc_xo_ddr_500_200[] = {
129}; 129};
130 130
131#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 131#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
132#define P_XO 0
133#define FE_PLL_200 1
134#define FE_PLL_500 2
135#define DDRC_PLL_666 3
136
137#define DDRC_PLL_666_SDCC 1
138#define FE_PLL_125_DLY 1
139
140#define FE_PLL_WCSS2G 1
141#define FE_PLL_WCSS5G 1
142 132
143static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { 133static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
144 F(48000000, P_XO, 1, 0, 0), 134 F(48000000, P_XO, 1, 0, 0),
145 F(200000000, FE_PLL_200, 1, 0, 0), 135 F(200000000, P_FEPLL200, 1, 0, 0),
146 { } 136 { }
147}; 137};
148 138
@@ -334,15 +324,15 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
334}; 324};
335 325
336static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = { 326static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
337 F(1843200, FE_PLL_200, 1, 144, 15625), 327 F(1843200, P_FEPLL200, 1, 144, 15625),
338 F(3686400, FE_PLL_200, 1, 288, 15625), 328 F(3686400, P_FEPLL200, 1, 288, 15625),
339 F(7372800, FE_PLL_200, 1, 576, 15625), 329 F(7372800, P_FEPLL200, 1, 576, 15625),
340 F(14745600, FE_PLL_200, 1, 1152, 15625), 330 F(14745600, P_FEPLL200, 1, 1152, 15625),
341 F(16000000, FE_PLL_200, 1, 2, 25), 331 F(16000000, P_FEPLL200, 1, 2, 25),
342 F(24000000, P_XO, 1, 1, 2), 332 F(24000000, P_XO, 1, 1, 2),
343 F(32000000, FE_PLL_200, 1, 4, 25), 333 F(32000000, P_FEPLL200, 1, 4, 25),
344 F(40000000, FE_PLL_200, 1, 1, 5), 334 F(40000000, P_FEPLL200, 1, 1, 5),
345 F(46400000, FE_PLL_200, 1, 29, 125), 335 F(46400000, P_FEPLL200, 1, 29, 125),
346 F(48000000, P_XO, 1, 0, 0), 336 F(48000000, P_XO, 1, 0, 0),
347 { } 337 { }
348}; 338};
@@ -410,9 +400,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
410}; 400};
411 401
412static const struct freq_tbl ftbl_gcc_gp_clk[] = { 402static const struct freq_tbl ftbl_gcc_gp_clk[] = {
413 F(1250000, FE_PLL_200, 1, 16, 0), 403 F(1250000, P_FEPLL200, 1, 16, 0),
414 F(2500000, FE_PLL_200, 1, 8, 0), 404 F(2500000, P_FEPLL200, 1, 8, 0),
415 F(5000000, FE_PLL_200, 1, 4, 0), 405 F(5000000, P_FEPLL200, 1, 4, 0),
416 { } 406 { }
417}; 407};
418 408
@@ -512,11 +502,11 @@ static struct clk_branch gcc_gp3_clk = {
512static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 502static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
513 F(144000, P_XO, 1, 3, 240), 503 F(144000, P_XO, 1, 3, 240),
514 F(400000, P_XO, 1, 1, 0), 504 F(400000, P_XO, 1, 1, 0),
515 F(20000000, FE_PLL_500, 1, 1, 25), 505 F(20000000, P_FEPLL500, 1, 1, 25),
516 F(25000000, FE_PLL_500, 1, 1, 20), 506 F(25000000, P_FEPLL500, 1, 1, 20),
517 F(50000000, FE_PLL_500, 1, 1, 10), 507 F(50000000, P_FEPLL500, 1, 1, 10),
518 F(100000000, FE_PLL_500, 1, 1, 5), 508 F(100000000, P_FEPLL500, 1, 1, 5),
519 F(193000000, DDRC_PLL_666_SDCC, 1, 0, 0), 509 F(193000000, P_DDRPLL, 1, 0, 0),
520 { } 510 { }
521}; 511};
522 512
@@ -536,9 +526,9 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
536 526
537static const struct freq_tbl ftbl_gcc_apps_clk[] = { 527static const struct freq_tbl ftbl_gcc_apps_clk[] = {
538 F(48000000, P_XO, 1, 0, 0), 528 F(48000000, P_XO, 1, 0, 0),
539 F(200000000, FE_PLL_200, 1, 0, 0), 529 F(200000000, P_FEPLL200, 1, 0, 0),
540 F(500000000, FE_PLL_500, 1, 0, 0), 530 F(500000000, P_FEPLL500, 1, 0, 0),
541 F(626000000, DDRC_PLL_666, 1, 0, 0), 531 F(626000000, P_DDRPLLAPSS, 1, 0, 0),
542 { } 532 { }
543}; 533};
544 534
@@ -557,7 +547,7 @@ static struct clk_rcg2 apps_clk_src = {
557 547
558static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = { 548static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
559 F(48000000, P_XO, 1, 0, 0), 549 F(48000000, P_XO, 1, 0, 0),
560 F(100000000, FE_PLL_200, 2, 0, 0), 550 F(100000000, P_FEPLL200, 2, 0, 0),
561 { } 551 { }
562}; 552};
563 553
@@ -940,7 +930,7 @@ static struct clk_branch gcc_usb2_mock_utmi_clk = {
940}; 930};
941 931
942static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 932static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
943 F(2000000, FE_PLL_200, 10, 0, 0), 933 F(2000000, P_FEPLL200, 10, 0, 0),
944 { } 934 { }
945}; 935};
946 936
@@ -1007,7 +997,7 @@ static struct clk_branch gcc_usb3_mock_utmi_clk = {
1007}; 997};
1008 998
1009static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = { 999static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
1010 F(125000000, FE_PLL_125_DLY, 1, 0, 0), 1000 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1011 { } 1001 { }
1012}; 1002};
1013 1003
@@ -1027,7 +1017,7 @@ static struct clk_rcg2 fephy_125m_dly_clk_src = {
1027 1017
1028static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = { 1018static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
1029 F(48000000, P_XO, 1, 0, 0), 1019 F(48000000, P_XO, 1, 0, 0),
1030 F(250000000, FE_PLL_WCSS2G, 1, 0, 0), 1020 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1031 { } 1021 { }
1032}; 1022};
1033 1023
@@ -1097,7 +1087,7 @@ static struct clk_branch gcc_wcss2g_rtc_clk = {
1097 1087
1098static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = { 1088static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
1099 F(48000000, P_XO, 1, 0, 0), 1089 F(48000000, P_XO, 1, 0, 0),
1100 F(250000000, FE_PLL_WCSS5G, 1, 0, 0), 1090 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1101 { } 1091 { }
1102}; 1092};
1103 1093