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authorVivek Gautam <vivek.gautam@codeaurora.org>2019-04-22 03:10:36 -0400
committerWill Deacon <will.deacon@arm.com>2019-04-23 07:23:16 -0400
commitbc580b56cb7888d1f09fff8a50270228fb834ae8 (patch)
treed98cab92214aa7770dad659d7aa27341b5b4b04b
parent3f54c447df34ff9efac7809a4a80fd3208efc619 (diff)
iommu/arm-smmu: Log CBFRSYNRA register on context fault
Bits[15:0] in CBFRSYNRA register contain information about StreamID of the incoming transaction that generated the fault. Dump CBFRSYNRA register to get this info. This is specially useful in a distributed SMMU architecture where multiple masters are connected to the SMMU. SID information helps to quickly identify the faulting master device. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--drivers/iommu/arm-smmu-regs.h2
-rw-r--r--drivers/iommu/arm-smmu.c8
2 files changed, 7 insertions, 3 deletions
diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
index a1226e4ab5f8..e9132a926761 100644
--- a/drivers/iommu/arm-smmu-regs.h
+++ b/drivers/iommu/arm-smmu-regs.h
@@ -147,6 +147,8 @@ enum arm_smmu_s2cr_privcfg {
147#define CBAR_IRPTNDX_SHIFT 24 147#define CBAR_IRPTNDX_SHIFT 24
148#define CBAR_IRPTNDX_MASK 0xff 148#define CBAR_IRPTNDX_MASK 0xff
149 149
150#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
151
150#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) 152#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
151#define CBA2R_RW64_32BIT (0 << 0) 153#define CBA2R_RW64_32BIT (0 << 0)
152#define CBA2R_RW64_64BIT (1 << 0) 154#define CBA2R_RW64_64BIT (1 << 0)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 930c07635956..5e54cc0a28b3 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -570,12 +570,13 @@ static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v1 = {
570 570
571static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 571static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
572{ 572{
573 u32 fsr, fsynr; 573 u32 fsr, fsynr, cbfrsynra;
574 unsigned long iova; 574 unsigned long iova;
575 struct iommu_domain *domain = dev; 575 struct iommu_domain *domain = dev;
576 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); 576 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
577 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; 577 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
578 struct arm_smmu_device *smmu = smmu_domain->smmu; 578 struct arm_smmu_device *smmu = smmu_domain->smmu;
579 void __iomem *gr1_base = ARM_SMMU_GR1(smmu);
579 void __iomem *cb_base; 580 void __iomem *cb_base;
580 581
581 cb_base = ARM_SMMU_CB(smmu, cfg->cbndx); 582 cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
@@ -586,10 +587,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
586 587
587 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); 588 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
588 iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR); 589 iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
590 cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
589 591
590 dev_err_ratelimited(smmu->dev, 592 dev_err_ratelimited(smmu->dev,
591 "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n", 593 "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
592 fsr, iova, fsynr, cfg->cbndx); 594 fsr, iova, fsynr, cbfrsynra, cfg->cbndx);
593 595
594 writel(fsr, cb_base + ARM_SMMU_CB_FSR); 596 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
595 return IRQ_HANDLED; 597 return IRQ_HANDLED;