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authorRex Zhu <Rex.Zhu@amd.com>2016-03-29 06:31:43 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-04-01 10:08:31 -0400
commitbbe6aa9953b2cef7f3a060e8b543a2271d0d5014 (patch)
tree162690c547fee985057751e4483c60e745f67622
parent5349ece70600bd574d9a825801c00f900acda3d4 (diff)
drm/amd/powerplay: add new Fiji function for not setting same ps.
Add comparison function used by powerplay to determine which power state to select. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c63
1 files changed, 63 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 51dedf84623c..a21f58e10d19 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -5195,6 +5195,67 @@ static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5195 return size; 5195 return size;
5196} 5196}
5197 5197
5198static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5199 const struct fiji_performance_level *pl2)
5200{
5201 return ((pl1->memory_clock == pl2->memory_clock) &&
5202 (pl1->engine_clock == pl2->engine_clock) &&
5203 (pl1->pcie_gen == pl2->pcie_gen) &&
5204 (pl1->pcie_lane == pl2->pcie_lane));
5205}
5206
5207int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5208{
5209 const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5210 const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5211 int i;
5212
5213 if (equal == NULL || psa == NULL || psb == NULL)
5214 return -EINVAL;
5215
5216 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5217 if (psa->performance_level_count != psb->performance_level_count) {
5218 *equal = false;
5219 return 0;
5220 }
5221
5222 for (i = 0; i < psa->performance_level_count; i++) {
5223 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5224 /* If we have found even one performance level pair that is different the states are different. */
5225 *equal = false;
5226 return 0;
5227 }
5228 }
5229
5230 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5231 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5232 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5233 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5234 *equal &= (psa->acp_clk == psb->acp_clk);
5235
5236 return 0;
5237}
5238
5239bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5240{
5241 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5242 bool is_update_required = false;
5243 struct cgs_display_info info = {0,0,NULL};
5244
5245 cgs_get_active_displays_info(hwmgr->device, &info);
5246
5247 if (data->display_timing.num_existing_displays != info.display_count)
5248 is_update_required = true;
5249/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5250 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5251 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5252 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5253 is_update_required = true;
5254*/
5255 return is_update_required;
5256}
5257
5258
5198static const struct pp_hwmgr_func fiji_hwmgr_funcs = { 5259static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5199 .backend_init = &fiji_hwmgr_backend_init, 5260 .backend_init = &fiji_hwmgr_backend_init,
5200 .backend_fini = &tonga_hwmgr_backend_fini, 5261 .backend_fini = &tonga_hwmgr_backend_fini,
@@ -5230,6 +5291,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5230 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt, 5291 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5231 .set_fan_control_mode = fiji_set_fan_control_mode, 5292 .set_fan_control_mode = fiji_set_fan_control_mode,
5232 .get_fan_control_mode = fiji_get_fan_control_mode, 5293 .get_fan_control_mode = fiji_get_fan_control_mode,
5294 .check_states_equal = fiji_check_states_equal,
5295 .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5233 .get_pp_table = fiji_get_pp_table, 5296 .get_pp_table = fiji_get_pp_table,
5234 .set_pp_table = fiji_set_pp_table, 5297 .set_pp_table = fiji_set_pp_table,
5235 .force_clock_level = fiji_force_clock_level, 5298 .force_clock_level = fiji_force_clock_level,