diff options
author | Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> | 2016-04-30 08:33:53 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2016-05-03 02:24:16 -0400 |
commit | bb91f8c0176b072aeb6b84cfd7e04084025121e0 (patch) | |
tree | a8eac3f5676531fc7629f04db74ed56b11f2156c | |
parent | 6bda529ec42e1cd4dde1c3d0a1a18000ffd3d419 (diff) |
x86/mce: Carve out writes to MCx_STATUS and MCx_CTL
We need to do this after __mcheck_cpu_init_vendor() as for
ScalableMCA processors, there are going to be new MSR write handlers
if the feature is detected using CPUID bit (which happens in
__mcheck_cpu_init_vendor()).
No functional change is introduced here.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462019637-16474-4-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 43f8b49ef570..6bffb26e05e0 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -1420,7 +1420,6 @@ static void __mcheck_cpu_init_generic(void) | |||
1420 | enum mcp_flags m_fl = 0; | 1420 | enum mcp_flags m_fl = 0; |
1421 | mce_banks_t all_banks; | 1421 | mce_banks_t all_banks; |
1422 | u64 cap; | 1422 | u64 cap; |
1423 | int i; | ||
1424 | 1423 | ||
1425 | if (!mca_cfg.bootlog) | 1424 | if (!mca_cfg.bootlog) |
1426 | m_fl = MCP_DONTLOG; | 1425 | m_fl = MCP_DONTLOG; |
@@ -1436,6 +1435,11 @@ static void __mcheck_cpu_init_generic(void) | |||
1436 | rdmsrl(MSR_IA32_MCG_CAP, cap); | 1435 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1437 | if (cap & MCG_CTL_P) | 1436 | if (cap & MCG_CTL_P) |
1438 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | 1437 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
1438 | } | ||
1439 | |||
1440 | static void __mcheck_cpu_init_clear_banks(void) | ||
1441 | { | ||
1442 | int i; | ||
1439 | 1443 | ||
1440 | for (i = 0; i < mca_cfg.banks; i++) { | 1444 | for (i = 0; i < mca_cfg.banks; i++) { |
1441 | struct mce_bank *b = &mce_banks[i]; | 1445 | struct mce_bank *b = &mce_banks[i]; |
@@ -1717,6 +1721,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) | |||
1717 | 1721 | ||
1718 | __mcheck_cpu_init_generic(); | 1722 | __mcheck_cpu_init_generic(); |
1719 | __mcheck_cpu_init_vendor(c); | 1723 | __mcheck_cpu_init_vendor(c); |
1724 | __mcheck_cpu_init_clear_banks(); | ||
1720 | __mcheck_cpu_init_timer(); | 1725 | __mcheck_cpu_init_timer(); |
1721 | } | 1726 | } |
1722 | 1727 | ||
@@ -2121,6 +2126,7 @@ static void mce_syscore_resume(void) | |||
2121 | { | 2126 | { |
2122 | __mcheck_cpu_init_generic(); | 2127 | __mcheck_cpu_init_generic(); |
2123 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); | 2128 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
2129 | __mcheck_cpu_init_clear_banks(); | ||
2124 | } | 2130 | } |
2125 | 2131 | ||
2126 | static struct syscore_ops mce_syscore_ops = { | 2132 | static struct syscore_ops mce_syscore_ops = { |
@@ -2138,6 +2144,7 @@ static void mce_cpu_restart(void *data) | |||
2138 | if (!mce_available(raw_cpu_ptr(&cpu_info))) | 2144 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
2139 | return; | 2145 | return; |
2140 | __mcheck_cpu_init_generic(); | 2146 | __mcheck_cpu_init_generic(); |
2147 | __mcheck_cpu_init_clear_banks(); | ||
2141 | __mcheck_cpu_init_timer(); | 2148 | __mcheck_cpu_init_timer(); |
2142 | } | 2149 | } |
2143 | 2150 | ||